JPS60223158A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60223158A JPS60223158A JP7926084A JP7926084A JPS60223158A JP S60223158 A JPS60223158 A JP S60223158A JP 7926084 A JP7926084 A JP 7926084A JP 7926084 A JP7926084 A JP 7926084A JP S60223158 A JPS60223158 A JP S60223158A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitter
- base layer
- polycrystalline silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 14
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000003892 spreading Methods 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 description 5
- -1 boron ions Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910001651 emery Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明はバイポーラトランジスタを含む半導体装置の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a method of manufacturing a semiconductor device including a bipolar transistor.
（ロ）従来技術
近年、バイポーラ半導体装置の高速化を図るために、種
々の手段が提案実施されている。例えば、エミツタ層と
エミッタ電極とのパターンズレをなくしてこれらの微細
加工を実現することにより、装置の高速化を図る手段が
ある。(B) Prior Art In recent years, various means have been proposed and implemented in order to increase the speed of bipolar semiconductor devices. For example, there is a means to increase the speed of the device by eliminating pattern misalignment between the emitter layer and the emitter electrode to achieve fine processing.
第１図は前記従来の半導体装置の製造方法を示す説明図
である。FIG. 1 is an explanatory diagram showing the conventional method for manufacturing the semiconductor device.
■Ｎ型基板１にＰ中型の外部ベース層（ｔ！ＸＴＲｌＮ
５ＩＣＢＡＳＥ） ２およびＰ−型の内部ベース層（ｒ
ＮＴＩ？ｌＮ５ＩＣＢＡＳＥ） ３を形成したのち、基
板表面に熱酸化膜４とＣＶＤ ＳｉＯ２５とを形成する
（同図（ａ）参照）
■両者の選択エラチンブト性を利用して、ＣＶＤ５ｉｏ
２５のパターンニングを行う（同図（ｂｌ参照）。■P medium-sized external base layer (t!
5ICBASE) 2 and P-type internal base layer (r
NTI? After forming 1N5ICBASE) 3, a thermal oxide film 4 and CVD SiO25 are formed on the substrate surface (see figure (a)).
25 patterning is performed (see the same figure (bl)).
■基板表面に窒化珪素膜６を成長させ、エミ・ツタ領域
に対応してパターンニングを行い、さらに、これをマス
クとして前記熱酸化膜４をエツチングする。（同図ｔｃ
＋参照）。(2) A silicon nitride film 6 is grown on the surface of the substrate, patterned to correspond to the emitter/vine regions, and then the thermal oxide film 4 is etched using this as a mask. (same figure tc
+Reference).
■Ｎ型不純物をイオン打ち込みして、Ｎ生型のエミツタ
層７を形成する。そして、この基板表面にアルミニウム
などを蒸着して、パターンニングすることによりエミッ
タ電極８を形成する（同図（ｄ））。(2) N-type impurities are ion-implanted to form an N-type emitter layer 7. Then, aluminum or the like is deposited on the surface of this substrate and patterned to form an emitter electrode 8 (FIG. 4(d)).
このように、前述した従来方法は、エミ・ツタ層とその
電極を自己整合によって形成するため、エミッタの微細
加工が可能であり、この意味において半導体装置の高速
化を図る上で一つの有効な手段である。In this way, in the conventional method described above, the emitter layer and its electrode are formed by self-alignment, so it is possible to microfabricate the emitter, and in this sense, it is an effective method for increasing the speed of semiconductor devices. It is a means.
しかしながら、この方法はエミ・ツタ層自身が外部ベー
ス層あるいは内部ベース層に対し自己整合によって形成
されるものでない。したがって、前記窒化珪素膜のパタ
ーンニングにマスクズレが生じると、外部ベース層から
エミツタ層にいたる領域９の不純物濃度が変動する。こ
れにより高周波特性に影響を与える時定数ＣＥＢ−ｒｂ
ｂ ’ （ＣＥＢはエミッターベース間容量、ｒｂｂ’
はヘース拡がり抵抗を意味する）にバラツキを生じ易い
。例えば、高濃度不純物層である外部ベース層とエミツ
タ層とが直接に接するとＣＥＢが大きくなることにより
、一方、外部ベース層９とエミツタ層７の間に内部ベー
ス層３を構成するＰ−Ｆｉが介在するとｒｂｂ“が大き
くなることにより、ともに前記時定数が増大する。その
ため、この方法は時定数Ｃ’ＥＢ −ｒ ｂｂ ’の小
さい装置を容易に製造し難いという意味において、装置
の高速化が困難である。However, in this method, the emery vine layer itself is not formed by self-alignment with the external base layer or the internal base layer. Therefore, if a mask misalignment occurs in the patterning of the silicon nitride film, the impurity concentration in the region 9 from the external base layer to the emitter layer changes. This causes the time constant CEB-rb to affect the high frequency characteristics.
b' (CEB is the emitter-base capacitance, rbb'
(means Heath spreading resistance) tends to vary. For example, if the external base layer, which is a high concentration impurity layer, and the emitter layer are in direct contact with each other, the CEB becomes large. If C'EB-rbb' is present, the above-mentioned time constant increases as rbb' increases.Therefore, this method is difficult to easily manufacture a device with a small time constant C'EB-rbb', so it is difficult to increase the speed of the device. is difficult.
また、前記理由によりｒｂｂ“が大きくなると、これに
伴い雑音が増えるという問題をも生じる。Furthermore, if rbb" increases due to the above-mentioned reason, a problem arises in that noise increases accordingly.
（ハ）目的
この発明に係る半導体装置の製造方法は、装置の高速化
および低雑音化に適した半導体装置の製造方法を提供す
ることを目的としている。(c) Purpose The method of manufacturing a semiconductor device according to the present invention is intended to provide a method of manufacturing a semiconductor device suitable for increasing the speed and reducing noise of the device.
（ニ）構成
この発明に係る半導体装置の製造方法は、バイポーラト
ランジスタを含む半導体装置の製造方法に係り、
多結晶シリコンが成長された基板のエミッタ領域に対応
する部分に、周辺部の膜厚が簿い遮蔽層を形成する工程
と、
前記遮蔽層をマスクとして、該遮蔽層の周辺部を適宜量
の不純物が通過するように、外部ベース層を形成すべき
不純物を打ち込む工程と、前記遮蔽層をマスクとして選
択酸化ＭＱを形成する工程と、
前記遮蔽層を除去し、その下部にある多結晶シリコンを
介して不純物を打ち込み、前記選択酸化膜を利用した自
己整合によって内部ベース層を形成する工程と、
前記多結晶シリコン層に不純物を打ち込み、さらに、前
記不純物を多結晶シリコンから基板内へ拡散させること
により、前記選択酸化膜を利用した自己整合によってエ
ミツタ層を形成する工程と、前記多結晶シリコンをコン
タクトととしてエミッタ電極を自己整合によって形成す
る工程とを具備したことを特徴としている。(D) Structure The method of manufacturing a semiconductor device according to the present invention relates to a method of manufacturing a semiconductor device including a bipolar transistor, and includes a method of manufacturing a semiconductor device including a bipolar transistor, in which a film thickness of a peripheral portion is increased in a portion corresponding to an emitter region of a substrate on which polycrystalline silicon is grown. a step of forming an unbalanced shielding layer; a step of implanting an impurity to form an external base layer using the shielding layer as a mask so that an appropriate amount of impurity passes through the periphery of the shielding layer; a step of forming a selectively oxidized MQ using the mask as a mask; and a step of removing the shielding layer, implanting impurities through the underlying polycrystalline silicon, and forming an internal base layer by self-alignment using the selectively oxidized film. and forming an emitter layer by self-alignment using the selective oxide film by implanting impurities into the polycrystalline silicon layer and further diffusing the impurities from the polycrystalline silicon into the substrate; The method is characterized by comprising a step of forming an emitter electrode by self-alignment using silicon as a contact.
（ホ）実施例
第２図はこの発明に係る半導体装置の製造方法の一実施
例の説明図である。(E) Embodiment FIG. 2 is an explanatory diagram of an embodiment of the method for manufacturing a semiconductor device according to the present invention.
■Ｎ型のシリコン基板１１の表面に多結晶シリコン１２
を成長させ、さらに熱酸化膜１３を形成した後、窒化珪
素膜１４を気相成長させる（同図ｔａ＋参照）。■Polycrystalline silicon 12 on the surface of N-type silicon substrate 11
After growing and further forming a thermal oxide film 13, a silicon nitride film 14 is grown in a vapor phase (see ta+ in the figure).
■エミッタ領域に当たる部分に窒化珪素膜１４を残して
、他をエツチングにより除去する。そして、少なくとも
外部ベース領域に当たる部分および前記窒化珪素膜１４
の周辺部を除いて、基板表面にレジスト１５．１５′を
被着する。したがって、窒化珪素膜１４およびレジスト
１５′はエミッタ領域に対応して形成され、該領域の周
辺部の膜厚を薄くした遮蔽層として作用する。これらの
遮蔽層およびレジスト１５をマスクとしてＰ型不純物と
しての硼素をイオン打ち込みする（同図（ｂ）参照）。(2) The silicon nitride film 14 is left in the portion corresponding to the emitter region, and the rest is removed by etching. At least a portion corresponding to the external base region and the silicon nitride film 14
A resist 15, 15' is applied to the surface of the substrate except for the peripheral area. Therefore, the silicon nitride film 14 and the resist 15' are formed corresponding to the emitter region, and act as a shielding layer with a thinner film thickness at the periphery of the region. Using these shielding layers and the resist 15 as a mask, boron ions as a P-type impurity are implanted (see FIG. 3(b)).
イオン打ち込みの注入エネルギーは膜厚が薄く設定され
た遮蔽層、すなわち、窒化珪素膜１４の周辺部を適宜量
の１ｔｌｌ素イオンが通過する値に設定される。The implantation energy of the ion implantation is set to a value that allows an appropriate amount of 1tll elementary ions to pass through the peripheral portion of the thin shielding layer, that is, the silicon nitride film 14.
■前記レジスト１５．１５′を除去したのち、窒化珪素
膜１４をマスクとして基板１１を熱処理し、選択酸化膜
１６を形成する。このとき、遮蔽層のない部分に打ち込
まれた高濃度の硼素イオンが拡散されＰ生型の外部ベー
ス層１７を形成する。一方、窒化珪素膜１４の周辺を通
過して打ぢ込まれた中濃度の硼素イオンが拡散されて中
濃度不純物領域であるＰ領域律を形成する（同図（Ｃ）
参照）。Ｐ＠域１８の内側端縁は拡散時の槽数がりによ
り多結晶シリコン１２０周辺に接する程度に前記熱処理
の温度条件が設定される。(2) After removing the resists 15 and 15', the substrate 11 is heat-treated using the silicon nitride film 14 as a mask to form a selective oxide film 16. At this time, the highly concentrated boron ions implanted into the portion where there is no shielding layer are diffused to form a P-type external base layer 17. On the other hand, medium-concentration boron ions implanted through the periphery of the silicon nitride film 14 are diffused to form a P region, which is a medium-concentration impurity region (see (C) in the same figure).
reference). The temperature conditions for the heat treatment are set such that the inner edge of the P@ region 18 touches the periphery of the polycrystalline silicon 120 due to the increase in the number of tanks during diffusion.
■窒化珪素膜１４及び熱酸化膜１３を除去した後、多結
晶シリコン１２を介してＰ型不純物としての硼素のイオ
ン打ち込みを行い、選択酸化膜１６を利用した自己整合
によってＰ−型の内部ベース層１９を形成する（同図（
ｄｌ参照）。■After removing the silicon nitride film 14 and the thermal oxide film 13, boron ions are implanted as a P-type impurity through the polycrystalline silicon 12, and a P-type internal base is formed by self-alignment using the selective oxide film 16. Form layer 19 (see figure (
dl).
■Ｎ型不純物としての例えば砒素を多結晶シリコン１２
中にイオン打ち込みし、ざらに、熱処理によって前記多
結晶シリコン１２から基板ＩＩへ砒素の拡散を行うこと
により、選択酸化膜１６を利用した自己整合によってＮ
生型のエミツタ層２０を形成する（同図ｔｅｌ参照）。■As an N-type impurity, for example, arsenic is added to polycrystalline silicon 12
Arsenic is diffused from the polycrystalline silicon 12 to the substrate II by ion implantation into the substrate II, and then by rough heat treatment to diffuse arsenic from the polycrystalline silicon 12 to the substrate II.
A green emitter layer 20 is formed (see tel in the figure).
同図より明らかなように、外部ベース層１７とエミッタ
Ｎ１９との間にＰ領域１８が介在する。As is clear from the figure, P region 18 is interposed between external base layer 17 and emitter N19.
■Ｐ＋のコンタクト孔を形成する工程を経た後、基板表
面にアルミニウム等の金属層を蒸着形成し、フォトエツ
チングによりエミッタ電極２Ｉを形成する（同図ｆｆｌ
参照）。このとき、多結晶シリコン１２はエミツタ層１
９を形成する際のイオン打ち込みによってＮ生型を呈し
ているので、いわゆるエミッタコンタクトととして機能
する。■After the process of forming a P+ contact hole, a metal layer such as aluminum is deposited on the surface of the substrate, and an emitter electrode 2I is formed by photoetching (ffl in the same figure).
reference). At this time, the polycrystalline silicon 12 is
Since the ion implantation during the formation of 9 gives it an N-type appearance, it functions as a so-called emitter contact.
なお、上述の実施例では遮蔽層として、窒化珪素膜１４
および前記窒化珪素膜１４の周辺部を除いて被着された
レジスト１５′により形成されるとして説明した。しか
し、この発明はこれに限られるものでなく、例えば、エ
ミッタ領域の周辺部の遮蔽層の膜厚を薄（する手段とし
ては、比較的厚く成長させた窒化珪素膜の周辺をエツチ
ングにより薄く形成するものであってもよい。Note that in the above embodiment, the silicon nitride film 14 is used as the shielding layer.
In the above description, the resist 15' is formed except for the peripheral portion of the silicon nitride film 14. However, the present invention is not limited thereto; for example, the thickness of the shielding layer around the emitter region may be reduced by etching the periphery of a relatively thick silicon nitride film. It may be something that does.
（へ）効果
この発明に係る半導体装置の製造方法は、外部ベース層
に対し内部ベース層およびエミツタ層を自己整合によっ
て形成し、しかも、エミッタ領域に覆う遮蔽層の周辺部
を薄くすることにより、外部ベース層のイオン打ち込み
と同時に前記周辺部の下部ににも適宜のイオン打ら込み
を行い、外部ベース層とエミツタ層との間に中間不純物
層を積極的に形成しでいる。したがって、この発明によ
れば、外部ベース層とエミツタ層とが直接に接すること
がないから、工程条件等の多少の変動によってＣＥＢが
大きくなることはない。また、同旨より、外部ベース層
とエミツタ層の間に内部ベース層を構成する低濃度不純
物層が介在することもないので、ｒｂｂ’が大きくなる
ことも防止できる。(f) Effect The method for manufacturing a semiconductor device according to the present invention forms an internal base layer and an emitter layer with respect to an external base layer by self-alignment, and furthermore, by thinning the peripheral part of the shielding layer covering the emitter region, At the same time as the ion implantation of the external base layer, appropriate ion implantation is also performed in the lower part of the peripheral portion to actively form an intermediate impurity layer between the external base layer and the emitter layer. Therefore, according to the present invention, since the external base layer and the emitter layer do not come into direct contact with each other, the CEB does not increase due to slight variations in process conditions. Furthermore, since the low concentration impurity layer constituting the internal base layer is not interposed between the external base layer and the emitter layer, it is also possible to prevent rbb' from increasing.
上述したことから、この発明によれば時定数ＣＥＢ−ｒ
ｂｂ’を小さく維持できるので、半導体装置の高速化を
実現することができる。From the above, according to the present invention, the time constant CEB-r
Since bb' can be kept small, the speed of the semiconductor device can be increased.
また、この発明は、エミツタ層とエミッタ電極を自己整
合によって形成しているので、エミッタ構造の微細加工
が可能である。この理由からもこの発明は半導体装置の
高速化に適したものである。Further, in the present invention, since the emitter layer and the emitter electrode are formed by self-alignment, fine processing of the emitter structure is possible. For this reason as well, the present invention is suitable for increasing the speed of semiconductor devices.
さらに、この発明によればｒ ｂｂ ’を小さくできる
から、該半導体装置の雑音を少なくすることができる。Furthermore, according to the present invention, since r bb ' can be reduced, the noise of the semiconductor device can be reduced.
第１図は従来の半導体装置の製造方法の説明図、第２図
はこの発明に係る半導体装置の製造方法の一実施例の説
明図である。
１１・・・基板、１２・・・多結晶シリコン、１３・・
・熱酸化膜、１４・・・窒化珪素膜、１６・・・選択酸
化膜、１７・・・外部ベース層、Ｉ８・・・Ｐ領域、１
９・・・内部ベース層、２０・・・エミツタ層、２１・
・・エミッタ電極。FIG. 1 is an explanatory diagram of a conventional method for manufacturing a semiconductor device, and FIG. 2 is an explanatory diagram of an embodiment of the method for manufacturing a semiconductor device according to the present invention. 11...Substrate, 12...Polycrystalline silicon, 13...
- Thermal oxide film, 14... Silicon nitride film, 16... Selective oxide film, 17... External base layer, I8... P region, 1
9... Internal base layer, 20... Emitter layer, 21.
...Emitter electrode.
Claims (1)
方法において、 多結晶シリコンが成長された基板のエミッタ領域に対応
する部分に、周辺部の膜厚が薄い遮蔽層を形成する工程
と、 前記遮蔽層をマスクとして、該遮蔽層の周辺部を適宜量
の不純物が通過するように、外部ベース層を形成すべき
不純物を打ち込む工程と、前記遮蔽層をマスクとして選
択酸化膜を形成する工程と、 前記遮蔽層を除去し、その下部にある多結晶シリコンを
介して不純物を打ら込み、前記選択酸化膜を利用した自
己整合によって内部ベース層を形成する工程と、 前記多結晶シリコン層に不純物を打ち込み、さらに、前
記不純物を多結晶シリコンから基板内へ拡散させること
により、前記選択酸化膜を利用した自己整合によってエ
ミツタ層を形成する工程と、前記多結晶シリコンをコン
タクトととしてエミッタ電極を自己整合によって形成す
る工程とを具備したことを特徴とする半導体装置の製造
方法。(1) A method for manufacturing a semiconductor device including a bipolar transistor, which includes the steps of: forming a shielding layer with a thin peripheral portion in a portion corresponding to an emitter region of a substrate on which polycrystalline silicon is grown; a step of implanting an impurity to form an external base layer so that an appropriate amount of impurity passes through the peripheral portion of the shielding layer as a mask; a step of forming a selective oxide film using the shielding layer as a mask; removing the layer, implanting an impurity through the polycrystalline silicon layer below the layer, and forming an internal base layer by self-alignment using the selective oxide film; implanting the impurity into the polycrystalline silicon layer; Furthermore, by diffusing the impurity from the polycrystalline silicon into the substrate, an emitter layer is formed by self-alignment using the selective oxide film, and an emitter electrode is formed by self-alignment using the polycrystalline silicon as a contact. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59079260A JPH0691097B2 (en) | 1984-04-18 | 1984-04-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59079260A JPH0691097B2 (en) | 1984-04-18 | 1984-04-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60223158A true JPS60223158A (en) | 1985-11-07 |
| JPH0691097B2 JPH0691097B2 (en) | 1994-11-14 |
Family
ID=13684882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59079260A Expired - Fee Related JPH0691097B2 (en) | 1984-04-18 | 1984-04-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691097B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63261748A (en) * | 1987-04-17 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS63261749A (en) * | 1987-04-17 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5310979A (en) * | 1976-07-16 | 1978-01-31 | Mitsubishi Electric Corp | Semiconductor device and its production |
-
1984
- 1984-04-18 JP JP59079260A patent/JPH0691097B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5310979A (en) * | 1976-07-16 | 1978-01-31 | Mitsubishi Electric Corp | Semiconductor device and its production |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63261748A (en) * | 1987-04-17 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS63261749A (en) * | 1987-04-17 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0691097B2 (en) | 1994-11-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |