JPS58110076A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the high frequency characteristics of the titled semiconductor device by a method wherein a ring-shaped graft base region is formed on the semiconductor substrate which will be turned to a collector region, a thick oxide film is generated thereon by performing a heat treatment, and an emitter region is provided at the vacant space located in the center of the ring-shaped part, thereby enabling to reduce the irregularity in size. CONSTITUTION:An SiO2 film 11a is coated on the N type Si substrate 10 which will be used as the collector region of an NPN transistor, and an Si3N4 film 12 is formed in the center of said film 11a aparting from an Si3N4 film 12a and surrounding the film 12a. Then, an ion is implanted using the films 12 and 12a, and after a ring-shaped P<+> type graft base region 13 has been formed in the substrate 10, a heat treatment is performed in an N2 atmosphere and an O2 atmosphere, and a pressing diffusion is performed on the region 13. On this region 13, a thick SiO2 film is generated, and an SiO2 film 11c is generated on the films 12 and 12a. Subsequently, a resist film 14 is provided while the inside of the ring-shaped base region 13 is being exposed, the film 12a is removed together with the film 11c located above the film 12a by performing an etching, an N type layer 15 is grown here, and an N type emitter region 15a is formed in the layer 15.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a bipolar transistor with excellent high frequency characteristics suitable for integrated circuits.

In recent years, in order to realize bipolar transistors with excellent high frequency characteristics and integrated circuits using said transistors, N
It is common practice to form the emitter region of a PN transistor into a mesa structure. FIG. 1 shows the structure of this type of transistor and its simple manufacturing method.

In the process diagram of FIG. 1, first, in step (,), a P-type base region 2 and a shallow N+ layer 3 doped with arsenic are formed by diffusion in an oxygen atmosphere on the surface of an N-type silicon substrate 1 that will become a collector region. do. After etching and removing the silicon oxide film on the N+ layer 3 remaining after the above-mentioned N+ layer formation diffusion treatment, a silicon oxide film 4 is deposited on the collector region 1 and the base region 2 by CVD or the like over the entire surface.
Then, a silicon nitride film 6 and a polycrystalline silicon film 6 are deposited. Then, a predetermined photoresist pattern 7 is provided on the outermost part.

In step (b), the surface of the polycrystalline silicon film 6 is formed using the positive photoresist pattern 7, such as product name 0FPR-800, formed by a conventional method as a mask.
After etching the polycrystalline silicon film 6 and removing the photoresist pattern 7, the silicon nitride film 5 immediately below is etched with hot phosphoric acid using the polycrystalline silicon film 6a of the same shape as a mask. , a silicon nitride film 6a having the same shape is formed.

In step (C), the N+ layer 3 is etched using the silicon nitride film 6a as a mask to form an N+ type emitter region 3a. During this etching process, the polycrystalline silicon film 6a above the mask is also etched away.

In step (d), the exposed surfaces of the P type base region 2 and the N+ type emitter region 3a are selectively oxidized in an oxidizing atmosphere at a temperature of about 900° C. to form a silicon oxide film 4a on the surface.

In the conventional method shown in FIG. 1 above, the arsenic concentration added to the N"43 is 1×
The etching rate of this layer 3 is as high as about 1octn, and the etching rate of this layer 3 is significantly higher than that of ordinary single crystal silicon. Therefore, when etching the N+ layer 3 to form the N-type emitter region 3a, when etching with a hydrofluoric acid solution, the undercut i with respect to the silicon nitride film 5, which is a mask, is large, and the emitter region 3 is etched. Control and reproducibility of pattern dimensions and shapes are poor, and the manufacturing process described above is
It is difficult to determine the end point of the etching of the N+ layer 3, and therefore there is a problem in that the electrical characteristics, particularly the high frequency characteristics such as the cut-off frequency, vary widely.

An object of the present invention is to provide a bipolar transistor manufacturing method that solves the above problems. .

In the present invention, a silicon nitride film formed directly or through an oxide film on the surface of a semiconductor substrate is selectively etched into an annular shape to separate it into an inner island-like part and an outer part, and then the silicon nitride film is separated into an inner island-like part and an outer part. A step of implanting impurity ions that give a conductivity type opposite to that of the substrate into the silicon substrate under selective etching using as a mask to form a certain region, silicon nitride remaining in the inner island-like portion A step of removing the silicon nitride film and the silicon oxide film immediately below to expose the semiconductor substrate surface, forming an epitaxial layer of the same conductivity type on the exposed semiconductor substrate portion, and then forming an epitaxial layer below the epitaxial layer. Alternatively, a method for manufacturing a semiconductor device includes a step of converting the top portion of the semiconductor substrate into a layer of an opposite conductivity type.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be explained in detail by way of examples and with reference to the drawings.

In FIG. 2, (a) to (f) show a method for manufacturing a bipolar integrated circuit, which is an embodiment of the present invention.

In step (a), the silicon oxide film 11a is grown to a thickness of about 300 to 6008 by thermally oxidizing the N-type silicon substrate 1o, which will become the collector region of the 1dNPN) transistor, in an oxidizing atmosphere. The silicon nitride film 12 is deposited with a film thickness of 6,000 to 80
0FP is formed by vapor deposition, and then, for example, the product name is 0FP.
1. of R-Boo etc. Using the positive photoresist film pattern as a mask, the silicon nitride film 12 is selectively removed in an annular manner by plasma dry etching to form an island portion 12a.

In step 0)), using the silicon nitride film 12.12a as a mask, an implantation energy of 60% is applied by ion implantation.
KeV, boron ions are implanted at a dose of about IX'10 crn to form a P+ layer 13 that will become a P-type base contact region (P-type graft base region), and then in a nitrogen atmosphere at a temperature of about 860 to 90°C. This is a step of annealing at a temperature of about 900 to 960° C. and then oxidizing it for about 100 minutes in an oxidizing atmosphere at a temperature of about 900 to 960°C. In addition to this, the above P
``In the region M113, oxidation progresses with diffusion, and a silicon oxide film 11b with a thickness of about 3000 to 4000 Å is formed.At the same time, a part of the silicon nitride films 12 and 12a is also oxidized by about 200 to 1000 Å, forming a silicon oxide film. 11c is formed, and the difference in thickness between the silicon nitride film 12.degree. 12a and the thick silicon oxide film 11b on the P+ layer 13 becomes sufficiently large.

In step (0) e (d), using the photoresist pattern 14 as a mask, the silicon nitride film 12a and the thin silicon oxide films 11a and 11c around the interlayer are removed by etching with a hydrofluoric acid solution to selectively remove the silicon nitride film 12a and the thin silicon oxide films 11a and 11c around the interlayer. 1o and a portion of the P+#13 are exposed. , 1 This gives us
Silicon oxide films 11a and 11b are formed except for part of the silicon substrate 1o and the P+ layer 13.

11c and a silicon nitride film 12.

In step (,), the substrate silicon 1o and the P+
An N-type epitaxial layer 15 of about 5,000 to 7,000 layers is selectively grown on a portion of the layer 13 by a low-pressure epitaxial growth method. The growth conditions were as follows: dichlorosilane (SiH2CR2) was used as the reaction gas, and the growth rate was 0.
5-1. oμm/min, growth temperature 1050-1
The temperature during growth was approximately 100° C. and the pressure during growth was approximately 80 Torr. As a result, the N-type epitaxial layer 16 selectively grows only on the exposed silicon surface.

In step (f), one layer 15 which is an N-type high concentration emitter region is formed in the N-type epitaxial layer 16 using the silicon oxide film 11b and the silicon nitride film 12 as masks.
a was implanted by ion implantation at an implantation energy of 40 KeV.
, arsenic ions are implanted at a dose of about 6×1 ocrn, and then diffused in a nitrogen atmosphere at a temperature of 960 to 100°C.

Next, 1, a P-type base region P is formed below the N-type epitaxial layer or at the top of the silicon substrate 1o.
One layer 16 is implanted using an ion implantation method with an implantation energy of 140
Boron ions are implanted at -160 KeV at a dose of about 1x1 or In, and annealed for 30 minutes at a temperature of about 900 DEG C. in a nitrogen atmosphere.

As explained above, if the method for manufacturing a bipolar integrated circuit according to the present invention is used, there is no need to etch heavily doped silicon such as the N+ layer 3 in the emitter region in the conventional example shown in FIG. This results in pattern dimensions of the emitter area.

Since variations in shape are eliminated, variations can be reduced when controlling the emitter dimensions and high frequency characteristics of transistors. Further, according to the present invention, there are thin silicon nitride films 11a and 11c directly under and around the silicon nitride film 12a to be removed by dry etching.
Since this silicon nitride film 12a serves as a stopper during plasma dry etching, the end point of the dry etching can be easily controlled.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view of an element showing a conventional method for forming a bipolar transistor with a mesa structure emitter region, and FIG. 2 is an embodiment of the present invention, in which a bipolar transistor with a mesa structure is formed. FIG. 3 is a cross-sectional view of an element showing a method of forming the element in the order of manufacturing steps. 1, 1o---N-type silicon substrate, 2,13°1
60...P type base region, 35ees...1 layer, 3
a. 151 mmmmmm l'J W :X-mitter area, 4, 4a, 11a. 1 lb, 11068m-e silicon oxide film, 5
．． 5a, 12°12a...0 silicon nitride film, 60
...Polycrystalline silicon film, 7,14...e@O photoresist film pattern, 16...■ N-type epitaxial layer. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure fJ1 Figure 1

Claims (1)

[Claims] A silicon nitride film formed directly or via an oxide film on the surface of a semiconductor substrate is selectively etched into an annular shape to separate it into an inner island-shaped portion and an outer portion, and then the silicon nitride film is used as a mask. A step of implanting impurity ions that give a conductivity type opposite to that of the substrate into the silicon substrate under the selective etching to form a predetermined region, and remaining in the inner island-shaped portion of the selective etching. a step of exposing the semiconductor substrate surface by removing the silicon nitride film or the silicon nitride film and the silicon nitride film immediately below the silicon nitride film, and a step of forming an epitaxial layer of the same conductivity type on the exposed semiconductor substrate portion. A method for manufacturing a semiconductor device, comprising the steps of: converting a layer below the epitaxial layer or a top portion of the semiconductor substrate into a layer of an opposite conductivity type.