JP3139235B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a high-speed and high-density bipolar transistor is integrated, and more particularly to a method of miniaturizing an active region by disposing an emitter electrode and further a base electrode on an element isolation region. The present invention relates to a manufacturing method capable of forming an emitter width by a state-of-the-art fine processing technique in the same manner as a gate electrode of a MOS transistor.

[0002]

2. Description of the Related Art In the field of silicon semiconductor bipolar technology, it has become common to use polysilicon (polycrystalline silicon) as a fine wiring material or a diffusion source for a shallow junction. As a method for forming an emitter region having a fine planar dimension, electrode extraction using polysilicon has become an indispensable technique.

As a conventional semiconductor device, a structure in which a structure called a single-layer polysilicon self-aligned type applied particularly to a high-speed and high-density bipolar transistor is applied to a type in which an emitter electrode is extended over an element isolation region. This will be described below.

FIG. 5A is a plan view of the conventional single-layer polysilicon self-aligned NPN transistor.
(B) is a sectional view taken along a broken line HH 'in the plan view (a), and (c) is a sectional view taken along a broken line YY' in the plan view (a).

In FIG. 1, reference numeral 30 denotes a separation area,
1 is a base region, 32 is a collector region, 3
3 is an emitter region. 34 is a base electrode, 3
5 is a collector electrode and 36 is an emitter electrode.

[0006] In the conventional wall-emitter type self-aligned NPN transistor configured as described above, the N ⁺ -type diffusion layer 33 (emitter region) formed by impurity diffusion from the polycrystalline silicon film 37.
Are characterized by being surrounded in three directions by an isolation region 30 (thermal oxide film) formed therearound. In this case, since there is no margin between the emitter and the separation, the transistor size can be reduced.
In addition, since the three directions of the side surface of the emitter diffusion layer are surrounded by the thermal oxide film, the parasitic capacitance between the emitter and the base can be reduced. Therefore, this electrode lead-out type structure can realize high-density and high-speed transistor operation.

[0007]

However, in such a conventional wall-emitter type single-layer polysilicon self-aligned NPN transistor, the N formed by impurity diffusion from the polycrystalline silicon film 37 is used.
^{In the} P-type diffusion layer 31 (base region) formed immediately below the ⁺ -type diffusion layer 33 (emitter region), boron forming this diffusion layer is absorbed by the thermal oxide film.
At the boundary with the thermal oxide film, a thinning of the base layer 39 occurs.
At this time, the breakdown voltage between the N ⁺ -type diffusion layer 33 (emitter region) and the N ⁻ -type epitaxial layer 32 (collector region) tends to decrease, and the yield of the transistor decreases. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides a method of manufacturing a semiconductor device having a single-layer polysilicon self-aligned structure, which suppresses a decrease in withstand voltage between an emitter region and a collector region. The purpose is to provide.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, a step of forming an element isolation insulating film serving as an element isolation region on a collector region;
Forming a semiconductor film, patterning the first semiconductor film so as to enter the base region from the element isolation insulating film, and ionizing the base region and the emitter region using the first semiconductor film as a mask. Forming by using implantation, depositing a second semiconductor film for an emitter extraction electrode on the semiconductor substrate on which the base region is formed, and forming at least the emitter region excluding the second semiconductor film pattern. A part is selectively removed, and the second
Leaving the emitter region directly below the semiconductor film pattern, leaving a sidewall on the side surface of the emitter region, and ion-implanting the sidewall and the second semiconductor film pattern as a mask to perform external ion implantation. Forming a base region and connecting the external base region to the base region.

In the present invention, it is preferable that the emitter extraction electrode is extended to an element isolation region.

In the present invention, it is preferable that the first semiconductor film that has entered the base region is used as a base extraction electrode, and is extracted onto the element isolation region.

Further, the present invention provides a semiconductor device, comprising:
It is desirable to form a semiconductor film to be a gate electrode of a MOS transistor at the same time as the step of forming the semiconductor film.

[0013]

According to the present invention, the distance between the element isolation insulating film, the base region and the emitter region is kept constant by the above structure, and boron is not absorbed into the thermal oxide film. No thinning of the base layer occurs. Therefore, the breakdown voltage between the emitter region and the collector region hardly decreases, and the yield of the transistor increases.

Further, by forming the structure in which the emitter electrode is drawn out to the isolation region and the external base region is etched, the emitter width can be reduced, and the junction capacitance between the emitter and the base can be reduced.

Further, by forming polysilicon for the base electrode at the boundary between the isolation region and the emitter region and drawing it out onto the isolation region, the base region is reduced, and the emitter / collector structure is further improved while having a walled emitter structure. It is possible to prevent a decrease in withstand voltage during the operation.

Also, by leaving polycrystalline silicon of a gate electrode formed in a MOS transistor manufacturing process as a dummy pattern at the boundary between the isolation region and the emitter region, the breakdown voltage between the emitter and the collector can be reduced while having a walled emitter structure. The drop can be prevented.

[0017]

(Embodiment 1) A first embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a process sectional view showing each manufacturing process of a bipolar semiconductor device according to a first embodiment of the present invention. FIG. 1 is a sectional view taken along a broken line YY ′ in FIG. 5A.

First, in FIG. 1A, the specific resistance of a silicon single crystal is shown.
N-type embedded semiconductor region in P-type substrate of 1 to 10 ohm.cm
Area 1 dose 10¹⁴-10^Fifteencm^{ー 2}Arsenic ion injection
Formed by implantation method and about
N-type half to be a first semiconductor region having a thickness of 1.3 microns
A conductive region is formed, and the N-type well region 2 is dosed at a dose of 10
¹²-10¹³cm^{ー 2}Formed by ion implantation of phosphorus
Furthermore, the surface of the epitaxial layer is subjected to LOCO by thermal oxidation.
Selective oxidation of about 500 nanometers by S method
Therefore, the element isolation film 3 is formed. Furthermore, the film thickness is about 3
A silicon oxide film of 0 nanometer is formed, and on this oxide film
To the collector wall using the resist pattern as a mask
N-type semiconductor region 4 having a dose amount of 10^Fifteen-10¹⁶cm^{ー 2}
Is formed by a phosphorus ion implantation method. Further active area
Remove the oxide film on the top and remove the gate acid for the MOS transistor.
Oxide film 5 is formed by thermal oxidation, and poly
Silicon 6 is deposited by a CVD method.

Next, in FIG. 1B, a gate polysilicon 6 is formed in an active region other than the collector region of the bipolar transistor by a resist pattern 7 for etching the gate electrode of the MOS transistor so as to enter the inside of the isolation oxide film.
Is etched.

Next, in FIG. 1C, using the resist pattern 16 in which only the active region other than the collector region is opened as a mask, a P-type semiconductor region 8 serving as a base is exposed to a dose of 10 ¹³ -1.
It is formed by a boron ion implantation method of 0 ¹⁴ cm ^-2 .

Next, the resist pattern shown in FIG.
After removal, emitter polysilicon 9 is deposited. FIG. 1d
Then, after depositing the polysilicon 9 with a thickness of, for example, 300 nanometers, the same resist 16 as that of FIG.
It was done. After the resist 16 is deposited, a dose of 10
Arsenic of 15 to 1016 cm-2 is introduced by ion implantation.

Next, in FIG. 1E, a resist pattern 10 for defining an intrinsic operation region of the bipolar transistor is deposited, the polysilicon 9 is etched, and silicon etching of the active region is further performed to form a P-type portion for a portion serving as an external base region. Most of the semiconductor region is removed, and an N-type residual semiconductor region 11 serving as an emitter is left under the polysilicon electrode.

Next, in FIG. 1F, after removing the resist 10, the silicon is removed.
Depositing a silicon oxide film with a thickness of, for example, 150 nanometers,
The side wall 19 is formed by anisotropic etching.
Further, a P-type half which becomes an external base region after forming the resist 16
Conductor region 13 with dose amount 10 ^Fifteen-10¹⁶cm^{ー 2}Boron
Formed by the ion implantation method. This allows
The breakdown voltage between the emitter area and the collector area decreases.
And the yield of transistors increases.

Next, in FIG. 1g, after removing the resist 16, the BP is removed.
After the insulating film 12 such as SG is deposited on the entire surface, for example, 85
The surface is flattened by heat treatment at 0 ° C. for 30 minutes. Thereafter, when the metal wirings 14 and 15 are formed, a semiconductor device having a structure as shown in FIG. 1G is obtained.

As described above, according to the present embodiment, the distance between the element isolation insulating film and the base region and the emitter region is kept constant, and boron is not absorbed by the thermal oxide film. No thinning of the base layer occurs at the boundary. Therefore, the breakdown voltage between the emitter region and the collector region hardly decreases, and the yield of the transistor increases. Further, by forming the structure in which the emitter electrode is extended to the isolation region and the external base region is etched, the emitter width can be reduced, and the junction capacitance between the emitter and the base can be reduced. In addition, a polycrystalline silicon of a gate electrode formed in a MOS transistor manufacturing process is left as a dummy pattern at a boundary portion between an isolation region and an emitter region, thereby preventing a reduction in withstand voltage between an emitter and a collector while having a walled emitter structure. can do.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to FIG.

FIG. 2 is a sectional view showing a process in each manufacturing step of a bipolar semiconductor device according to a second embodiment of the present invention. FIG. 2 is a cross-sectional view taken along a broken line YY ′ in FIG. 5A. 1A and 1B are the same as the process cross-sectional views of the respective manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

As in the first embodiment, after the steps shown in FIGS. 1A and 1B, in FIG. 2A, the resist pattern 16 having an opening only in the active region other than the collector region is left in the active region of the transistor using the resist pattern 16 as a mask. The silicon oxide film 5 is removed by etching.

Next, in FIG. 2B, after removing the resist 16, a silicon thin film 17 of, for example, 30 nanometers is deposited. After the formation of the resist 16, the N-type semiconductor region 11 for forming the emitter is subjected to a dose of 10 ¹⁵ to 10 ¹⁶ with energy such that it overtakes the silicon thin film 17 of 30 nm.
It is formed by arsenic ion implantation of cm ^-2 . Further, the P-type semiconductor region 8 serving as a base is dosed at a dose of 10
^{13-10 14} formed by ion implantation of boron cm ^-2.

Next, in FIG. 2C, after removing the resist 16, a polysilicon 18 is deposited to a thickness of, for example, 300 nanometers. After the resist 16 is formed, the arsenic dose of 10 ¹⁵ to 10 ¹⁶ cm ^-2 is introduced by ion implantation into the poly silicon for the emitter electrode lead-out.

Next, in FIG. 2D, a resist pattern 10 for defining the intrinsic operation region of the bipolar transistor is deposited, the polysilicon 18 is etched, and the active region is subjected to silicon etching. Most of the semiconductor region is removed, and an N-type residual semiconductor region serving as an emitter is left under the polysilicon electrode.

Next, in FIG. 2E, after removing the resist 10, a silicon oxide film is deposited to a thickness of, for example, 150 nanometers, and a side wall 19 is formed by anisotropic etching. Further, after the formation of the resist 16, a P-type semiconductor region 13 serving as an external base region is formed by boron ion implantation at a dose of 10 ¹⁵ to 10 ¹⁶ cm ⁻² . This makes it difficult for the breakdown voltage between the emitter region and the collector region to decrease, thereby increasing the yield of the transistor.

Next, in FIG. 2F, an insulating film 1 such as BPSG is formed.
After 2 is deposited on the entire surface, the surface is flattened by, for example, heat treatment at 850 ° C. for 30 minutes. Then, each metal wiring 1
By forming 4 and 15, a semiconductor device having a structure as shown in FIG. 2f is obtained.

In this embodiment, the same effects as in the first embodiment can be obtained. (Embodiment 3) Hereinafter, a third embodiment of the present invention will be described with reference to FIG.
It will be described based on.

FIG. 3 is a process sectional view of each manufacturing process of the bipolar semiconductor device according to the second embodiment of the present invention. FIG. 3 is a sectional view taken along a broken line YY ′ in FIG. 5A. 1A and 1B are the same as the process cross-sectional views of the respective manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

As in the first embodiment, after the steps shown in FIGS. 1A and 1B, in FIG. 3A, for example, a silicon thin film 17 of, for example, 30 nm is deposited, and an active region serving as an emitter region is resisted in consideration of a matching margin. Using a resist pattern 20 having an opening larger than the pattern 10 as a mask, an N-type semiconductor region 21 for forming an emitter is formed with an energy such as to overtake a silicon thin film of 30 nanometers with a dose of 10 ¹⁵ to 10 ¹⁶ cm ⁻² . It is formed by arsenic ion implantation. Further the N-type semiconductor region 22 serving as a buried collector layer overtake 30 nanometer silicon thin film, by N-type dose 10 ¹⁵ to 10 ¹⁶ cm ^over the ion implantation of ² phosphorus at high energy, such as to reach the buried layer 1 Form.

Next, in FIG. 3B, after the resist 20 is removed, the P-type semiconductor region 8 serving as the base is used as a mask by using the resist pattern 16 in which only the active region other than the collector region is opened as a mask, overtaking the silicon thin film of 30 nanometers. energy at formed by a dose of 10 ¹³ to 10 ¹⁴ cm ^-2 of ion implantation of boron.

Next, in FIG. 3C, after removing the resist 16, a polysilicon 18 is deposited to a thickness of, for example, 300 nanometers. After the resist 16 is formed, the arsenic dose of 10 ¹⁵ to 10 ¹⁶ cm ^-2 is introduced by ion implantation into the poly silicon for the emitter electrode lead-out.

Next, in FIG. 3D, a resist pattern 10 for defining the intrinsic operation region of the bipolar transistor is deposited, the polysilicon 18 is etched, and the silicon is etched in the active region. Most of the semiconductor region is removed, and an N-type residual semiconductor region serving as an emitter is left under the polysilicon electrode.

Next, in FIG. 3E, after removing the resist 10, a silicon oxide film is deposited to a thickness of, for example, 150 nanometers. After the formation of the resist 16, the side wall 19 is formed by anisotropic etching. Further, a P-type semiconductor region 13 serving as an external base region is formed by boron ion implantation at a dose of 10 ¹⁵ to 10 ¹⁶ cm ⁻² . This makes it difficult for the breakdown voltage between the emitter region and the collector region to decrease, thereby increasing the yield of the transistor.

Next, in FIG. 3F, after the resist 16 is removed, B
After an insulating film 12 such as PSG is deposited on the entire surface,
The surface is flattened by a heat treatment at 50 ° C. for 30 minutes. Thereafter, when the metal wirings 14 and 15 are formed, a semiconductor device having a structure as shown in FIG. 3F is obtained.

In this embodiment, the SI
Since a collector high-concentration layer called C (Selectivity Ion implanted Collector) can be formed, expansion of the base width can be suppressed, and high-frequency characteristics of the bipolar transistor can be improved.

In this embodiment, the same effects as in the first embodiment can be obtained. (Embodiment 4) Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG.
It will be described based on.

FIG. 4 is a process cross-sectional view of each manufacturing process of the bipolar semiconductor device according to the second embodiment of the present invention. FIG. 4 is a cross-sectional view taken along a broken line YY ′ in FIG. 6A.

First, in FIG. 4A, the specific resistance of the silicon single crystal is shown.
N-type embedded semiconductor region in P-type substrate of 1 to 10 ohm.cm
Area 1 dose 10¹⁴-10^Fifteencm^{ー 2}Arsenic ion injection
Formed by implantation method and about
N-type half to be a first semiconductor region having a thickness of 1.3 microns
A conductive region is formed, and the N-type well region 2 is dosed at a dose of 10
¹²-10¹³cm^{ー 2}Formed by ion implantation of phosphorus
Furthermore, the surface of the epitaxial layer is subjected to LOCO by thermal oxidation.
Selective oxidation of about 500 nanometers by S method
Therefore, the element isolation film 3 is formed. Furthermore, the film thickness is about 3
A silicon oxide film of 0 nanometer is formed, and on this oxide film
To the collector wall using the resist pattern as a mask
N-type semiconductor region 4 having a dose amount of 10^Fifteen-10¹⁶cm^{ー 2}
Is formed by a phosphorus ion implantation method. More collector
Remove the oxide film on the active area other than the
For example, the polysilicon 23 serving as a source is
Deposits. Further, the silicon oxide film 24 is
Deposit 50 nanometers.

Next, in FIG. 4B, in the active region other than the collector region in the resist pattern 25, polysilicon for the base electrode is formed in such a shape as to enter the inside of the isolation oxide film and form a contact on the isolation oxide film. Etch.

Next, in FIG. 4C, after removing the resist 25, a silicon thin film 17 of, for example, 30 nanometers is deposited. After the resist 16 is formed, the N-type semiconductor region 11 for forming the emitter, is formed by a dose of 10 ¹⁵ to 10 ¹⁶ cm ^over the ^second arsenic ion implantation at an energy such overtake the silicon thin film 17. Further formed by a dose of 10 ¹³ 10 ¹⁴ Ion implantation of boron cm ^-2 to P-type semiconductor region 8 serving as the base in energy, such as overtake the silicon thin film 17.

Next, in FIG. 4D, after removing the resist 16, a polysilicon 18 is deposited to a thickness of, for example, 300 nanometers. After the resist 16 is formed, the arsenic dose of 10 ¹⁵ to 10 ¹⁶ cm ^-2 is introduced by ion implantation into the poly silicon for the emitter electrode lead-out.

Next, in FIG. 4E, after the resist 16 is removed, a resist pattern 10 for defining the intrinsic operation region of the bipolar transistor is deposited, the polysilicon 9 is etched, and the silicon of the active region is further etched. Most of the N-type semiconductor region is removed, leaving an N-type residual semiconductor region serving as an emitter below the polysilicon electrode.

Next, in FIG. 4F, after removing the resist 10, a silicon oxide film is deposited to a thickness of, for example, 150 nanometers, and a side wall 19 is formed by anisotropic etching. Further, after the formation of the resist 16, a P-type semiconductor region 13 serving as an external base region is formed by boron ion implantation at a dose of 10 ¹⁵ to 10 ¹⁶ cm ⁻² . This makes it difficult for the breakdown voltage between the emitter region and the collector region to decrease, thereby increasing the yield of the transistor.

Next, in FIG. 4g, after removing the resist 16, titanium 40 is deposited, for example, to a thickness of 40 nanometers. Next, RT
An alloy reaction between titanium and silicon is caused by an A (Rapid Thermal Anealing) method to silicide the emitter electrode polysilicon / external base region in a self-aligned manner. Further, titanium which has not been silicided on the silicon oxide film is removed by wet etching.

Next, in FIG. 4H, an insulating film 1 such as BPSG is formed.
After 2 is deposited on the entire surface, the surface is flattened by, for example, heat treatment at 850 ° C. for 30 minutes. Then, each metal wiring 1
By forming the layers 4 and 15, a semiconductor device having a structure as shown in FIG. 4h can be obtained. This silicide formation process is CMOS
Can be shared with the gate / source / drain silicidation process, so that application to the BiCMOS process is easy.

In this embodiment, the same effects as in the first embodiment can be obtained. Further, in this embodiment, it is possible to reduce the size of the base region in spite of the walled emitter structure by forming polysilicon for the base electrode at the boundary between the separation region and the emitter region and drawing it out onto the separation region ( See FIG. 6).

Although the silicon thin film 17 is used in the second to fourth embodiments, an amorphous Si film or PolyS
i.

In the fourth embodiment, a polysilicon thin film serving as a base electrode is formed to a thickness of, for example, 300 nm. However, if a conductive film such as a metal silicon film (tungsten silicide, molybdenum silicide) is used instead of the polysilicon thin film. This is preferable because the resistance of the electrode can be reduced.

In the first to fourth embodiments, when the active region excluding the intrinsic base region is etched by the resist of the emitter polysilicon patterning, the N-type semiconductor region is not necessarily etched, but the external base region is not necessarily etched. Can be made P-type by optimizing the ion implantation amount of P-type impurities for forming GaN.

Further, the second to fourth embodiments have the following features. (1) By ion-implanting impurities of the first conductivity type and the second conductivity type through a semiconductor thin film such as polysilicon, a relatively low diffusion temperature and a short time can be obtained while eliminating the influence of a natural oxide film. Can also form a shallow emitter and base, and narrow the base width.
A bipolar transistor with high speed can be formed.

(2) By implanting impurities through a semiconductor thin film such as polysilicon, a natural oxide film formed between the semiconductor region and the single crystal semiconductor substrate can be destroyed to some extent. , Thereby reducing the series resistance of the emitter.

(3) The first and second conductivity type impurities are ion-implanted through the same semiconductor thin film such as polysilicon to form a semiconductor region serving as an emitter and a base. The variation in base width caused by the variation in film thickness can be prevented.

[0061]

As described above, according to the present invention of the present invention, the distance between the element isolation insulating film and the base region and the emitter region is separated by a certain distance, and boron is not absorbed into the thermal oxide film. The base layer does not become thinner at the boundary with the thermal oxide film. Therefore, the breakdown voltage between the emitter region and the collector region hardly decreases,
The yield of transistors increases.

Further, by forming the structure in which the emitter electrode is led out to the isolation region and the external base region is etched, the emitter width can be reduced, and the junction capacitance between the emitter and the base can be reduced.

The base region is reduced by forming polysilicon for the base electrode at the boundary between the separation region and the emitter region and drawing it out onto the separation region. It is possible to prevent a decrease in withstand voltage during the operation.

Also, by leaving polycrystalline silicon of the gate electrode formed in the MOS transistor manufacturing process as a dummy pattern at the boundary between the isolation region and the emitter region, the breakdown voltage between the emitter and the collector can be reduced despite the wall-emitter structure. The drop can be prevented.

According to the present invention, a semiconductor device in which a vertical bipolar transistor having high density, high speed, and high withstand voltage is integrated can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a manufacturing process according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process according to a fourth embodiment of the present invention.

FIG. 5 is a plan view and a sectional view of a structure of a conventional device.

FIG. 6 is a plan view and a structural sectional view according to a fourth embodiment of the present invention.

[Explanation of symbols]

 8 Base 9 Emitter polysilicon 11 Emitter 13 External base 19 Side wall

Continuation of the front page (56) References JP-A-55-3686 (JP, A) JP-A-60-70763 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29 / 73

Claims (4)

(57) [Claims] 1. A forming a collector region isolation insulating film made of an element isolation region on the steps of forming a first semiconductor film on said collector region, to enter the inside of the element isolation insulating film The first shape
Patterning a semiconductor film of the above, a step of implanting ions using the first semiconductor film as a mask, and forming a base region and an emitter region so as to overlap with each other ; and forming an emitter extraction electrode on the semiconductor substrate on which the base region is formed. Depositing a second semiconductor film, and selectively removing at least a part of the emitter region except for the second semiconductor film pattern, thereby forming an external semiconductor layer.
Most of the semiconductor region which is to be a source region is removed, and the emitter region and the emitter region are formed immediately below the second semiconductor film pattern.
Leaving a semiconductor region, and leaving a sidewall on the side surface of the emitter region; and forming an external base region by ion implantation using the sidewall and the second semiconductor film pattern as a mask. Connecting the external base region to the base region. 2. The method according to claim 1, wherein said emitter extraction electrode is extended to an element isolation region. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first semiconductor film that has entered the base region is used as a base extraction electrode and is extracted onto the element isolation region. 4. The method according to claim 1, wherein a semiconductor film serving as a gate electrode of a MOS transistor is formed simultaneously with the step of forming a first semiconductor film on the collector region.
4. The method of manufacturing a semiconductor device according to any one of items 2 and 3.