JPS63119265A - Manufacture of bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To attain shallow active base which is suitable for high speed operation by forming oxidation proof film material on the base forming area and collector contact region forming area, implanting a second conductivity type impurity atom into the base forming area with the selective formed insulating film and mask material pattern used as the mask and simultaneously opening the base, emitter, collector contact. CONSTITUTION:An N type buried layer region 110, N type epitaxial layer 120, P type semiconductor regions 130A, 130B, silicon oxide film 140 and silicon nitride film patterns 150A, 150B are formed on the P type semiconductor substrate 100. Boron ions are selectively implanted to form the N type semiconductor region 250A for collector contact and N type semiconductor region 250B for emitter. Thereafter, an opening is formed reaching the polysilicons 230A, 230B, 230C in the silicon oxide film 260 to form aluminum electrode 270A for collector, aluminum electrode 270B for base and aluminum electrode 270C for emitter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a highly integrated manufacturing method for bipolar semiconductor devices, and particularly to a method for forming contact holes in bipolar semiconductor devices having shallow junctions suitable for high-speed operation. It is related to the manufacturing method.

Conventional technology With the miniaturization of bipolar devices, anisotropic dry etching (RIE: Reac
tive ion etching) is widely used.

However, when this dry etching is applied to the contact formation of a bipolar element, especially to the opening in the area where the emitter is to be formed, fine holes can be formed, but on the opening surface,
As soon as etching damage or ion contamination mixed into the 3.-2 etching occurs, the device characteristics deteriorate. In order to simplify the process, it is preferable to open contact holes, diffusion openings, etc. all at once as much as possible. That is, in order to reduce variations in base resistance between the emitter and the base, it is necessary to open the base contact and the emitter contact (diffusion window) at the same time. For example, as disclosed in Japanese Patent Application No. 52-74635, a conventional method involves forming an active base region of a vertical NPN transistor, and then forming an emitter contact hole in an insulating film over the base region. After forming the base contact hole, by forming the emitter region from the emitter contact hole, the base contact and emitter region are formed in a self-aligned manner, thereby reducing fluctuations in base resistance and characteristics. It is stabilizing. According to this method, the base contact hole and the emitter region can be formed in a self-aligned manner, but the active base region must be formed in advance before forming the emitter contact hole and the base contact hole. However, it has been difficult to form the active base shallow enough to be suitable for high speed operation. In order to form a shallow active base suitable for high speed, it is preferable to first form a base region around the emitter, that is, an external base, and then form the active base. On the other hand, a method for forming the active base region after forming the emitter contact hole (diffusion window) and the external base region is described, for example, in the 1984 International Electron Device Meeting Digest of Technical Papers (
1984INTER-NATI○NAL ELECT
RON DEVICE MEETING DIGEST
OF TECHNICAL PAPEFtS)PP.

753-756. The feature of this technology is that an oxidation-resistant mask material pattern such as a silicon nitride film is formed on the area where the emitter is to be formed, and this is used as a diffusion mask to release boron from boron silicide glass (BSG). After forming an external base region around the area where the emitter is to be formed by thermal diffusion, use this oxidation-resistant mask material pattern as a mask.
The purpose is to perform selective oxidation to form emitter contact holes. Furthermore, an active base is formed by implanting ions such as boron, and an emitter is formed by implanting ions such as arsenic, but since the lateral diffusion from the external base to the active base a1j due to BSG is large, pattern conversion is difficult. Because of the large size and the fact that the emitter region must be formed deeper than the damaged layer due to boron ion implantation in the active base, it is necessary to form the emitter deep, and a shallow base structure suitable for high speed is not possible. Not yet. Furthermore, in this technique, the base contact hole is formed with respect to the emitter by a mask alignment method, so the base contact hole and the emitter contact hole are not formed in a self-aligned manner. Emitter, base.

From the viewpoint of simplifying the process and improving the yield, it is most preferable to open the contact hole of the collector or the diffusion window at the same time.

Problems to be Solved by the Invention What happens when the base contact, emitter contact, and collector e-contact of a miniaturized bipolar device are simultaneously formed, and abnormal diffusion occurs in the active base region? ! It has been difficult to achieve a manufacturing method that prevents the occurrence of various damages and contaminations that cause gas leaks. The present invention
In addition to solving these problems, the present invention also provides a method for manufacturing a semiconductor device that facilitates the introduction of a method for forming an external base that achieves a shallow active base suitable for higher speeds, thereby realizing higher performance of bipolar elements. be able to.

Means for Solving the Problems In order to solve these problems, the present invention selectively forms an insulating film around the portion where the base is to be formed and the portion where the collector contact region is to be formed on the semiconductor layer of the first conductivity type. a step of forming an oxidation-resistant film material at least on the base formation area and the collector contact region formation area, the base contact formation area and the emitter formation area, and , and the entire area where the collector contact area is to be formed are selectively covered.
- forming an oxidation-resistant material pattern on the oxidation-resistant film material; and using the selectively formed insulating film and the mask material pattern as a mask, impurities of a second conductivity type are formed on the portion where the base is to be formed. a step of implanting atoms to form a semiconductor region that will become a part of the base; a step of forming the oxidation-resistant film material pattern using the mask material pattern as a mask; A step of selectively oxidizing as a mask to form an insulating film on the surface of the semiconductor region that will become a part of the base, and removing the oxidation-resistant mask material pattern used in the selective oxidation to form a base contact,
A method of manufacturing a bipolar semiconductor device is provided, which includes a step of simultaneously opening an emitter contact and a collector contact.

Effects When the means according to the invention were applied to a bipolar NPN) transistor, the elements of each means produced the following effects.

After selectively patterning an oxidation-resistant mask material with a mask material pattern that covers the base contact formation area, the emitter contact formation area, and the entire collector contact formation area, this is masked. By selectively oxidizing the base contact hole and the emitter contact hole, the base contact hole and the emitter contact hole can be arranged in a self-aligned manner, and the collector contact hole can also be formed at the same time. Using the mask material pattern, an external base region could be formed by a method such as ion implantation. in this case,
Since the entire surface of the collector/contact formation area was covered with the mask material pattern, it was possible to prevent impurities of different conductivity types from entering the collector/contact area.

Furthermore, when selectively patterning the oxidation-resistant mask material, methods such as dry etching were used, but the semiconductor surface within the emitter contact was not directly exposed to dry etching.
Since it was not etched, the surface of the emitter could be kept in good condition. This made it possible to prevent variations and deterioration of transistor characteristics by 9'-7.

Embodiments FIGS. 1 to 5 show bipolar vertical NPN according to the present invention.
) FIG. 3 is a process cross-sectional view showing a series of methods for manufacturing a transistor. First, on the P-type semiconductor substrate 100 shown in FIG.
After forming an N-type buried layer region 110 and an N-type epitaxial layer 120 of about 1 Ωm, and forming P-type semiconductor regions 130A and 130B for element isolation from the surface of this epitaxial layer, on the surface of the epitaxial layer 1200, Approximately 500
A silicon oxide film 14o of about 1,000 people and a silicon nitride film of about 1,000 people were successively formed. Through the photo-ethoting process,
This silicon nitride film was selectively removed to form silicon nitride film patterns 1soA and 150B.

Next, using the silicon nitride film patterns 150A and 150B as oxidation-resistant masks, selective oxidation of about 6,000% is performed to form a thick silicon oxide film 160, and then the silicon nitride films 15oA and 15oB and the silicon oxide film 140 are After forming a new oxide film 170 with a thickness of about 500, -7 and a silicon nitride film with a thickness of about 500, resist butter 719OA, 190B, and 190C were formed on the collector by a photolithography process. - Resist patterns 190A and 190B are formed on the areas where contacts, base-contacts, and emitter contacts are to be formed.

Using 190C as a mask, the silicon nitride film is etched to form silicon nitride film patterns 1soA and 1soB.

180C was formed as shown in FIG.

Next, resist patterns 190A and 190B.

Using 19oC as a mask, poron ion implantation is performed to form a P-type semiconductor region 200A that will become an external base.

After forming resist patterns 719OA, 190B and 190C and removing resist patterns 719OA, 190B and 190C, -
71J j 7 Nitride film pattern 1808, 180B, 1
Silicon oxide film 21 OA, 21 is selectively oxidized using 8oC as a mask and becomes a thin insulating film of about 2,000 people.
oB.

210C was formed. Phosphorus is selectively ion-implanted using a photomask process to form N for the collector contact.
A semiconductor region 220 of the type is formed, and silicon nitride films 180A and 180B are formed on each contact.

At 18oC, the silicon oxide film 170, etc. are removed, each contact hole is exposed as shown in Figure 3, and a polysilicon film is then deposited over the entire surface by approximately 3,000 people, followed by photolithography.
In the etching process, etching site, polysilicon, etc.
Patterns 230A, 230B.

230C was formed. Polysilicon pattern 230B
, 230C, and heat treatment to form a P-type semiconductor region 24OA for a base contact and a P-type semiconductor region 240 for an active base, respectively.
B was formed as shown in FIG. However, boron ion implantation for the base contact and the active base do not necessarily have to be at the same implantation dose;
It is preferable to increase the injection amount for contacts.

Next, as shown in FIG.
After selectively implanting arsenic ions into OA and 230C and performing heat treatment to form an N-type semiconductor region 250A for collector contact and an N-type semiconductor region 260B for emitter, normal integration is performed. According to the circuit manufacturing method, a conductive material pattern of polysilicon: 77230A, 230B, 2 is applied to the silicon oxide film 260 which becomes an insulating film.
An opening reaching 30C is formed, and an A for the collector is formed.
T electrode 27OA, for base (DAt electrode 270B,
An At electrode 270C for emitter was formed.

As described above, by the series of manufacturing methods of the present invention, the base contact and emitter region are formed in a self-aligned manner, and moreover, the active base and emitter regions can be formed by diffusion from the same polysilicon. , the emitter depth is 50 degrees, the base depth is 1,500 people, and therefore the pace width is about 1,000 people, making it an excellent high-speed NP.
It was possible to form an N transistor.

Although an example of the present invention is shown in FIGS. 1 to 5, other suitable methods may be adopted at various points in the process depending on the case. For example, in Figure 2, approximately 600 silicon oxide films and approximately 500 silicon nitride films are used as oxidation-resistant mask materials, but the composition of the oxidation-resistant films is ,
One layer or three or more layers may be used.Also, the oxidation-resistant mask material was patterned using photoresist, and then boron ions serving as an external base were ion-implanted. As a method, it is also possible to implant ions before patterning the oxidation-resistant mask material. Although photoresist is simply used to pattern the oxidation-resistant mask material, other film materials may be used instead of photoresist. or,
The gist of the present invention is that the film material such as photoresist for patterning this oxidation-resistant mask material and the film material such as photoresist for implanting the external base are strictly defined. They do not need to be the same, and may be different film materials that maintain a self-aligned positional relationship with each other. For example, after turning a thick layer of oxidation-resistant mask material,
After forming the so-called side wall film on the surface K, the emitter 14 is implanted with externally based boron.
1, -7 It is also possible to improve and control the electrical breakdown voltage of the junction between the bases. In order to form semiconductor regions such as an internal base and an emitter, in this example, a diffusion method from polysilicon was used, but it is naturally possible to use a normal diffusion source or direct ion implantation. . Furthermore, when switching speed is generally considered important, it may be possible to form another low-resistance external base in addition to the external base formed in this embodiment by matching a mask. In the method of the present invention, since the distance between the emitter and base contact is maintained in a self-aligned manner, the variation in base resistance is naturally smaller compared to a method in which the distance between the emitter and base contact is determined by matching the mask. Also, since the internal base and emitter can be formed by diffusion from polysilicon, very high-speed switching can be achieved.

Regarding the transistor structure, by changing the arrangement of the insulating film formed around the area where the base is to be formed and the selectively formed oxidation-resistant mask material pattern, a so-called walled 15 base structure can be obtained. Alternatively, the walled emitter structure N
PN) transistor structure could be easily realized.

Effects of the Invention According to the manufacturing method of the present invention, a base contact and an emitter region can be formed in a fine shape in a self-aligned manner, and
At the same time, the collector contact region could also be easily formed. Furthermore, it is possible to easily form a shallow base with excellent high-speed performance, and to provide a bipolar semiconductor device with good performance.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views showing an embodiment of the method for manufacturing a bipolar NPN transistor according to the present invention. 100...P-type semiconductor substrate, 110...
・N-type buried layer region, 120...N-type epitaxial layer, 130A, 130B, 20OA, 200B
, 200C, 24OA. 240B-, -P type semiconductor region, 220.25OA. 250B-, -N type semiconductor region, 23OA, 230B
. 230C...Polysilicon, 140.160
, 170. 210A, 210B, 21oC, 260--
--- Silicon oxide film, 150A, 150B, 180
A, 180B, 180C...-71J con nitride film,
190A, 190B, 190C...Resist, 27OA, 270B, 270C---A
I: Electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 5 Figure 2ED--δ, 02 T27oA-AI.

Claims (1)

[Claims] a step of selectively forming an insulating film around a portion where a base is to be formed and a portion where a collector contact region is to be formed on the semiconductor layer of the first conductivity type; a step of forming an oxidation-resistant film material thereon; and a mask material pattern that selectively covers the base contact formation area, the emitter formation area, and the entire collector contact area formation area. forming a second layer on the oxidation-resistant film material, and using the selectively formed insulating film and the mask material pattern as a mask, a second
a step of implanting conductivity type impurity atoms to form a semiconductor region that will become a part of the base; a step of forming the oxidation-resistant film material pattern using the mask material pattern as a mask; Using the mask material pattern as a mask,
A step of performing selective oxidation to form an insulating film on the surface of the semiconductor region that will become a part of the base, and removing the oxidation-resistant mask material pattern used for the selective oxidation to form a base contact and an emitter contact. , a method for manufacturing a bipolar semiconductor device comprising the steps of simultaneously opening a collector contact.