JPH05218319A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a high-speed transistor by forming an intrinsic base region of an npn transistor after a high temperature heat treatment process so that shallow base and emitter regions can be formed, whereby a side wall of the emitter region can be formed into a double structure. CONSTITUTION:Only a Si3N4 film 17 to be used as intrinsic base and emitter regions 20 of an npn transistor is removed after a thermal oxidation treatment, and an intrinsic base 8 having an electical continuity to a graft base region 7 is formed by introducing p-type impurities into the regions from which the film was removed. An SiO2 film 13 located above regions to be used as a collector 16 of the npn transistor and a base 26 of a pnp transistor, a p<+>-type polysilicon 6, and a Si3N4 film 27 are sequentially removed. An emitter region 9 and a collector region 6 of the npn transistor and a base extraction region 61 of the pnp transistor are formed by introducing impurities into the regions from which the films were removed. An isolation film between the base region and the emitter region is formed into a double structure made of a SiO2 film 13 and a Si3N4 film 27, and hence it is possible to reduce a leakage current and an emitter-base junction capacitance. Therefore, shallow base and emitter regions can be formed, and a high-speed transistor can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is miniaturized and has a high speed, and more particularly to a method of manufacturing a bipolar transistor centering on a high frequency transistor.

[0002]

2. Description of the Related Art Conventionally, a high-frequency transistor has a high speed by reducing the width and depth of the base region, reducing the collector-base junction capacitance, and forming a shallow base-emitter diffusion layer, that is, by forming a shallow region. Has been promoted. However, if both NPN and PNP transistors are manufactured in the same substrate, for example, NPN
Even if the transistor (NPNTr) is made vertical and high speed, the PNP transistor (PNPTr) becomes horizontal,
The high speed of PNPTr will be impaired. 8 to 1
Reference numeral 2 is an example of a known and basic manufacturing process of the vertical NPTr and the horizontal PNPTr. That is, FIG. 8 shows a P-type silicon substrate 1 formed by a well-known technique, an n + buried layer 4 and then an N-type epitaxial layer 2, and a P-type diffusion layer 5 for element isolation and a compensation collector of NPNTr. An n + type diffusion layer 6 which is a region and an n + type diffusion layer 61 which is a compensation base region of the PNPTr are formed by thermal diffusion or the like. Further, a P-type diffusion layer is formed in the base region 7 of the NPNTr, the emitter region 71 and the collector region 72 of the PNPTr by the same method. At this time, since the base width 62 of the PNPTr is horizontal, it depends on the capability of the photoetching technique.
Submicron formation is not possible. After that, non-doped polysilicon 16 is deposited on the entire surface and a so-called LOC is formed.
The OS method oxidizes non-doped polysilicon unnecessary portions, to the silicon oxide film (S _i O ₂ film) 13. Next, referring to FIG. 9, a silicon nitride film (S _i3 N ₄ film) 17, S _i O ₂
Film are sequentially deposited, for S _i O ₂ film, the emitter of NPNTr, to leave only S _i O ₂ film 18 of the base portion reserved for formation of the collector formation area and PNPTr, choose remove other portions. The P-type impurity such as boron The S _i O ₂ film 18 on the non-doped polysilicon 16 in the impurity diffusion mask is introduced by ion implantation, the p + -type polysilicon 12. Consequently, non-doped polysilicon 16 immediately below S _i O ₂ film 18 remains non-doped. Next, in FIG. 10, the S _i3 N ₄ film 17 is removed by wet etching. At this time, only the S _{i 3} N ₄ film immediately below the S _i O ₂ film 18 remains, but etching is performed to the extent of overetching, so-called side etching, whereby the S _i O ₂ film 1 is formed.
Make it thinner than 8. Therefore, the non-doped polysilicon 16 is etched by using an etching solution in which the non-doped polysilicon 16 has a faster etching rate than the p + polysilicon 12. Then, a part of the non-doped polysilicon 16 is etched from the edge portion of the emitter pattern, and the p + polysilicon 12 and the non-doped polysilicon 16 are separated. Further, in FIG. 11, S _i O ₂ film 1
After 8 was removed, subjected to thermal oxidation, non-doped polysilicon 16, P + polysilicon 12, and the exposed portions of the base forming region of NPNTr the silicon substrate 2 S _i O ₂ film 13 and (insulating film). Then, the S _i3 N ₄ film 17 is removed. Finally, in FIG. 12, undoped polysilicon 1
An N-type impurity 15 such as arsenic (As) is formed into n + polysilicon 15 by a method such as thermal diffusion, and this is used as an impurity source to form an emitter region 9. Then, the base electrode 42, the emitter electrode 41, and the collector electrode 4 of the NPNTr.
3, PNPTr base electrode 44, emitter electrode 45,
The collector electrode 46 is formed.

[0003]

As described above, in the manufacturing method according to the conventional method, in the case of NPNTr, the base diffusion must be performed at the beginning of the process, and the subsequent heat treatment promotes the diffusion to deepen the base diffusion. Because it is formed
It was not possible to obtain sufficient speed. The base, for emitter is a thin S _i O ₂ film, the base-emitter,
There is a drawback that a leak current may occur. Further, since the PNPTr manufactured at the same time is a horizontal type, there is a drawback that the base width is wide and the high speed cannot be obtained, like the NPNTr. The present invention solves the above-mentioned drawbacks, and in the case of NPNTr, an ultrafine emitter region having a submicron width and depth is formed in a fine base region, and Tr with a small parasitic capacitance and PNPTr are NP
It is an object to provide a high-speed Tr manufacturing method with a vertical structure similar to that of NTr.

[0004]

According to the present invention, in order to achieve the above object, the formation of the intrinsic base region of the NPNTr is performed in the latter stage of the manufacturing process (after the high temperature heat treatment process).
To form a shallow base region and the emitter region, also by the side walls of the emitter region and the double structure of S _i O ₂ film and S _i3 N ₄ film, it is possible to reduce the base-emitter junction capacitance, yet, the base-emitter The structure is such that the leak current between them can be reduced. At the same time, a vertical PNPTr having a narrow base width is also manufactured.

[0005]

As a result, it is possible to reduce the parasitic capacitance (base-emitter junction capacitance) and the leak current between the base and emitter simultaneously with the miniaturization of Tr, and it is possible to reduce the high speed NPNTr and the high speed vertical type. It is possible to manufacture the PNPTr on the same substrate.

[0006]

Embodiments will be described in detail below with reference to embodiments of the present invention. 1 to 7 are cross-sectional views in each process for explaining an embodiment of the present invention. In these figures, the left side is the PNPTr and the right side is the description about the NPNTr. FIG. 1 shows an N-type buried layer 4 and P-type buried layers 5 and 51, which are formed on a P-type silicon substrate 1 by a known technique.
Are formed respectively. At this time, the P-type buried layer 51 is formed with a higher concentration than the N-type buried layer 4. After that, an N type epitaxial layer 2 is formed, and an oxidation resistant and silicon etching resistant film such as a Si ₃ N ₄ film is deposited on the entire surface by a CVD method, and then NP is applied by a photo etching technique.
The S _i3 N ₄ film on the base / collector of the NTr, the base / emitter of the PNPTr, the region where the collector electrode is to be installed and the element isolation region is removed. And the remaining S _i3 N ₄
The N type epitaxial layer 2 is etched using the film 17 as an etching mask. At this time, the element isolation region and the PN
The collector region 10 of the PTr is deeply etched. Next, in FIG. 2, thermal oxidation is performed in the presence of the S _i3 N ₄ film 17 to form a S _i O ₂ film 3 as an insulating film. On this occasion,
When the thermal oxidation is sufficiently performed, the N-type epitaxial layer 2 under the S _i3 N ₄ film 17 also becomes the S _i O ₂ film 3. Next, in FIG. 3, in this state, if reactive ion etching accompanied by deposition of deposits with poor step coverage or dry etching with good directionality is performed, the S _i3 N ₄ film under the film 17 described in FIG. only S _i O ₂ film 3 is left. Since this etching method is anisotropic, the side walls of the etching groove are almost vertical. Further, in this state, for example, S _i3 by the CUD method which is an insulating film
The N ₄ film 27 is deposited on the entire surface. Next, in FIG. 4, NPNT
When the anti-etching material such as photoresist is selectively formed in the region where the collector electrode 16 of r and the base electrode 26 of the PNPTr are to be formed, and the anisotropic etching described in FIG. Only the S _i3 N ₄ film 27 on the sidewall of the _i O ₂ film 3 remains, and the S _i3 N ₄ film 27 on the flat portion is removed. At this time, the collector electrode 1 of the NPNTr
6. In the PNPTr base electrode 26 formation planned region, the Si ₃ N ₄ film 27 in the flat portion remains. The side wall S _i3 N ₄ film 27 and the side wall S _i O ₂ film 3 described with reference to FIG. 3 serve as a separation film between the emitter region of the NPNTr and the base extraction electrode. further,
P + type polysilicon is deposited on the entire surface by the CVD method.
At this time, the p + -type polysilicon is deposited with a thickness that is more than twice the depth of the etching groove. In this way, after the deposition, there is almost no step, and the surface becomes almost flat. Then, isotropic etching is performed in this state to leave the p + -type polysilicon 12 only in the etching groove portion. This method is a so-called etch back method. Furthermore, the thermal oxidation is performed in this state, the exposed portion of the p + -type polysilicon 12 is oxidized, S _i O ₂ film 13 is formed. During this thermal oxidation process, the P-type impurities are diffused from the p + -type polysilicon 12 into the N-type epitaxial layer 2, and in the NPNTr, the graft base region 7 becomes the PNP.
In Tr, the collector layer 7 connected to the P-type buried layer 51
1 and the emitter layer 72 are formed, and the element isolation region is completed by connecting to the P-type buried layer 5 in the element isolation region. At this time, the collector section 16 of the NPNTr and the PNPTr
In the base portion 26, the _{Si 3} N ₄ film 27 serves as a diffusion stopper, and the impurities are not diffused. Next, in FIG. 5, NPNT
Intrinsic base of r, S _i3 N ₄ of the emitter formation planned region 20
Only the film 17 is removed, P-type impurities are introduced from this opening, and the intrinsic base region 8 that is electrically connected to the graft base region 7
Are formed by an ion implantation method or the like. Then sequentially removing S _i O ₂ film 13, p + form polysilicon 6, S _i3 N ₄ film 27 on the base 26 forming area of the collector 16, PNPTr of NPNTr. Further, in FIG. 6, when N-type impurities are introduced in this state by, for example, an ion implantation method, the emitter region 9 of the NPNTr, the collector region 6, and the base extraction region 61 of the PNPTr can be formed. Furthermore, PNPTr
Opening the emitter, the S _i O ₂ film 13 of the collector unit. Further, an opening part of S _i O ₂ film 13 on the P-type polysilicon 6 on the graft base NPNTr. With the above, N
The formation of the base, emitter and collector regions of both PNPNP transistors was completed. Finally, in FIG. 7, an electrode material such as aluminum is deposited, and the emitter electrode 41, the base electrode 42, and the collector electrode 43 of the NPNTr are connected to the PNP.
An emitter electrode 45, a collector electrode 46, and a base electrode 44 of Tr are formed. The emitter electrode 41 of the NPNTr, the collector electrode 43, and the base electrode 4 of the PNPTr
4 may be formed of n + type polysilicon, and this region may be formed by using this as a diffusion source.

[0007]

As described above, according to the present invention, when producing NPNTr, separation membrane of the base region and the emitter region, S _i O ₂
For film and a double structure of S _i3 N ₄ film, low leakage current and the emitter-base junction capacitance (CEB) can be reduced, element isolation region, because of the thin epitaxial layer by etching The collector-substrate junction capacitance (Csub) can be reduced. Further, since a high temperature heat treatment process such as thermal oxidation is not used after the formation of the intrinsic base, shallow base and emitter regions can be formed and so-called shallowing can be achieved. As a result, a high speed transistor can be manufactured. Furthermore, at the same time, the vertical PNPTr with a narrow base width
Can be manufactured, and the speed is increased.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention.

FIG. 2 is a sectional view of an embodiment of the present invention.

FIG. 3 is a sectional view of an embodiment of the present invention.

FIG. 4 is a sectional view of an embodiment of the present invention.

FIG. 5 is a sectional view of an embodiment of the present invention.

FIG. 6 is a sectional view of an embodiment of the present invention.

FIG. 7 is a sectional view of an embodiment of the present invention.

FIG. 8 is a sectional view of a conventional example.

FIG. 9 is a sectional view of a conventional example.

FIG. 10 is a sectional view of a conventional example.

FIG. 11 is a sectional view of a conventional example.

FIG. 12 is a sectional view of a conventional example.

[Explanation of symbols]

1 P-type S _i substrate 2 N type epitaxial layer 3, 13 S _i O ₂ film 4 N-type buried layer 5 and 51 P-type buried layer 6 compensation collector region 7 graft base region 8 intrinsic base region 9 emitter region 10 PNPTr Collector formation planned region 12 p + type polysilicon 15 n + polysilicon 16 undoped polysilicon 17, 27 Si ₃ N ₄ film 20 intrinsic base, emitter formation region 72 PNPTr emitter region 41, 42, 43, 44, 45, 46 Aluminum electrode 61 PNPTr base region 71 PNPTr collector region

Claims (1)

[Claims] 1. A first major surface of a semiconductor substrate of a first conductivity type,
A second conductivity type buried collector layer and a first conductivity type buried element isolation layer are formed so as to surround the second conductivity type buried collector layer, and at the same time, a second conductivity type element isolation layer is formed on the second main surface of the semiconductor substrate. Forming, a buried collector layer of the first conductivity type is formed inside the layer, a buried element isolation layer of the first conductivity type is formed so as to surround it, and an epitaxial layer of the second conductivity type is formed. Aside from the base extraction electrode on the first main surface on the epitaxial layer, the collector compensation region, the base emitter on the second main surface, the collector region, and the element isolation region surrounding them, silicon etching resistance and oxidation resistance. Film is formed, and in this state, the above-mentioned epitaxial layer is anisotropically etched to form an etching groove,
At this time, the collector region on the second epitaxial main surface and the etching trench in the element isolation region are formed deeper than the other etching trenches, and a silicon oxide film and a silicon nitride film are formed on the side wall of the etching trench. A first portion is formed in the etching groove other than the collector compensation region of the first epitaxial main surface and the base region of the second epitaxial main surface.
A step of forming an electrode that makes ohmic contact with the conductive type epitaxial layer, oxidizing the exposed portion of the electrode to form an element isolation region, a graft base in the first epitaxial main surface, an emitter in the second epitaxial main surface, A step of forming a base region, removing the silicon-etching-resistant and oxidation-resistant film adjacent to the graft base region, and introducing an impurity of the first conductivity type that is conductive with the graft base region into the opening, Forming an intrinsic base region, a collector compensation region in the first epitaxial main surface, and a second
And a step of forming an opening on the base and emitter collector regions in the epitaxial main surface, and forming an electrode that makes ohmic contact with the base, emitter and collector regions in the first and second epitaxial main surfaces, respectively. A method for manufacturing a semiconductor device, comprising: