JPS60258920A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60258920A JPS60258920A JP11456384A JP11456384A JPS60258920A JP S60258920 A JPS60258920 A JP S60258920A JP 11456384 A JP11456384 A JP 11456384A JP 11456384 A JP11456384 A JP 11456384A JP S60258920 A JPS60258920 A JP S60258920A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- layer
- oxide film
- polysilicon
- type layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 7
- 150000004767 nitrides Chemical class 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 230000007547 defect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は多結晶シリコンを使用した半導体装置の製造方
法に係り、特に窒化珪素膜上に形成した多結晶シリコン
を酸化し、絶縁膜を形成する方法に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device using polycrystalline silicon, and in particular, a method of oxidizing polycrystalline silicon formed on a silicon nitride film to form an insulating film. Regarding the method.
従来窒化珪素膜等の耐酸化性被膜上に形成した多結晶シ
リコンを酸化し絶縁膜を形成した場合、第１図に示すよ
うに多結晶シリコン４の表面の酸（１）
化膜５は窒化珪素膜３と接触する部分で薄くなることが
知られている。このために第２図（ａ）に示すように多
結晶シリコン４を引出し電極として用い、右側の窒化珪
素膜３と酸化珪素膜２を除去し、同図（ｂ）に示す多結
晶シリコン８を形成し、第１導電形層７と第２導電形層
９を形成してトランジスタを作る場合、前記被膜のエツ
チング工程において、窒化珪素膜に近接した薄い酸化膜
部分が無くなり、多結晶シリコン４と多結晶シリコン８
が接触し、特性が劣化する場合がある。Conventionally, when polycrystalline silicon formed on an oxidation-resistant film such as a silicon nitride film is oxidized to form an insulating film, as shown in FIG. It is known that the portion that contacts the silicon film 3 becomes thinner. For this purpose, as shown in FIG. 2(a), polycrystalline silicon 4 is used as an extraction electrode, the silicon nitride film 3 and silicon oxide film 2 on the right side are removed, and the polycrystalline silicon 8 shown in FIG. 2(b) is removed. When forming a first conductivity type layer 7 and a second conductivity type layer 9 to form a transistor, the thin oxide film portion adjacent to the silicon nitride film is eliminated in the film etching process, and the polycrystalline silicon 4 and polycrystalline silicon 8
may come into contact with each other, resulting in deterioration of characteristics.
本発明は前記両多結晶シリコン層の接触による不良の発
生を防止することを目的に開発したものである。The present invention was developed for the purpose of preventing the occurrence of defects due to contact between the two polycrystalline silicon layers.
耐酸化性被膜上の多結晶シリコンを酸化して形成した絶
縁膜がその界面において薄くなるために発生する不良は
集積規模が小さい場合にはあまり問題にならないが、大
きくなるにしたがって歩留の低下を生じ、特に低電流領
域の電流増幅率が重（２）
要なメモリ素子で重大な問題となる。Defects that occur because the insulating film formed by oxidizing the polycrystalline silicon on the oxidation-resistant film becomes thinner at the interface are not much of a problem when the scale of integration is small, but the yield decreases as the scale of integration increases. This is a serious problem especially in memory devices where the current amplification factor in the low current region is important.
この不良を防ぐ方法として薄くなった部分に絶縁膜を埋
込む方法が特開昭５６−８７３４６号に開示されている
が、より簡単で、確実に不良を防止する方法として、第
２導電形領域上の窒化珪素膜を完全に除去し、酸化を行
なって連続した酸化膜で第１導電形層と接続される電極
用の多結晶シリコンを被うものである。As a method of preventing this defect, a method of embedding an insulating film in the thinned part is disclosed in JP-A-56-87346, but as a simpler and more reliable method of preventing the defect, The upper silicon nitride film is completely removed and oxidized to cover the polycrystalline silicon for the electrode connected to the first conductivity type layer with a continuous oxide film.
以下、本発明の一実施例を第３図により説明する。同図
（ａ）は第２図（ａ）に示した構造を形成後窒化珪素膜
３を熱リン酸により除去した所である。すなわち、ｎ型
シリコン基板１を酸化し。An embodiment of the present invention will be described below with reference to FIG. FIG. 2(a) shows the structure shown in FIG. 2(a) having been formed and the silicon nitride film 3 removed using hot phosphoric acid. That is, the n-type silicon substrate 1 is oxidized.
５０ｎｍの酸化膜２を形成後、１１００ｎの窒化珪素膜
３を被着し、第１導電形層のコンタクト領域の同二層膜
を除去し、３００ｎｍの多結晶シリコン層４を形成し、
ボロンを添加後、第２導電形層上の多結晶シリコンを選
択的に除去して酸化をｊ′ 行ない酸化膜５を形成し、
第２導電形層の酸化防止用に使用した窒化珪素膜を除去
した。なお、第（３）
２導電形層６は多結晶シリコン４の酸化時に同シリコン
中のボロンが拡散して形成される。After forming an oxide film 2 of 50 nm, a silicon nitride film 3 of 1100 nm is deposited, the same two-layer film in the contact region of the first conductivity type layer is removed, and a polycrystalline silicon layer 4 of 300 nm is formed.
After adding boron, the polycrystalline silicon on the second conductivity type layer is selectively removed and oxidized to form an oxide film 5,
The silicon nitride film used to prevent oxidation of the second conductivity type layer was removed. The (3) second conductivity type layer 6 is formed by diffusing boron in the polycrystalline silicon 4 when it is oxidized.
第３図（ｂ）は窒化珪素膜の下の酸化膜２（同図（ａ）
）を除去し、酸化を行ない、酸化膜１０を形成した状態
を示す。次に方向性のあるエツチング方法により第２導
電形層上の酸化膜１０を除去し、第１導電形層７を形成
し、多結晶シリコン１１を被着し、ヒ素を拡散させて第
２導電形層９を形成した（第３図（Ｃ））。FIG. 3(b) shows the oxide film 2 under the silicon nitride film (FIG. 3(a)).
) is removed and oxidized to form an oxide film 10. Next, the oxide film 10 on the second conductivity type layer is removed by a directional etching method, a first conductivity type layer 7 is formed, polycrystalline silicon 11 is deposited, and arsenic is diffused to form the second conductivity type layer 7. A shaped layer 9 was formed (FIG. 3(C)).
なお、本実施例では説明を簡単にするためにトランジス
タの一部のみを述べたが、集積回路に使用する実際のト
ランジスタでは埋込み層やアイソレーションを始め配線
工程が必要なことは云うまでもない。Note that in this example, only a part of the transistor is described to simplify the explanation, but it goes without saying that actual transistors used in integrated circuits require wiring processes such as buried layers and isolation. .
本発明によれば簡単な方法で第１および第２導電形層に
それぞれ接続される多結晶シリコン間の接触を完全に防
止することが可能で、特に高いトランジスタ歩留が要求
される大規模集積回路の製作時にその効果が顕著になる
。According to the present invention, it is possible to completely prevent contact between the polycrystalline silicon connected to the first and second conductivity type layers by a simple method, especially in large-scale integration where high transistor yield is required. The effect becomes noticeable when manufacturing the circuit.
（４、(4,
第１図および第２図は従来法の問題点を説明するための
断面構造図、第３図は本発明の一実施例を示す工程図で
ある。
１・・・シリコン基板、２，５・・・シリコンの酸化膜
。
（５）
第１図
第２図
Ｃｂ）
第３図
（ａ−）
（ｂ）
（Ｃ）1 and 2 are cross-sectional structural views for explaining the problems of the conventional method, and FIG. 3 is a process diagram showing an embodiment of the present invention. 1... Silicon substrate, 2, 5... Silicon oxide film. (5) Figure 1 Figure 2 Cb) Figure 3 (a-) (b) (C)
Claims (1)
領域を形成する領域に形成されている耐酸化性被膜上に
まで延びている構造において、前記多結晶シリコン層の
一部を酸化し、絶縁膜で被った後、前記耐酸化性被膜を
完全に除去し、前記多結晶シリコン層の露出部を酸化す
ることを特徴とする半導体装置の製造方法。In a structure in which polycrystalline silicon connected to a first conductivity type region extends onto an oxidation-resistant film formed in a region forming a second conductivity type region, a part of the polycrystalline silicon layer is oxidized. . A method of manufacturing a semiconductor device, characterized in that after covering with an insulating film, the oxidation-resistant film is completely removed and exposed portions of the polycrystalline silicon layer are oxidized.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11456384A JPS60258920A (en) | 1984-06-06 | 1984-06-06 | Manufacture of semiconductor device |
| US06/741,525 US4640721A (en) | 1984-06-06 | 1985-06-05 | Method of forming bipolar transistors with graft base regions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11456384A JPS60258920A (en) | 1984-06-06 | 1984-06-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60258920A true JPS60258920A (en) | 1985-12-20 |
Family
ID=14640942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11456384A Pending JPS60258920A (en) | 1984-06-06 | 1984-06-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60258920A (en) |
-
1984
- 1984-06-06 JP JP11456384A patent/JPS60258920A/en active Pending
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