JPH0344912A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0344912A
JPH0344912A JP18098189A JP18098189A JPH0344912A JP H0344912 A JPH0344912 A JP H0344912A JP 18098189 A JP18098189 A JP 18098189A JP 18098189 A JP18098189 A JP 18098189A JP H0344912 A JPH0344912 A JP H0344912A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
silicon
layers
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18098189A
Other languages
Japanese (ja)
Inventor
Kazuyuki Kurita
栗田 和行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18098189A priority Critical patent/JPH0344912A/en
Publication of JPH0344912A publication Critical patent/JPH0344912A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form symmetry with respect to material and structure, to prevent warpage due to a heat treatment and to improve an accuracy of miniaturization by adhesively bonding thin semiconductor films having equal thickness on both side surfaces of a semiconductor substrate through insulating layers. CONSTITUTION:Thermal oxide films 4 are formed on whole surfaces including both side surfaces of a silicon substrate 2, and silicon layers 6, 8 are formed on both side surfaces of the substrate 2 through the films 4. In this case, the face orientation of both the substrate 2 and the layers 6, 8 are brought into agreement. The thus formed substrate is kept symmetric with respect to materials and structures on the front and rear surfaces, and mismatches of thermal expansion coefficients of the substrate 2, the layers 6, 8 and the films 4 are cancelled to each other at the front and rear surfaces. Accordingly, even if it is heat treated, it can prevent warpage. Thus, a fine pattern processing can be facilitated to enhance its accuracy.

Description

【発明の詳細な説明】 [vA要] 半導体装置及びそのM 36方法に係り、特にウェーハ
接着型S OI (5ilicon On In5ul
ator)基板及びその製造方法に関し、 プロセス中の熱処理による反りの発生を防止し、rR細
加工の精度を高めることができる半導体基板及びその製
造方法を提供することを目的とし、半導体基板と、前記
半導体基板の両面にそれぞれ形成された第1及び第2の
絶縁層と、前記第1及び第2の絶縁層上にそれぞれ接着
接合された第1及び第2の半導体層とを有するように構
成し、また、第1の半導体基板の両面にそれぞれ第1及
び第2の絶縁層を形成する工程と、前記第1及び第2の
絶縁層上に、それぞれ第2及び第3の半導体基板を接着
接合させる工程と、前記第2及び第3の半導体基板の各
露出面を両面研磨して第1及び第2の半導体層を形成す
る工程とを有するように構成する。
[Detailed Description of the Invention] [vA Required] Relates to semiconductor devices and M36 methods thereof, particularly wafer-bonded SOI (5ilicon On In5ul)
The purpose of the present invention is to provide a semiconductor substrate and a manufacturing method thereof that can prevent the occurrence of warpage due to heat treatment during the process and improve the accuracy of rR fine processing. The semiconductor device is configured to have first and second insulating layers formed on both sides of a semiconductor substrate, respectively, and first and second semiconductor layers adhesively bonded on the first and second insulating layers, respectively. , a step of forming first and second insulating layers on both surfaces of the first semiconductor substrate, respectively, and adhesively bonding second and third semiconductor substrates on the first and second insulating layers, respectively. and a step of polishing both exposed surfaces of the second and third semiconductor substrates to form first and second semiconductor layers.

[産業上の利用分野] 本発明は半導体装置及びその製造方法に係り、特にウェ
ーハ接着型So I (Silicon On In5
ulator)基板及びその製造方法に関する。
[Industrial Field of Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a wafer-bonded SoI (Silicon On In5) semiconductor device and a method for manufacturing the same.
ulator) substrate and its manufacturing method.

[従来の技術] 近年、Sol基板は、メモリデバイスの高集積化やデジ
タ、ルデバイスの高速化において、ソフトエラー耐性に
優れ、スピード高速化が図れる半導体基板として期待さ
れている。しかし同時に、SOf基板を安定に供給する
ことやデバイスプロセスにマツチングさせること等の課
題を解決することが要求されている。特に、プロセス中
に発生するSol基板の反りの問題は、早急な解決が迫
られている。
[Prior Art] In recent years, Sol substrates have been expected to serve as semiconductor substrates that have excellent soft error resistance and can achieve high speeds in the context of higher integration of memory devices and higher speeds of digital devices. However, at the same time, it is required to solve problems such as stably supplying SOf substrates and matching them to device processes. In particular, there is an urgent need to solve the problem of warpage of the Sol substrate that occurs during the process.

すなわち、従来のシリコンウェーハ接着型SOI基板は
、シリコン基板の片面上にシリコン酸化膜を介してシリ
コン薄膜を接着接合している。
That is, in a conventional silicon wafer bonded SOI substrate, a silicon thin film is adhesively bonded to one side of a silicon substrate via a silicon oxide film.

このとき、シリコン基板の熱膨張係数は3,5×10−
6であるのに対し、シリコン酸化膜の熱膨張係数は0.
5X10−’であり、オーダ的な差があるため、SOI
基板には常に残留応力が存在する。
At this time, the thermal expansion coefficient of the silicon substrate is 3.5 x 10-
6, whereas the thermal expansion coefficient of silicon oxide film is 0.
5X10-', and there is a difference in order, SOI
Residual stress always exists in the substrate.

従って、プロセス中の熱処理によって、SOI基板に大
きな反りが発生する。これは、熱膨張係数の異なる異種
金属の接合で反りが生じるバイメタルの原理と同じとい
える。
Therefore, heat treatment during the process causes large warpage in the SOI substrate. This can be said to be the same principle as that of bimetals, where warping occurs when joining dissimilar metals with different coefficients of thermal expansion.

[発明が解決しようとする課題] このように、上記従来のシリコンウェーハ接着型SOI
基板は、プロセス中の熱処理によって大きな反りが発生
ずるために、このSOI基板上において微細なパターン
を形成する等の微細加工が困難であった。
[Problems to be Solved by the Invention] In this way, the above-mentioned conventional silicon wafer bonded SOI
Since the substrate is greatly warped due to heat treatment during processing, it has been difficult to perform microfabrication such as forming a fine pattern on the SOI substrate.

そこで本発明は、プロセス中の熱処理による反りの発生
を防止し、微細加工の精度を高めることができる半導体
装置及びその製造方法を提供することを目白勺とする。
Therefore, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can prevent warpage caused by heat treatment during processing and improve the precision of microfabrication.

[課題を解決するための手段] 上記課題は、半導体基板と、前記半導体基板の両面にそ
れぞれ形成された第1及び第2の絶縁層と、前記第1及
び第2の絶縁層上にそれぞれ接着接合された第1及び第
2の半導体層とを有することを特徴とする半導体装置に
よって達成される。
[Means for Solving the Problems] The above-mentioned problems include a semiconductor substrate, first and second insulating layers formed on both sides of the semiconductor substrate, and adhesion on the first and second insulating layers, respectively. This is achieved by a semiconductor device characterized by having first and second semiconductor layers that are bonded together.

また上記課題は、第1の半導体基板の両面にそれぞれ第
1及び第2の絶縁層を形成する工程と、前記第1及び第
2の絶縁層上に、それぞれ第2及び第3の半導体基板を
接着接合させる工程と、前記第2及び第3の半導体基板
の各露出面を両面研磨して第1及び第2の半導体層を形
成する工程とを有することを特徴とする半導体装置の製
造方法によって達成される。
The above problem also includes forming first and second insulating layers on both sides of a first semiconductor substrate, and forming second and third semiconductor substrates on the first and second insulating layers, respectively. A method for manufacturing a semiconductor device, comprising the steps of adhesively bonding the exposed surfaces of the second and third semiconductor substrates, and polishing both sides of each exposed surface of the second and third semiconductor substrates to form first and second semiconductor layers. achieved.

[作 用] すなわち本発明は、半導体基板の両面上にそれぞれ絶縁
層を介して半導体薄膜が接@接合されている’!FJ造
となっているために、全体として材質的にもm選的にも
対称となっており、熱処理によって反りが生じることは
ない。
[Function] That is, in the present invention, semiconductor thin films are bonded to both surfaces of a semiconductor substrate via insulating layers, respectively. Due to the FJ construction, the overall structure is symmetrical both in terms of material and selection, and no warpage occurs during heat treatment.

[実施例] 以下、本発明を図示する実施例に基づいて具体的に説明
する。
[Example] The present invention will be specifically described below based on an illustrative example.

第1図は、本発明の一実施例による半導体装置を示す断
面図である。
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

厚さ500μmのシリコン基板2の表裏両面を含む全表
面に、厚さ1〜2μmの熱酸化膜4が形成されている。
A thermal oxide film 4 with a thickness of 1 to 2 μm is formed on the entire surface including both the front and back surfaces of a silicon substrate 2 with a thickness of 500 μm.

この熱酸化WA4を介して、シリコン基板2両面上に、
それぞれ厚さ3〜10JJ、mのシリコン層6.8が形
成されている。なおこのとき、シリコン基板2とシリコ
ン層6.8との面方位は一致するようにしておく。
On both sides of the silicon substrate 2 through this thermally oxidized WA4,
A silicon layer 6.8 is formed, each having a thickness of 3 to 10 JJ, m. At this time, the plane orientations of the silicon substrate 2 and the silicon layer 6.8 are made to match.

こうして、熱酸化膜4とこの熱酸化膜4上のシリコン層
6.8のいずれか一方のシリコン層とによってSOI楕
遣が構成される。
In this way, an SOI ellipse is formed by the thermal oxide film 4 and one of the silicon layers 6 and 8 on the thermal oxide film 4.

このとき、シリコン層6−悲酸化M4−シリコン基板2
−熱酸化膜4−シリコン層8という構造で構成されるS
OI基板は、その表裏において材質的にも構造的にも対
称性が保持されていることにより、シリコン基板2及び
シリコン層6.8の熱膨張係数と熱酸化WA4の熱膨張
係数とのミスマツチングは表裏間でキャンセルされる。
At this time, silicon layer 6 - sad oxidation M4 - silicon substrate 2
S composed of a structure of - thermal oxide film 4 - silicon layer 8
Since the OI substrate maintains symmetry both in terms of material and structure on its front and back sides, mismatching between the thermal expansion coefficients of the silicon substrate 2 and the silicon layer 6.8 and that of the thermally oxidized WA4 is avoided. Cancelled between front and back.

このため、SOI基板を用い、シリコン層6,8のいず
れか一方のシリコン層に半導体素子を形成するプロセス
において熱処理を行なっても、この熱処理によってSO
I基板に大きな反りが発生することはない。
Therefore, even if an SOI substrate is used and heat treatment is performed in the process of forming a semiconductor element on one of the silicon layers 6 and 8, the SOI
No major warping occurs on the I-board.

このように本実施例によれば、SOI基板を材質的、構
造的に表裏対称とすることにより、プロセス中の熱処理
による反りの発生を防止することができる。従って、こ
の平坦なSOI基板を用いたプロセスにおいて、微細パ
ターンを形成する等の微細加工を容易に行なうことがで
き、その精度を高めることができる。
As described above, according to this embodiment, by making the SOI substrate symmetrical in terms of material and structure, it is possible to prevent warping due to heat treatment during the process. Therefore, in a process using this flat SOI substrate, microfabrication such as forming a micropattern can be easily performed, and the precision thereof can be improved.

次に、第2図を用いて、第1図に示す半導体装置の製造
方法を説明する。
Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be explained using FIG. 2.

厚さ500ALmのシリコン基板2の表裏両面を含む全
表面に、厚さ1〜2μmの熱酸化[4を成長させる(第
2図(a))。
Thermal oxidation [4] is grown to a thickness of 1 to 2 μm on the entire surface including both the front and back surfaces of a silicon substrate 2 having a thickness of 500 ALm (FIG. 2(a)).

次いで、シリコン基板2と同じ面方位で、かつ後の工程
において半導体素子を形成するのに必要な所望の比抵抗
を有する厚さ500 u mのシリコン基板10.12
に、例えばHNO3等の酸によってケミカルオキサイド
を形成する親水性処理を行なう、そして表面が親水性と
なったシリコン基板10.12を、熱酸化M4を介して
、シリコン基板2両面上に貼り合わせて圧着する。さら
に温度800℃、30分のアニール処理を酸化性雰囲気
中で行ない、シリコン基板10.12と熱酸化@4とを
原子レベルで接合させる。こうしてシリコン基板2両面
上に、熱酸化膜4を介して、シリコン基板10.12を
接V接合する(第2図(b))。
Next, a silicon substrate 10.12 having a thickness of 500 μm and having the same surface orientation as the silicon substrate 2 and having a desired resistivity necessary for forming a semiconductor element in a later step is prepared.
Then, a hydrophilic treatment is performed to form a chemical oxide using an acid such as HNO3, and the silicon substrate 10.12 whose surface has become hydrophilic is bonded onto both sides of the silicon substrate 2 via thermal oxidation M4. Crimp. Further, an annealing treatment is performed at a temperature of 800° C. for 30 minutes in an oxidizing atmosphere to bond the silicon substrate 10.12 and the thermal oxidation @4 at the atomic level. In this way, the silicon substrates 10 and 12 are V-bonded to both sides of the silicon substrate 2 via the thermal oxide film 4 (FIG. 2(b)).

次いで、例えばアルミナ粉とKOHl又はアルミナ粉と
エチレンジアミン等を用いるメカニカルポリッシュ及び
ゲミカルボリッシュを行ない、シリコン基板10.12
の露出面を同時に研磨する。
Next, mechanical polishing and chemical polishing using, for example, alumina powder and KOHl or alumina powder and ethylenediamine are performed to form the silicon substrate 10.12.
Polish the exposed surface at the same time.

そしてこの両面研磨によって、後の工程において半導体
素子を形成するのに必要な所望の厚さのシリコン層にす
る0例えばここでは、シリコン基板10.12をそれぞ
れ厚さ3〜10μm程度になるまで研磨して、シリコン
層6,8を形成する。
Then, by this double-sided polishing, the silicon layer is polished to a desired thickness necessary for forming a semiconductor element in a later process. Then, silicon layers 6 and 8 are formed.

こうして、熱酸化膜4とこの熱酸化[4上のシリコンN
6,8のいずれか一方のシリコン層とによってSOI構
造を構成するSOI基板を製造する(第2図((:))
In this way, the thermal oxide film 4 and the silicon N on this thermal oxidation [4]
An SOI substrate is manufactured that constitutes an SOI structure with either silicon layer 6 or 8 (Fig. 2 ((:)).
.

本発明は上記実施例に限らず種々の変形が可能である。The present invention is not limited to the above-mentioned embodiments, and various modifications are possible.

例えば、上記実施例では半導体基板をシリコン基板とし
、絶縁層を熱酸化膜とし、半導体層をシリコン層とした
が、他の材料で構成してもよい。
For example, in the above embodiment, the semiconductor substrate is a silicon substrate, the insulating layer is a thermal oxide film, and the semiconductor layer is a silicon layer, but other materials may be used.

[発明の効果〕 以上のように本発明によれば、半導体基板の両面上にそ
れぞれ絶縁層を介して膜厚がほぼ等しい半導体薄膜が接
着接合されている構造とすることにより、全体として材
質的、WJ構造的対称となるようにし、プロセス中の熱
処理による反りの発生を防止することができる。これに
より微細加工の精度を高めることができる。
[Effects of the Invention] As described above, according to the present invention, by creating a structure in which semiconductor thin films of approximately equal film thickness are adhesively bonded on both sides of a semiconductor substrate via insulating layers, the material quality as a whole can be improved. , the WJ structure can be made symmetrical, and warping due to heat treatment during the process can be prevented. This makes it possible to improve the precision of microfabrication.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による半導体装置を示す断面
図、 第2図は第1図の半導体装置の製造方法を示す工程図で
ある。 図において、 2.10.12・・・シリコン基板 4・・・熱酸化膜 6.8・・・シリコン層 2:シリコン基板 4:熱酸化膜 6.8:シリコン層 本発明の一実施例による半導体装置を示す断面図第1図 2:シリコン基板 4:熱酸化膜 10.12:シリコン基板 6.8:シリコン層 第1図の半導体装置の製造方法を示す工程図第2図
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process diagram showing a method for manufacturing the semiconductor device shown in FIG. In the figure, 2.10.12...Silicon substrate 4...Thermal oxide film 6.8...Silicon layer 2: Silicon substrate 4: Thermal oxide film 6.8: Silicon layer According to an embodiment of the present invention Cross-sectional view showing a semiconductor device FIG. 1 FIG. 2: Silicon substrate 4: Thermal oxide film 10.12: Silicon substrate 6.8: Silicon layer FIG.

Claims (1)

【特許請求の範囲】 1、半導体基板と、 前記半導体基板の両面にそれぞれ形成された第1及び第
2の絶縁層と、 前記第1及び第2の絶縁層上にそれぞれ接着接合された
第1及び第2の半導体層と を有することを特徴とする半導体装置。 2、第1の半導体基板の両面にそれぞれ第1及び第2の
絶縁層を形成する工程と、 前記第1及び第2の絶縁層上に、それぞれ第2及び第3
の半導体基板を接着接合させる工程と、前記第2及び第
3の半導体基板の各露出面を両面研磨して第1及び第2
の半導体層を形成する工程と を有することを特徴とする半導体装置の製造方法。
[Claims] 1. A semiconductor substrate; first and second insulating layers respectively formed on both sides of the semiconductor substrate; and a first insulating layer adhesively bonded on the first and second insulating layers, respectively. and a second semiconductor layer. 2. Forming first and second insulating layers on both surfaces of the first semiconductor substrate, respectively; and forming second and third insulating layers on the first and second insulating layers, respectively.
bonding the semiconductor substrates together, and polishing both exposed surfaces of the second and third semiconductor substrates to form the first and second semiconductor substrates.
1. A method for manufacturing a semiconductor device, comprising: forming a semiconductor layer.
JP18098189A 1989-07-12 1989-07-12 Semiconductor device and manufacture thereof Pending JPH0344912A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18098189A JPH0344912A (en) 1989-07-12 1989-07-12 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18098189A JPH0344912A (en) 1989-07-12 1989-07-12 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0344912A true JPH0344912A (en) 1991-02-26

Family

ID=16092661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18098189A Pending JPH0344912A (en) 1989-07-12 1989-07-12 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0344912A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03250615A (en) * 1990-02-28 1991-11-08 Shin Etsu Handotai Co Ltd Manufacture of bonded wafer
JP2007523472A (en) * 2004-01-09 2007-08-16 エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ Substrate with determinable thermal expansion coefficient

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03250615A (en) * 1990-02-28 1991-11-08 Shin Etsu Handotai Co Ltd Manufacture of bonded wafer
JPH0680624B2 (en) * 1990-02-28 1994-10-12 信越半導体株式会社 Method for manufacturing bonded wafer
JP2007523472A (en) * 2004-01-09 2007-08-16 エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ Substrate with determinable thermal expansion coefficient
US20110094668A1 (en) * 2004-01-09 2011-04-28 S.O.I Tec Silicon On Insulator Technologies Substrate with determinate thermal expansion coefficient
JP4745249B2 (en) * 2004-01-09 2011-08-10 エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ Substrate with determinable thermal expansion coefficient

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