JP2848481B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate wiring of a MOS transistor.

[0002]

2. Description of the Related Art In a conventional method of manufacturing a MOS type semiconductor device, first, a thick silicon oxide film serving as an element isolation region is selectively formed, and then a gate oxide film is formed in an element region partitioned by the element isolation region. Then, a gate electrode is formed thereon. In recent years, in order to suppress an increase in gate wiring resistance due to miniaturization of elements,
And, in order to be able to enjoy the advantages of the polysilicon gate technology, which has been widely used,
A technique of forming a gate electrode using a so-called polycide film made of a laminated film of polycrystalline silicon and a high melting point metal silicide such as titanium silicide has been adopted.

A conventional method for manufacturing a semiconductor device having the polycide gate electrode will be described with reference to FIG. 5A to 5C are step-by-step cross-sectional views illustrating a conventional manufacturing method, and FIG. 5D is a plan view illustrating a state after a subsequent impurity doping step is completed. First, a silicon oxide film 2 serving as an element isolation oxide film is formed on a silicon substrate 1 by applying a well-known selective oxidation method, and then a gate oxide film is formed in an element region surrounded by the silicon oxide film 2 by a thermal oxidation method. Form 3 Next, low pressure CVD (LP
A polycrystalline silicon film 4 is deposited on the entire surface by using a (CVD) method, and impurities are diffused to reduce the resistance of the polycrystalline silicon (FIG. 5A).

Further, a high-melting-point metal silicide film 5 made of titanium silicide or the like is deposited on the entire surface by sputtering to further reduce the sheet resistance (FIG. 5B). Next, the refractory metal silicide film 5 is formed using photolithography technology and dry etching technology.
Then, the polycrystalline silicon film 4 is patterned to form a polycide gate electrode 6 (FIG. 5C). Thereafter, an impurity is doped into the surface of the silicon substrate in the active element region to form an impurity diffusion layer 7 serving as a source / drain region (FIG. 5D).

However, in such a method for forming a MOS transistor, as shown in FIG. 5B, a layer composed of a polycrystalline silicon film 4 and a refractory metal silicide film 5 has a silicon oxide film in an element isolation region. 2, a step is generated. Therefore, in the photolithography process, the gate electrode is formed shorter than the mask pattern in the active element region due to a bulk effect and a multiple reflection / interference effect generated in the photoresist due to the step. To cope with this problem, Japanese Patent Application Laid-Open No.
Japanese Patent No. 30774 proposes that a mask pattern of a gate portion formed short as a result of a photolithography process is thickened in advance.

[0006]

In the prior art shown in FIG. 5, the surfaces of the polycrystalline silicon film 4 and the refractory metal silicide film 5 are formed on the surfaces of the element isolation regions as shown in FIG. A step occurs due to the silicon oxide film 2. Therefore, when the photoresist is applied, the photoresist is formed thick on the element region and thin on the element isolation region. As a result, in the element region, the pattern is formed thin due to a bulk effect (a phenomenon in which the width of the pattern is varied due to the difference in the thickness of the photoresist) generated in the photoresist. Furthermore, the pattern in the element region varies due to multiple reflection of exposure light and interference caused at the step. Therefore, in the conventional semiconductor device, the gate length deviates from the design value, and the variation in the gate length becomes large. As a result, the characteristics of the transistor deviate from the design values, and the uniformity of the characteristics is impaired. Was.

On the other hand, Japanese Unexamined Patent Publication No. Hei 4-130774 proposed to cope with the deterioration of the uniformity of the gate length.
The method disclosed in the above publication also has the following problems. In general, the gate length of a MOS transistor is not always constant on a chip, and the shape of the step differs depending on the location. Therefore, in this method, it is necessary to adjust the gate wiring length in the mask design stage so as to compensate for the deviation in the gate length depending on the width of each gate wiring. This places a heavy burden on mask design.
Also in this method, since there is a step due to the element isolation oxide film, the dimensional variation of the gate length due to the bulk effect and the multiple reflection / interference effect of the photoresist cannot be suppressed.

The present invention has been made in view of such circumstances, and an object of the present invention is to enable patterning of a gate electrode to be performed according to design values without variation.

[0009]

According to the present invention, in order to achieve the above object, (1) a step of forming an element isolation oxide film on a silicon substrate by a selective oxidation method to separate and partition an element region; (2) a step of forming a gate oxide film on the semiconductor substrate in the element region by a thermal oxidation method; and (3) a step of forming the element isolation oxide film.
The step amount is determined according to the step amount generated on the silicon substrate surface.
A polycrystalline silicon film having a greater thickness than the silicon substrate
Forming on the entire surface of the upper, (4) the chemical mechanical polishing method and the step of flattening the surface of the polycrystalline silicon film by performing polishing by, (5) a refractory metal silicide film on the planarized surface Forming a gate electrode by patterning the refractory metal silicide film and a polycrystalline silicon film thereunder using a photolithography method. Is done.

Preferably, in the polishing in the step (4), the polycrystalline silicon film on the element isolation oxide film is completely removed, and a part of the element isolation oxide film thereunder is also polished. It is to be removed.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. 1A to 1D are cross-sectional views in the order of steps showing a first embodiment of the present invention, and FIG. 2 is a plan view of a MOS transistor formed by this method. First, a silicon oxide film 2 having a thickness of about 0.6 μm is formed on a silicon substrate 1 by a selective oxidation method called a LOCOS method, and then a gate oxide film 3 is formed by a thermal oxidation method. Next, by a low pressure CVD method, a film thickness of about 0.5
A μm polycrystalline silicon film 4 is deposited. At this time, the polycrystalline silicon is deposited to a thickness equal to or greater than the step formed on the surface. Next, impurity diffusion is performed to lower the resistance of the polycrystalline silicon film (FIG. 1A).

Subsequently, chemical mechanical polishing (CM) shown in FIG.
P) The surface of the polycrystalline silicon film 4 is polished using an apparatus. As shown in FIG. 3, a polishing pad 12 made of polyurethane or the like is mounted on a rotating polishing platen 11, and a slurry as an abrasive is supplied thereon. The silicon wafer 14 holds the rotating vacuum chuck 1
The silicon wafer is pressed against the polishing pad 12 with a predetermined load.

Here, as an example of the polishing conditions, Granzox FGL3900 made by Fujimi is used for the slurry, the slurry supply amount = 50 ml / min, and the polishing platen rotation speed = 35.
rpm, wafer holding vacuum chuck rotation speed = 35 rpm
m, and the applied load of the wafer = 0.44 kg / cm ² . By this polishing, the step of the surface of the polycrystalline silicon film 4 is eliminated and the polycrystalline silicon film 4 is completely flattened (FIG. 1B).

Next, a refractory metal silicide film 5 is deposited on the planarized polycrystalline silicon film 4 by sputtering (FIG. 1C). At this time, the surface of the silicide film 5 is formed extremely flat. Specifically, in the prior art, the step of the silicon oxide film for element isolation is 200
A similar step was also formed on the high melting point metal silicide film because the thickness was about 300 nm. However, in the method of the present invention, the step on the high melting point metal silicide was It can be suppressed to 50 nm or less.

Thereafter, the refractory metal silicide film 5 and the polycrystalline silicon film 4 are patterned by photolithography and dry etching to form a polycide gate electrode 6 (FIG. 1D). In this photolithography technique, the photoresist is applied on a flat surface, so that the photoresist is formed to have a uniform film thickness. In addition, since no step is formed on the surface, multiple reflection and interference caused by the step can be avoided. Therefore, according to the method of the present invention, the pattern of the gate electrode can be formed in accordance with the mask pattern, and the in-plane variation and the variation between wafers can be extremely suppressed.

The polycide gate electrode 6 formed here
Has a laminated structure of a refractory metal silicide film 5 and an extremely thin polycrystalline silicon film 4a on the silicon oxide film 2 in the element isolation region, but the gate wiring resistance is high refractory metal having a lower sheet resistance than polycrystalline silicon. Since it is governed by silicide, the wiring resistance hardly increases. Next, the element region is doped with impurities using the formed gate electrode as a mask to form an impurity diffusion layer 7 serving as a source / drain region (FIG. 2).

Next, a second embodiment of the present invention will be described with reference to FIGS. The state shown in FIG. 4A is the same as that of the first embodiment shown in FIG. 1A, and a description thereof will be omitted. Thereafter, the surface of the polycrystalline silicon film 4 is polished using the chemical mechanical polishing apparatus shown in FIG. At this time, polishing is continued even if the surface of the silicon oxide film 2 is exposed, so that the thickness of the remaining polycrystalline silicon film is about 0.1 μm (FIG. 4B). In this embodiment, since a part of the silicon oxide film 2 is polished, the polishing amount is large and the surface is further planarized. However, the polishing conditions are such that the polishing rates of the polycrystalline silicon film 4 and the silicon oxide film 2 are constant. It is necessary to adjust the conditions.

Next, a refractory metal silicide film 5 is deposited on the polycrystalline silicon film 4 and the silicon oxide film 2 by sputtering (FIG. 4C). Thereafter, the refractory metal silicide film 5 and the polycrystalline silicon film 4 are patterned using a photolithography technique and a dry etching technique to form a polycide gate electrode 6 [FIG.
(D)].

In this photolithography technique,
Since the photoresist is formed to have a uniform film thickness and no step is formed on the surface of the base, the gate electrode pattern can be formed with high accuracy and little variation.
In the polycide gate electrode formed in this embodiment, only the refractory metal silicide film 5 is formed on the silicon oxide film 2 in the element isolation region. Because of the low resistance
The wiring resistance hardly increases as compared with the case of the conventional polycide structure. Thereafter, the element region is doped with impurities using the formed polycide gate electrode as a mask, and source / drain regions (not shown) are formed to form a MOS transistor.

[0020]

As described above, the present invention is to form a polycide gate electrode by flattening a polycrystalline silicon film by a chemical mechanical polishing method and then depositing a refractory metal silicide film thereon. Therefore, a photolithography step for patterning a gate electrode can be performed on a flat surface. Therefore, according to the present invention, the thickness of the photoresist can be made uniform in the plane, and since no step is formed on the underlayer, the bulk effect of the photoresist can be suppressed and the step can be reduced. The resulting multiple reflection and interference can be avoided. As a result, it is possible to form the gate electrode with high accuracy and low variation.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing method according to a first embodiment of the present invention in the order of steps.

FIG. 2 shows a transformer formed according to the first embodiment of the present invention.
Plan view of the register.

FIG. 3 is a schematic view of a chemical mechanical polishing apparatus used in an embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing method according to a second embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view in the order of steps showing a manufacturing method of a conventional example, and a plan view of a MOS transistor formed thereby.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 silicon oxide film 3 gate oxide film 4 polycrystalline silicon film 5 refractory metal silicide film 6 polycide gate electrode 7 impurity diffusion layer 11 polishing platen 12 polishing pad 13 vacuum chuck 14 silicon wafer

Claims (2)

(57) [Claims] (1) a step of forming an element isolation oxide film on a silicon substrate by a selective oxidation method to separate and partition an element region; and (2) a gate on a semiconductor substrate of the element region by a thermal oxidation method. Forming an oxide film; and (3) forming the device isolation oxide film to form the device isolation oxide film.
The step amount is determined according to the step amount generated on the silicon substrate surface.
A polycrystalline silicon film having a greater thickness than the silicon substrate
Forming on the entire surface of the upper, (4) the chemical mechanical polishing method and the step of flattening the surface of the polycrystalline silicon film by performing polishing by, (5) a refractory metal silicide film on the planarized surface Forming a gate electrode by patterning the refractory metal silicide film and the polycrystalline silicon film therebelow by using a photolithography method. Production method. 2. The polishing in the step (4), wherein the polycrystalline silicon film on the element isolation oxide film is completely removed, and a part of the element isolation oxide film thereunder is also polished and removed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein