JPH01181469A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To facilitate high speed operation and high density integration, by forming a polycrystalline silicon wiring layer on a semiconductor substrate, in the manner in which the thickness is large in a transistor region part, and making a polycide structure by arranging high melting point metallic silicide on the polycrystalline silicon. CONSTITUTION:Only the gate wiring of a transistor forming region is constituted by a thick polycrystalline silicon film 14, in order to stabilize element characteristics, and a polycide structure wherein high melting point metallic silicide 16 is formed on the polycrystalline silicon film 14 is made. Since the polycrystalline silicon film 14 of transistor region of the gate wiring is thick, the reaction between a gate oxide film 13 and elements to constitute silicide is restrained, thereby enabling the manufacture of a semiconductor device having stable element characteristics. Further, since a polycrystalline silicon film 16 to constitute the wiring except the transistor region is thin, the step-difference is reduced, and the later manufacturing process is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device having a gate wiring structure with low gate delay and easy stabilization of the transistor portion, and a method for manufacturing the same. be.

Conventional technology - The gate wiring structure of a conventional semiconductor device consists of high melting point metal silicide 1 on polycrystalline silicon 19, as shown in FIG.
6, or a single layer structure using polycrystalline silicon or high melting point metal silicide.

In FIG. 4, 11 is a semiconductor substrate, 12 is a field oxide film, 19 is polycrystalline silicon, 16 is a refractory metal silicide, 13 is a gate oxide film, 17 is an insulating film, and 18 is an aluminum wiring.

Problems to be Solved by the Invention However, with the structure described above, when semiconductor devices become faster and more highly integrated, interconnect delay becomes a problem with polycrystalline silicon gates, and high-melting point metal silicide gates and polycide gates become problematic. Deterioration of device characteristics due to reaction between the gate oxide film and gate material and deterioration of device characteristics due to the influence of impurities in the gate material have become issues.

In view of these problems, the present invention forms a gate wiring structure in a semiconductor device that has less wiring delay and can easily stabilize element characteristics.

Means for Solving the Problems In order to solve the above problems, in the present invention, a thick polycrystalline silicon film is formed so that the device characteristics are stabilized only for the gate wiring in the transistor formation region, and a high melting point film is formed on the polycrystalline silicon film. It has a polycide structure in which metal silicide is formed.

That is, the present invention provides a polycrystalline silicon wiring layer on a semiconductor substrate, in which all of the polycrystalline silicon wiring layer serving as a gate electrode is formed, and a portion of the polycrystalline silicon film in a portion of the polycrystalline silicon wiring layer other than the transistor region is removed by etching. It has a polycide structure in which high melting point metal silicide is formed on a silicon film.

Alternatively, a structure may be adopted in which all of the polycrystalline silicon film in areas other than the transistor region is removed.

According to the present invention, since the polycrystalline silicon film in the transistor region of the gate wiring is thick, the reaction between the gate oxide film and the silicide constituent elements is suppressed, so that it is possible to manufacture a semiconductor device with stable device characteristics.

Furthermore, since the polycrystalline silicon film constituting the gate wiring in areas other than the transistor region is thin, the step difference is reduced and subsequent manufacturing processes are facilitated.

EXAMPLE The structure of an apparatus according to an embodiment of the present invention is shown in FIG. 1, and the manufacturing process thereof is shown in FIG. In FIG. 1, 11 is a semiconductor substrate;
12 is a selective oxide film, 13 is a gate oxide film, 14 is polycrystalline silicon in the transistor region, 16 is polycrystalline silicon in areas other than the transistor region, 17 is an interlayer insulating film, and 18 is an aluminum wiring.

Figure 2 shows the manufacturing process of this device. First, as shown in FIG. 2A, polycrystalline silicon 15 of, for example, 200 mm is formed on gate oxide film 13 formed by a conventional method. At this time, the polycrystalline silicon film is formed to have the same thickness in the transistor formation region and on the selective oxide film. After applying a photoresist on top of the photoresist and performing uniform etching of the photoresist and polycrystalline silicon, the photoresist is removed, and as shown in Figure 2, the polycrystalline silicon film in the transistor region becomes thicker. Until then, the polycrystalline silicon 16 on the selective oxide film is formed thin. At this time, etching is performed so that the thickness of the polycrystalline silicon film 14 in the transistor region becomes 100 Å or more. However, the polycrystalline silicon film 16 on the selective oxide film may be removed. Further, a high melting point metal silicide 16 is formed on the polycrystalline silicon 14.15. For example, if 3,000 people are formed with wsi2f, a sheet resistance of about 3 to 4 Ω/mouth can be obtained.

Note that the high melting point metal silicide is WSi2.
Besides, TaSi2 and MoSi2 may also be used. Next, the high melting point metal silicide 16 and polycrystalline silicon 14.degree. 16 are etched using a resist mask with a predetermined pattern to form an electrode pattern. After removing the resist mask, a glabellar insulating film 17 is formed, a contact hole is formed, and then an aluminum wiring 18 is formed.

In the above formation method, when impurity is implanted into the polycrystalline silicon 14.15, good characteristics of gate oxide film breakdown voltage can be obtained by either POCe5 diffusion or the adjacent ion implantation method. In addition, the polycide wiring on the selective oxide film 12 can be formed thinly,
It is possible to reduce the level difference.

Alternatively, as shown in FIG. 3, polycrystalline silicon 20 may be formed only in the transistor region using a photoresist pattern.

Effects of the Invention According to the present invention, high speed and high integration of semiconductor devices can be easily achieved without losing the characteristics of conventional stable polycrystalline silicon gate elements.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a semiconductor device of the embodiment of FIG. FIG. 4 is a cross-sectional view of a semiconductor device using a conventional polycide structure. 11... Semiconductor substrate, 12... Selective oxide film, 13... Gate oxide film, 14.15...
... Polycrystalline silicon, 16 ... High melting point metal silicide, 17 ... Interlayer insulating film, 18 ...
...Aluminum wiring, 2o...Polycrystalline silicon in the transistor area. Name of agent: Patent attorney Toshio Nakao and 1 other person/l
-Toto board/2-i-"1-Ashii Patari/3-m-Taihi"Monday 1/4.15--Ita φ Sango Solicon/6---4 The larva is a big fish.
Between, Loquat strain/δ---Aluminum wiring Figure 1 Figure 2/4 Figure 3 73/I

Claims (2)

[Claims] (1) A polycrystalline silicon interconnection layer serving as a gate electrode is provided on a semiconductor substrate, the polycrystalline silicon interconnection layer is formed thickly in the transistor region, and a refractory metal silicide is provided on the polycrystalline silicon to form a polycide structure. semiconductor device. (2) Form a polycrystalline silicon film that will become a gate electrode on a semiconductor substrate, and remove a portion of the polycrystalline silicon from the polycrystalline silicon film outside the transistor area by etching away the polycrystalline silicon film to form a thick polycrystalline silicon film in the transistor area. A method for manufacturing a semiconductor device, comprising forming a wiring layer, and providing a refractory metal silicide on the polycrystalline silicon wiring layer to form a polycide structure.