JPS6235555A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6235555A
JPS6235555A JP17676985A JP17676985A JPS6235555A JP S6235555 A JPS6235555 A JP S6235555A JP 17676985 A JP17676985 A JP 17676985A JP 17676985 A JP17676985 A JP 17676985A JP S6235555 A JPS6235555 A JP S6235555A
Authority
JP
Japan
Prior art keywords
polysilicon
film
semiconductor device
oxide film
resistance part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17676985A
Other languages
Japanese (ja)
Inventor
Toru Ueda
徹 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP17676985A priority Critical patent/JPS6235555A/en
Publication of JPS6235555A publication Critical patent/JPS6235555A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the size and to increase the density of a semiconductor device by performing separation between polysilicon films by means of a polysilicon oxide film. CONSTITUTION:After an active region 12 is formed on a semiconductor substrate 11, a polysilicon film 14 is accumulated on the entire surface through an insulat ing film 13. Individual polysilicon films are separated therebetween by a normal locos method. After a thin polysilicon oxide film 15 is formed by thermal oxida tion, a nitride film 15 is accumulated and patterned. Then, a locus oxide film 17 is formed. The nitride film of a high resistor is removed. An oxide film 17' is formed by selective oxidation. After the film 16 is separated, high density ions are implanted to low resistors D, F. After an insulating film 18 is accumulat ed, it is treated at high temperature to form low resistors D', F'. Then, a contacting hole is opened, aluminum wiring electrode 19 is formed to complete a semiconductor device. The length of the resistor E' is shortened from L to L ' by lateral diffusion of an impurity at heat treating time for activating the ion implanted impurity.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、高抵抗部(抵抗素子部分)と低抵抗部(接続
配線部分)とを含む複数のポリシリコン膜を有する半導
体装置、及びその製造方法に関するものである。
Detailed Description of the Invention <Industrial Application Field> The present invention relates to a semiconductor device having a plurality of polysilicon films including a high resistance part (resistance element part) and a low resistance part (connection wiring part), and a semiconductor device thereof. This relates to a manufacturing method.

〈従来の技術〉 近年のLSIの集積化に伴なって、例えば、スタチック
型のメモリ素子等では、セル内の負荷素子に半導体素子
を用いるようになってきている。
<Prior Art> With the recent integration of LSIs, semiconductor elements have been used as load elements in cells, for example, in static type memory elements.

プロセスの簡易さからポリシリコンにより抵抗素子を形
成するのが盛んである。
Resistance elements are often formed from polysilicon because of the simplicity of the process.

第2図に従来の半導体装置の構造及びその製造工程の一
例を示す。
FIG. 2 shows an example of the structure of a conventional semiconductor device and its manufacturing process.

半導体基板1に活性領域2を形成した後、絶縁膜3を介
して全面にポリシリコン膜4を形成する。
After forming an active region 2 on a semiconductor substrate 1, a polysilicon film 4 is formed on the entire surface with an insulating film 3 interposed therebetween.

ポリシリコン膜4をバターニング後、レジスト5する。After patterning the polysilicon film 4, a resist 5 is applied.

Bは高抵抗部丸である。レジスト5を除去し、絶縁膜6
を形成した後、イオン注入した不純物の活性化の為の熱
処理を施し、低抵抗部A′、σを形成する。コンタクト
ホールを開けた後、アルミ配線電極7を設け、半導体装
置を完成する。イオン注入した不純物の活性化の為の熱
処理時に、不純物の横方向拡散により高抵抗部(抵抗素
子部分)B′の長さはLからL′に縮小される。高抵抗
値はL′により決定される。
B is the high resistance circle. Remove the resist 5 and remove the insulating film 6.
After forming , heat treatment is performed to activate the ion-implanted impurities to form low resistance parts A' and σ. After opening the contact holes, aluminum wiring electrodes 7 are provided to complete the semiconductor device. During heat treatment for activating the ion-implanted impurities, the length of the high resistance portion (resistance element portion) B' is reduced from L to L' due to lateral diffusion of the impurities. The high resistance value is determined by L'.

〈発明が解決しようとする問題点〉 しかしながら、上記従来の半導体装置は、その高い抵抗
値の制御ということで、高抵抗部の素子寸法が大きくな
るという問題点を有していた。
<Problems to be Solved by the Invention> However, the conventional semiconductor device described above has a problem in that the element size of the high resistance portion becomes large due to the control of the high resistance value.

本発明は上記の点に鑑みてなされたものであり、高抵抗
部の素子寸法が非常に小さい半導体装置及びその製造方
法を提供することを目的としているものである。
The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device in which the element size of the high resistance portion is extremely small, and a method for manufacturing the same.

く問題点を解決するだめの手段〉 複数のポリシリコン膜間の分離をポリシリコン酸化膜に
よって行うと共に、高抵抗部のポリシリコン膜厚を低抵
抗部のポリシリコン膜厚より薄くする。ポリシリコン膜
間を分離するポリシリコン酸化膜形成のための第1の選
択酸化工程と、高抵抗部薄膜化のための第2の選択酸化
工程とを設ける。
[Means to Solve the Problem] A plurality of polysilicon films are separated by a polysilicon oxide film, and the thickness of the polysilicon film in the high resistance part is made thinner than the thickness of the polysilicon film in the low resistance part. A first selective oxidation step for forming a polysilicon oxide film that separates polysilicon films, and a second selective oxidation step for thinning a high-resistance portion are provided.

〈実施例〉 第1図に、本発明に係る半導体装置の構造及びその製造
工程を示す。
<Example> FIG. 1 shows the structure of a semiconductor device and its manufacturing process according to the present invention.

(1)半導体基板11に活性領域12を形成した後、絶
縁膜13を介して全面にポリシリコン膜14を3000
A堆積する。
(1) After forming the active region 12 on the semiconductor substrate 11, a polysilicon film 14 is formed on the entire surface with a film thickness of 3000 nm with an insulating film 13 interposed therebetween.
A Deposit.

(2)通常のロコス法により個々のポリシリコン膜間を
素子分離する。熱酸化により薄いポリシリコン酸化膜1
5を形成した後、CVD法で窒化膜(5i3N4)16
を堆積し、ドライエツチング法でパターニングする。そ
して、窒化膜16を酸化マスクとして、ポリシリコン膜
間分離のためのロコス酸化膜17を形成する。
(2) Element isolation between individual polysilicon films is performed using the usual LOCOS method. Thin polysilicon oxide film 1 by thermal oxidation
After forming 5, a nitride film (5i3N4) 16 is formed by CVD method.
is deposited and patterned using a dry etching method. Then, using the nitride film 16 as an oxidation mask, a LOCOS oxide film 17 for isolation between polysilicon films is formed.

(3)高抵抗部の窒化膜をエツチングによシ除去する。(3) Remove the nitride film in the high resistance area by etching.

(4)選択酸化(ロコス法)して、酸化膜17′を形成
する。窒化膜16を剥離した後、酸化膜17′をイオン
注入のマスクとして、低抵抗部り、Fに高濃度イオン注
入する。Eは高抵抗部である。
(4) Selective oxidation (LOCOS method) is performed to form an oxide film 17'. After peeling off the nitride film 16, high concentration ions are implanted into F into the low resistance portion using the oxide film 17' as a mask for ion implantation. E is a high resistance part.

酸化膜17′は、イオン注入のマスク性及び上層ドープ
ドガラス層からの影響を考慮すると、1000A以上は
必要である。
The oxide film 17' needs to have a thickness of 1000 A or more, considering the masking properties of ion implantation and the influence from the upper doped glass layer.

(5)絶縁膜(ドープドガラス層)18を堆積した後、
イオン注入した不純物の活性化のための高温処理を施し
、低抵抗部D’、F’を形成する。次に、コンタクトホ
ールを開孔し、アルミ配線電極19を設けて、半導体装
置を完成する。
(5) After depositing the insulating film (doped glass layer) 18,
A high temperature treatment is performed to activate the ion-implanted impurities to form low resistance parts D' and F'. Next, contact holes are opened and aluminum wiring electrodes 19 are provided to complete the semiconductor device.

イオン注入した不純物の活性化の為の熱処理時に、不純
物の横方向拡散により高抵抗部(抵抗素子部分)E′の
長さはLからL′に縮小される。高低とにより、初期膜
厚dの時と比べて、著しく抵抗値を増大させることがで
き、L′をより小さくすることが可能となる。
During the heat treatment for activating the ion-implanted impurities, the length of the high resistance portion (resistance element portion) E' is reduced from L to L' due to lateral diffusion of the impurities. Due to the height, the resistance value can be significantly increased compared to the initial film thickness d, and L' can be made smaller.

上記実施例に於いては、イオン注入により低抵抗部形成
のための不純物導入を行っているが、イオン注入の代わ
りに熱拡散によってもよい。
In the above embodiment, impurities are introduced to form the low resistance portion by ion implantation, but thermal diffusion may be used instead of ion implantation.

〈発明の効果〉 以上詳細に説明したように本発明によれば、高抵抗部(
抵抗素子部分)と低抵抗部(接続配線部分)とを含む複
数のポリシリコン膜を有する半導体装置に於いて、高抵
抗部の素子寸法を非常に小さくすることができるもので
あり、これにより半導体装置の小型化・高密度化が達成
されるものである。
<Effects of the Invention> As explained in detail above, according to the present invention, the high resistance portion (
In a semiconductor device having multiple polysilicon films including a resistance element part) and a low resistance part (connection wiring part), the element dimensions of the high resistance part can be made extremely small. This makes it possible to downsize and increase the density of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る半導体装置の構造及びその製造工
程を示す図、第2図は従来の半導体装置の構造及びその
製造工程の一例を示す図である。 11:半導体基板、12:活性領域、 13 、18 :絶縁膜、14;ポリシリコン膜、15
:薄いポリシリコン酸化膜、16:窒化膜、17.17
’:ロコス酸化膜、19;アルミ配線電極、D’、F’
:低抵抗部、E′:高抵抗部。 代理人 弁理士 福 士 愛 彦(他2名)事11−P
優3半1休襄藁一番諺 腹Fぞめ情1畑:C奨乞示す面 填1図
FIG. 1 is a diagram showing the structure of a semiconductor device and its manufacturing process according to the present invention, and FIG. 2 is a diagram showing an example of the structure of a conventional semiconductor device and its manufacturing process. 11: Semiconductor substrate, 12: Active region, 13, 18: Insulating film, 14: Polysilicon film, 15
: Thin polysilicon oxide film, 16: Nitride film, 17.17
': LOCOS oxide film, 19; aluminum wiring electrode, D', F'
: low resistance part, E': high resistance part. Agent Patent Attorney Aihiko Fuku (and 2 others) Matter 11-P
Yu 3 and a half 1 resting straw first proverb F zomejo 1 field: C encouragement 1 picture

Claims (3)

【特許請求の範囲】[Claims] (1)高抵抗部(抵抗素子部分)と低抵抗部(接続配線
部分)とを含む複数のポリシリコン膜を有する半導体装
置に於いて、上記複数のポリシリコン膜間の分離をポリ
シリコン酸化膜によって行うと共に、上記高抵抗部のポ
リシリコン膜厚を上記低抵抗部のポリシリコン膜厚より
薄くしたことを特徴とする半導体装置。
(1) In a semiconductor device having a plurality of polysilicon films including a high resistance part (resistance element part) and a low resistance part (connection wiring part), the separation between the plurality of polysilicon films is performed using a polysilicon oxide film. A semiconductor device characterized in that the polysilicon film thickness of the high resistance part is made thinner than the polysilicon film thickness of the low resistance part.
(2)高抵抗部(抵抗素子部分)と低抵抗部(接続配線
部分)とを含む複数のポリシリコン膜を有する半導体装
置であって、上記複数のポリシリコン膜間の分離をポリ
シリコン酸化膜によって行うと共に、上記高抵抗部のポ
リシリコン膜厚を上記低抵抗部のポリシリコン膜厚より
薄くした半導体装置の製造方法に於いて、上記ポリシリ
コン膜間を分離するポリシリコン酸化膜形成のための第
1の選択酸化工程と、上記高抵抗部薄膜化のための第2
の選択酸化工程とを設けたことを特徴とする、半導体装
置の製造方法。
(2) A semiconductor device having a plurality of polysilicon films including a high resistance part (resistance element part) and a low resistance part (connection wiring part), in which the separation between the plurality of polysilicon films is formed by a polysilicon oxide film. In the method for manufacturing a semiconductor device in which the polysilicon film thickness of the high resistance part is made thinner than the polysilicon film thickness of the low resistance part, for forming a polysilicon oxide film separating the polysilicon films. a first selective oxidation step, and a second selective oxidation step for thinning the high-resistance portion.
1. A method for manufacturing a semiconductor device, comprising: a selective oxidation step.
(3)第2の選択酸化工程によって高抵抗部上に形成さ
れたポリシリコン酸化膜をマスクにして、低抵抗部形成
のための不純物イオン注入又は不純物熱拡散を行うこと
を特徴とする、特許請求の範囲第(2)項に記載の半導
体装置の製造方法。
(3) A patent characterized in that impurity ion implantation or impurity thermal diffusion for forming a low resistance part is performed using the polysilicon oxide film formed on the high resistance part by the second selective oxidation process as a mask. A method for manufacturing a semiconductor device according to claim (2).
JP17676985A 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof Pending JPS6235555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17676985A JPS6235555A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17676985A JPS6235555A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6235555A true JPS6235555A (en) 1987-02-16

Family

ID=16019501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17676985A Pending JPS6235555A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6235555A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413841B1 (en) 1998-10-22 2002-07-02 Nec Corporation MOS type semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6413841B1 (en) 1998-10-22 2002-07-02 Nec Corporation MOS type semiconductor device and manufacturing method thereof

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