JPS61264763A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS61264763A JPS61264763A JP10651985A JP10651985A JPS61264763A JP S61264763 A JPS61264763 A JP S61264763A JP 10651985 A JP10651985 A JP 10651985A JP 10651985 A JP10651985 A JP 10651985A JP S61264763 A JPS61264763 A JP S61264763A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- silicon film
- gate electrode
- adhered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 239000012535 impurity Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 238000009413 insulation Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、8縁ゲ一ト屋電界効果半導体装置の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an eight-edge gate field effect semiconductor device.
第2図軸(a)、(b)は従来の半導体装置、例えば絶
縁ゲート屋電界効果半導体装置を示す断面図である。こ
の図において、1はシリフン基板、2はフィールド酸化
膜、3はゲート絶縁膜、4はゲート電極、5は絶縁膜で
、例えば二酸化シリコン膜であり、T、8はそれぞれソ
ース、ドレイン領域である。Axes (a) and (b) of FIG. 2 are cross-sectional views showing a conventional semiconductor device, for example, an insulated gate field effect semiconductor device. In this figure, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate insulating film, 4 is a gate electrode, 5 is an insulating film, for example, a silicon dioxide film, and T and 8 are source and drain regions, respectively. .
次Vcll造方法について説明する。まず、第2ry!
J(a)のように−導電型のシリコン基・板1′%:用
いてゲート絶縁膜SV介して多結晶シリコンが被着され
る。その後、7オトエツチング法により後にゲート電極
4となるべき部分にのみ多結晶シリコン票
を残して除去される。この用いたフォトレジスト(図示
せず)tマスクとして不純物tイオン注入法でソース領
域7.ドレイン領域8に導入する。Next, the Vclll construction method will be explained. First, the 2nd ry!
As shown in J(a), polycrystalline silicon is deposited via the gate insulating film SV using a -conductivity type silicon substrate/plate 1'%. Thereafter, the polycrystalline silicon chip is removed by a 7-to-etching method, leaving a polycrystalline silicon chip only in the portion that will later become the gate electrode 4. This photoresist (not shown) was used as a mask for impurity ion implantation in the source region 7. is introduced into the drain region 8.
その後、第2図(b)のようにシリコン基板1全面に二
酸化シリコン膜5を被着する。Thereafter, a silicon dioxide film 5 is deposited on the entire surface of the silicon substrate 1 as shown in FIG. 2(b).
従来の絶縁ゲート型電界効果半導体装置の製造方法は以
上のように、ゲート絶縁II1.3によってシリコン基
板1と接続されているゲート電極4上からイオン注入を
行うため忙、注入イオンによる電荷の蓄積によってゲー
ト絶縁膜3に大きな電界がかかり、絶縁膜破壊が多発す
るという問題点があった。As described above, in the conventional manufacturing method of an insulated gate type field effect semiconductor device, ions are implanted from above the gate electrode 4 connected to the silicon substrate 1 through the gate insulation II1. Therefore, a large electric field is applied to the gate insulating film 3, resulting in frequent breakdown of the insulating film.
この預明は、上記のような問題点を解消するためKなさ
れkもので、イオン注入時にゲート絶縁膜Kかかる電界
を小さくすることkより、破壊を防止することができる
絶縁ゲート型電界効果半導体装置の製造方法を提供する
ことな目的とする。This promise was made in order to solve the above-mentioned problems, and by reducing the electric field applied to the gate insulating film during ion implantation, an insulated gate field effect semiconductor can be prevented from being destroyed. The purpose is to provide a method for manufacturing the device.
この発明忙係る絶縁ゲート屋電界効果半導体装置の製造
方法は、ゲート電極形成後に多結晶シリコン膜を基板全
面に被層し、その上からイオン注入を行い、熱酸化処理
を施して不純物を活性化すると同時に、多結晶シリコン
膜を酸化させるものである。The method for manufacturing an insulated gate field effect semiconductor device according to the present invention is to cover the entire surface of the substrate with a polycrystalline silicon film after forming the gate electrode, implant ions over the film, and perform thermal oxidation treatment to activate impurities. At the same time, the polycrystalline silicon film is oxidized.
〔作用、〕
この発明においては、ゲート電極と半導体基板を電気的
に接続することkよりイオン注入時に電荷がゲート電極
上化蓄積されるのt防ぎ、ゲート絶謙膜の破壊を防止す
る。[Function] In the present invention, by electrically connecting the gate electrode and the semiconductor substrate, charges are prevented from being accumulated on the gate electrode during ion implantation, and damage to the gate insulation film is prevented.
この発明の一実施例Vat図(a)、 (b)、 (c
) Vc示す。まず、−導電屋、例えばNuのシリコン
基板1の主表面に厚さ8000Aの二酸化シリコン膜か
らなるフィールド酸化膜2と厚さ400Aの二酸化シリ
コン膜からなるゲート絶縁膜3t、それぞれ所定の位置
に被着する。次k、後にゲート電極4となる多結晶シリ
コン膜を厚さ5000Aで被着し、その後、熱酸化によ
り多結晶シリコン膜の表面に2000Aだけ酸化された
二酸化シリコン膜5が被着される。その後、フォトエツ
チング法により後にゲート電極4となるべき部分にのみ
ゲート電極4となる多結晶シリコン膜と、その上の二酸
化シリコン膜、およびゲート絶縁膜3となる二酸化シリ
コン膜は残して他は除去する。この状態が第1図(&)
である。One embodiment of this invention Vat diagrams (a), (b), (c
) Vc is shown. First, a field oxide film 2 made of a silicon dioxide film with a thickness of 8000 Å and a gate insulating film 3t made of a silicon dioxide film with a thickness of 400 Å are coated on the main surface of a silicon substrate 1 made of conductive material, for example Nu, at predetermined positions. wear it. Next, a polycrystalline silicon film that will later become the gate electrode 4 is deposited to a thickness of 5000 Å, and then a silicon dioxide film 5 oxidized by 2000 Å is deposited on the surface of the polycrystalline silicon film by thermal oxidation. Then, by photo-etching, the polycrystalline silicon film that will become the gate electrode 4, the silicon dioxide film above it, and the silicon dioxide film that will become the gate insulating film 3 are left only in the part that will later become the gate electrode 4, and the rest is removed. do. This state is shown in Figure 1 (&)
It is.
次に第1図(b)のようK、多結晶シリフン膜6を厚さ
IGOOAで被着する。その後、イオン注入法化より加
速エネルギー40に@Vでドーズ量5X10”個/ c
m”の条件でボロン原子tソース領域1とドレイン領域
8に打ち込む。次に、シリコン基板1に熱酸化処理を施
すことにより多結晶シリコン膜6を二酸化シリコン膜9
にする。この工程中に、ソース領域7とドレイン領域8
のポロンは活性化される。このよう忙して形成された半
導体装置v#It図(c) K示す。Next, as shown in FIG. 1(b), a K polycrystalline silicon film 6 is deposited to a thickness of IGOOA. After that, by using the ion implantation method, the acceleration energy was set to 40 @V and the dose was 5 x 10"/c.
Boron atoms are implanted into the source region 1 and drain region 8 under conditions of t.
Make it. During this process, source region 7 and drain region 8
porons are activated. The semiconductor device v#It that was formed in this way is shown in FIG.
この実施例においては、ソース領域7とドレイン領域8
にイオン注入法で不純物を導入する際。In this embodiment, source region 7 and drain region 8
When introducing impurities using ion implantation method.
ゲート絶縁膜3の周りが多結晶シリフン膜6で囲まれて
いるため、ゲート絶縁膜3に電界がかかることもなく、
ゲート絶縁膜3の破壊は生じない。Since the gate insulating film 3 is surrounded by the polycrystalline silicon film 6, no electric field is applied to the gate insulating film 3.
Destruction of the gate insulating film 3 does not occur.
なお、上記実施例では、ゲート絶縁膜3に二酸化シリコ
ン膜を用いた場合について説明したが、窒化シリコン膜
やリンガラス膜を用いてもよい。In the above embodiment, the case where a silicon dioxide film is used as the gate insulating film 3 has been described, but a silicon nitride film or a phosphorus glass film may also be used.
この発明は以上説明したとおり、イオン注入が多結晶シ
リコン膜ン介して行われるkめ、ソース領域、ドレイン
領域形成時にゲート電極が半導体基板から絶縁されない
状態となり、イオン注入によるゲート絶縁膜の破壊を防
止できるという効果がある。As explained above, in this invention, since ion implantation is performed through a polycrystalline silicon film, the gate electrode is not insulated from the semiconductor substrate when forming the source and drain regions, which prevents the breakdown of the gate insulating film due to ion implantation. It has the effect of preventing
第1図(aハ(b)、 (c)はこの発明の一実施例を
示す製造工程の説明図、第2図(a)、(b)は従来の
半導体装置の製造工程の説明図である。
図において、1はシリコン基板、3はゲート絶縁膜、4
はゲート電極、5,9は二・酸化シリコン膜、6は多結
晶シリコン膜、7はソース領域、8はドレイン領域であ
る。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大岩増雄 (外2名)
第1図
第2図
ム
手続補正書(自発)
1、事件の表示 特願昭eo−toests号26
発明の名称 半導体装置の製造方法3、補正をする
者
5、補正の対象
図面
う、補正の内容
第1図(b)、(C)を別紙のように補正する。
以上1(a)(b) and (c) are explanatory diagrams of the manufacturing process showing one embodiment of the present invention, and FIGS. 2(a) and (b) are explanatory diagrams of the manufacturing process of a conventional semiconductor device. In the figure, 1 is a silicon substrate, 3 is a gate insulating film, and 4 is a silicon substrate.
is a gate electrode, 5 and 9 are silicon dioxide films, 6 is a polycrystalline silicon film, 7 is a source region, and 8 is a drain region. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others) Figure 1 Figure 2 Mu procedural amendment (voluntary) 1. Indication of the case Patent application Sho EO-TOESTS No. 26
Title of the invention: Method for manufacturing a semiconductor device 3; Person making the amendment 5; Drawings to be amended; Contents of the amendment; Figures 1(b) and 1(C) are amended as shown in the attached sheet. that's all
Claims (1)
化シリコン膜を順次形成する工程と、ソース領域とドレ
イン領域上の前記各膜を除去してゲート電極を形成した
後、全面に多結晶シリコン膜を形成する工程と、この多
結晶シリコン膜を介して前記ソース領域とドレイン領域
にイオン注入を行い、次に熱酸化処理を施すことによつ
て注入した不純物を活性化すると同時に前記多結晶シリ
コン膜を酸化する工程とを含むことを特徴とする半導体
装置の製造方法。A process of sequentially forming a gate insulating film, a polycrystalline silicon film, and a silicon dioxide film on a semiconductor substrate, and after removing each of the above films on the source region and drain region to form a gate electrode, a polycrystalline silicon film is formed on the entire surface. ion implantation into the source and drain regions through this polycrystalline silicon film, and then thermal oxidation treatment to activate the implanted impurities and at the same time remove the polycrystalline silicon film. A method for manufacturing a semiconductor device, the method comprising: oxidizing a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10651985A JPS61264763A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10651985A JPS61264763A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61264763A true JPS61264763A (en) | 1986-11-22 |
Family
ID=14435651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10651985A Pending JPS61264763A (en) | 1985-05-17 | 1985-05-17 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61264763A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04165616A (en) * | 1990-10-30 | 1992-06-11 | Nec Corp | Method of forming diffused layer |
US6372611B1 (en) | 1997-01-24 | 2002-04-16 | Nec Corporation | Semiconductor manufacturing method including gettering of metal impurities |
-
1985
- 1985-05-17 JP JP10651985A patent/JPS61264763A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04165616A (en) * | 1990-10-30 | 1992-06-11 | Nec Corp | Method of forming diffused layer |
US6372611B1 (en) | 1997-01-24 | 2002-04-16 | Nec Corporation | Semiconductor manufacturing method including gettering of metal impurities |
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