JPS6350015A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6350015A JPS6350015A JP19454486A JP19454486A JPS6350015A JP S6350015 A JPS6350015 A JP S6350015A JP 19454486 A JP19454486 A JP 19454486A JP 19454486 A JP19454486 A JP 19454486A JP S6350015 A JPS6350015 A JP S6350015A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- semiconductor substrate
- oxide film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 150000002500 ions Chemical class 0.000 claims abstract description 14
- 239000010409 thin film Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 44
- 238000009792 diffusion process Methods 0.000 abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 6
- -1 boron ions Chemical class 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 239000004411 aluminium Substances 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置製造方法に関し、特に半導体基板
表面に所望の不純物をイオン注入する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for ion-implanting desired impurities into the surface of a semiconductor substrate.
従来、この種の半導体装置製造方法は、半導体基板表面
にイオン注入のマスク材料としてレジストを用いて所望
のマスクパターンを形成し前記マスクパターンを通して
不純物をイオン注入し、半導体基板表面に所望の不純物
領域を形成していた。Conventionally, this type of semiconductor device manufacturing method uses a resist as a mask material for ion implantation to form a desired mask pattern on the surface of a semiconductor substrate, and implants impurity ions through the mask pattern to form a desired impurity region on the surface of the semiconductor substrate. was forming.
上述した従来の半導体装置製造方法は、イオン注入マス
クパターンをレジストを半導体基板表面に塗布、被着形
成後、所定のパターンによって写真蝕刻形成していた為
、絶縁物質であるレジスト中に、イオン他人時の不純物
イオンの電荷が蓄損し、半導体基板とレジストとの間に
放電現象が発生し、半導体基板上の特にＭＯ８型トラン
ジスタのゲート絶縁膜の様な薄い絶縁膜が破壊されると
いう欠点がおった。In the conventional semiconductor device manufacturing method described above, an ion implantation mask pattern is formed by coating a resist on the surface of a semiconductor substrate, depositing it, and then photo-etching it according to a predetermined pattern. The drawback is that the charge of impurity ions accumulates and dissipates, and a discharge phenomenon occurs between the semiconductor substrate and the resist, which destroys the thin insulating film on the semiconductor substrate, especially the gate insulating film of the MO8 type transistor. Ta.
上述した従来の半導体装置製造方法に対して、本発明は
半導体基板及び半導体基板表面上の薄い絶縁膜等をイオ
ン注入時のマスク材と電界的にシールドする効果が得ら
れ、かつ、イオン注入時、所望の不純物イオンが透過可
能な導電性薄膜を形成することである。更に、上述した
導電性薄膜は、イオン注入装置に半導体基板を固定する
際に、−定電位に保たれた導電性クランプで固定するこ
とにより一層の効果が得られる。In contrast to the conventional semiconductor device manufacturing method described above, the present invention has the effect of electrically shielding a semiconductor substrate and a thin insulating film on the surface of the semiconductor substrate with a mask material during ion implantation. , to form a conductive thin film through which desired impurity ions can pass. Further, when the above-mentioned conductive thin film is fixed to the ion implantation apparatus, a further effect can be obtained by fixing the semiconductor substrate with a conductive clamp maintained at a constant potential of -.
本発明の半導体装置の製造方法は、半導体基板上全面に
導電性薄膜を形成する工程と、前記導電性薄膜上全面に
イオン注入時のイオン？マスキングするマスク材料を形
成する工程と、前記マスク材料を必要な部分金銭して除
去する工程と、所望する不純物を前記半導体基板表面に
イオン注入する工程金倉んで構成さｊ、る。The method for manufacturing a semiconductor device of the present invention includes a step of forming a conductive thin film on the entire surface of the semiconductor substrate, and a step of forming ions during ion implantation on the entire surface of the conductive thin film. The method is comprised of a step of forming a mask material for masking, a step of removing a necessary portion of the mask material, and a step of ion-implanting desired impurities into the surface of the semiconductor substrate.
次に、本発明をＭＯ８型トランジスタのＳＤ領領域選択
的に拡散層を形成する方法に適用した一実施例について
詳細に説明する。Next, an embodiment in which the present invention is applied to a method of selectively forming a diffusion layer in the SD region of an MO8 type transistor will be described in detail.
第１図に本発明を適用するＭＯ８型トランジスタの断面
図を示す。半導体基板１の表面上に形成された厚さ０．
８μｍ のフィールド酸化膜２とそのフィールド酸化膜
２で囲まれた領域」二の厚さ５０〜４００Ａのゲート酸
化膜３と前記ゲート酸化膜３上に形成されたゲート電極
４から成る複数のＰ１４０Ｓ型トランジスタの８Ｄ領域
に選択的に拡散層を形成する為に、まず、第２１凶に示
す様に半導体基板１上に形成されたフィールドｆｆ１２
化膜２を含むＭＯ８型トランジスタ上全面に導電性薄膜
として厚さ１００〜５００Ａの薄いアルミニウム膜２を
蒸着、もしくけスバヴタにより形成し、その後所望する
トランジスタにのみイオン注入する為の厚さ１．５〜２
．０μｍのレジスト３を選択的に形成し、全面に例えば
、エネルギー１０〜３００に−ｅｖのボロンをイオン注
入する。この場合レジスト６、フィールド酸化膜２゜及
びゲート電極４ば、十分な厚さを持つのでボロンイオン
は、レジスト６、フィールド酸化膜２゜ゲート電極４全
通して半導体基板１まで到達せずに、レジスト６、フィ
ールド酸化膜２及びゲート電極４中にトラップｇｆＬる
が、イオンの電荷の一部は、導電性薄膜であるアルミニ
ウム膜を通して半導体基板１を支えている、クランプに
逃げる。FIG. 1 shows a cross-sectional view of an MO8 type transistor to which the present invention is applied. A layer having a thickness of 0.0 mm formed on the surface of the semiconductor substrate 1.
A plurality of P140S type devices are formed of a field oxide film 2 of 8 μm in thickness, a region surrounded by the field oxide film 2, a gate oxide film 3 with a thickness of 50 to 400 Å, and a gate electrode 4 formed on the gate oxide film 3. In order to selectively form a diffusion layer in the 8D region of the transistor, first, a field ff12 is formed on the semiconductor substrate 1 as shown in the 21st column.
A thin aluminum film 2 with a thickness of 100 to 500 Å is deposited as a conductive thin film on the entire surface of the MO8 type transistor including the oxidized film 2, and then formed by evaporation, and then deposited to a thickness of 1.0 mm to implant ions only into desired transistors. 5-2
．． A resist 3 with a thickness of 0 μm is selectively formed, and boron ions with an energy of 10 to 300, for example, −ev are implanted over the entire surface. In this case, the resist 6, field oxide film 2, and gate electrode 4 have sufficient thickness, so boron ions do not pass through the resist 6, field oxide film 2, and gate electrode 4 all the way to the semiconductor substrate 1. Although the ion charges are trapped in the resist 6, the field oxide film 2, and the gate electrode 4, some of the ion charges escape to the clamp supporting the semiconductor substrate 1 through the aluminum film, which is a conductive thin film.
更に、アルミニウム膜５は電界シールド効果を持つので
、たとえレジスト６中に電荷が蓄積しても半導体基板１
との間で放電が起きることはなく、ゲート酸化膜３が破
壊されるおそれは無い。Furthermore, since the aluminum film 5 has an electric field shielding effect, even if charges accumulate in the resist 6, the semiconductor substrate 1
There is no possibility that a discharge will occur between the gate oxide film 3 and the gate oxide film 3.
また、ゲート酸化膜３上のアルミニウム膜５は十分に薄
いので、ボロ／イオンはＭＯＳ）ランシストのＳＤ領領
域注入さ扛る。イオン注入により８Ｄ領域の拡散層形成
後、レジスト６を剥離し、アルミニウム膜５をリン酸で
エツチング除去することによって、第３図の様にＭＯ８
型トランジスタの８Ｄ領域に選択的に拡散層７を形成す
ることができる。Furthermore, since the aluminum film 5 on the gate oxide film 3 is sufficiently thin, boron/ions are implanted into the SD region of the MOS transistor. After forming a diffusion layer in the 8D region by ion implantation, the resist 6 is peeled off and the aluminum film 5 is etched away with phosphoric acid to form an MO8 as shown in FIG.
The diffusion layer 7 can be selectively formed in the 8D region of the type transistor.
他の実施例はＭＯ８型トランジスタのＳＤ領領域選択的
に拡散層を形成する方法に適用したものである。本発明
全適用するＭＯ８型トランジスタの断面図は、実施例１
と同様第１図に示す。第４図は本発明の実施例２の断面
図である。第４図に示す様に半導体基板１上に形成され
たフィールド酸化膜２を含むＭＯ８型トランジスタ全面
に、リン？含むシリコン膜８をコーティング形成し、更
に実施例１と同様レジス）６ｆＣ選択的に形成後全面に
イオン注入することにより、所望するＳＤ領領域拡散層
を形成する。その後、レジスト６を剥離し、更に電気炉
で高温熱処理することにより、第５図に示す様にリンを
含むシリコン膜８は、半導体基板１上に形成されたフィ
ールド領域２．ゲート酸化膜３、及びゲート開極４をカ
バーする安定した絶縁膜９として残す。即ちこの実施例
２では、導電性薄膜であるリン？含むシリコン膜８をイ
オン注入後に熱処理して絶縁膜９と１−で使用するので
安定したゲート酸化膜３と絶縁膜８とを持つＭＯ８型ト
ランジスタのＳＤ領領域拡散層７を選択的に形成でき、
１だ、半導体装置の工程を大幅（（短縮することができ
る。Another embodiment is applied to a method of selectively forming a diffusion layer in the SD region of an MO8 type transistor. A cross-sectional view of an MO8 type transistor to which the present invention is fully applied is Example 1.
Similarly, it is shown in FIG. FIG. 4 is a sectional view of Embodiment 2 of the present invention. As shown in FIG. 4, phosphorus is applied over the entire surface of the MO8 type transistor including the field oxide film 2 formed on the semiconductor substrate 1. A desired SD region diffusion layer is formed by coating a silicon film 8 containing silicon, selectively forming a resist (6fC) as in Example 1, and then implanting ions over the entire surface. Thereafter, the resist 6 is peeled off and further heat-treated at a high temperature in an electric furnace, so that the silicon film 8 containing phosphorus is removed from the field area 2 formed on the semiconductor substrate 1, as shown in FIG. A stable insulating film 9 covering the gate oxide film 3 and the gate opening 4 is left. That is, in this Example 2, phosphorus, which is a conductive thin film, is used. Since the silicon film 8 containing the silicon film 8 is heat-treated after ion implantation and used as the insulating films 9 and 1-, the SD region diffusion layer 7 of the MO8 type transistor having a stable gate oxide film 3 and the insulating film 8 can be selectively formed. ,
1. The semiconductor device process can be significantly shortened.
以上説明したように、本発明は不純物をイオン注入する
際に、マスクパターンと半導体基板の間に形成された導
電性薄膜で゛電界をシールドすることができる。したが
って、半導体基板に導電性薄膜を形成せずにマスクパタ
ーン全形成する従来の方法と異なり、マスクパターンと
基板との間で放電が起り、薄い酸化膜等を破壊すること
無くイオン注入できる。As described above, the present invention can shield an electric field with a conductive thin film formed between a mask pattern and a semiconductor substrate when impurity ions are implanted. Therefore, unlike the conventional method in which a mask pattern is entirely formed without forming a conductive thin film on a semiconductor substrate, a discharge occurs between the mask pattern and the substrate, and ions can be implanted without destroying a thin oxide film or the like.
第１図から第５図は本発明の実施例を工程順に示す断面
図である。
１・・・・・・半導体基板、２・・・・・・フィールド
酸化膜、３・・・・・・ゲート酸化膜、４・・・・・・
ゲート電極、５・・・・・・アルミニウム膜、６・・・
・・・レジスト、７・・・・・・拡散層、８・・・・・
・シリコン膜、９・・・・・・絶縁膜。
７一FIGS. 1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of steps. 1...Semiconductor substrate, 2...Field oxide film, 3...Gate oxide film, 4...
Gate electrode, 5... Aluminum film, 6...
...Resist, 7... Diffusion layer, 8...
・Silicon film, 9...Insulating film. 71
Claims (1)
導電性薄膜上全面にイオン注入時のイオンをマスキング
するマスク材料を形成する工程と、前記マスク材料を必
要な部分を残して除去する工程と、所望する不純物を前
記半導体基板表面にイオン注入する工程を含むことを特
徴とする半導体装置の製造方法。A step of forming a conductive thin film over the entire surface of the semiconductor substrate, a step of forming a mask material for masking ions during ion implantation over the entire surface of the conductive thin film, and a step of removing the mask material leaving only necessary portions. and a step of ion-implanting desired impurities into the surface of the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19454486A JPS6350015A (en) | 1986-08-19 | 1986-08-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19454486A JPS6350015A (en) | 1986-08-19 | 1986-08-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6350015A true JPS6350015A (en) | 1988-03-02 |
Family
ID=16326295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19454486A Pending JPS6350015A (en) | 1986-08-19 | 1986-08-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6350015A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02246323A (en) * | 1989-03-20 | 1990-10-02 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1986
- 1986-08-19 JP JP19454486A patent/JPS6350015A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02246323A (en) * | 1989-03-20 | 1990-10-02 | Fujitsu Ltd | Manufacture of semiconductor device |
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