JPS57196543A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57196543A
JPS57196543A JP8035481A JP8035481A JPS57196543A JP S57196543 A JPS57196543 A JP S57196543A JP 8035481 A JP8035481 A JP 8035481A JP 8035481 A JP8035481 A JP 8035481A JP S57196543 A JPS57196543 A JP S57196543A
Authority
JP
Japan
Prior art keywords
sio2 layer
layers
cvd method
etching
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8035481A
Other languages
Japanese (ja)
Inventor
Riyouichi Hazuki
Takahiko Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8035481A priority Critical patent/JPS57196543A/en
Publication of JPS57196543A publication Critical patent/JPS57196543A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Abstract

PURPOSE:To form an element isolation region in a semiconductor device without high temperature treatment by a method wherein after patterning is performed on the first silicon oxide film containing impurities being deposited by the CVD method, the second silicon oxide film containing no impurity is depasited thereon, and the etching treatment is performed using a solution containing hydrofluoric acid. CONSTITUTION:The SiO2 layer 2 added with phosphorus is formed on a semiconductor substrate 1 by the plasma CVD method, and after patterning is performed, ion implanted layers 3 for prevention of inversion are formed. Then the SiO2 layer 4 containing no impurity is formed by the plasma CVD method, and when etching is performed, because the etching speed from the corner of the concave part of the SiO2 layer 4 toward the diagonal direction is fast, and moreover the etching speed at the SiO2 layer containing impurities is fast, the first SiO2 layer 2 is selectively removed to leave the SiO2 layers 4 to constitute field insulating layers. Accordingly generation of bird beaks and redistribution of the inversion preventive layers can be prevented without the high temperature treatment.
JP8035481A 1981-05-27 1981-05-27 Manufacture of semiconductor device Pending JPS57196543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8035481A JPS57196543A (en) 1981-05-27 1981-05-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8035481A JPS57196543A (en) 1981-05-27 1981-05-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57196543A true JPS57196543A (en) 1982-12-02

Family

ID=13715913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8035481A Pending JPS57196543A (en) 1981-05-27 1981-05-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57196543A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5378650A (en) * 1990-10-12 1995-01-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a manufacturing method thereof
WO2000075981A1 (en) * 1999-06-03 2000-12-14 Asahi Kasei Microsystems Co., Ltd. Method for manufacturing semiconductor device
US6414352B2 (en) 1997-09-11 2002-07-02 Nec Corporation Semiconductor device having an electronically insulating layer including a nitride layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5378650A (en) * 1990-10-12 1995-01-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a manufacturing method thereof
US6414352B2 (en) 1997-09-11 2002-07-02 Nec Corporation Semiconductor device having an electronically insulating layer including a nitride layer
WO2000075981A1 (en) * 1999-06-03 2000-12-14 Asahi Kasei Microsystems Co., Ltd. Method for manufacturing semiconductor device
US6387741B1 (en) 1999-06-03 2002-05-14 Asahi Kasei Microsystems Co., Ltd. Manufacturing a semiconductor device with isolated circuit-element formation layers of different thicknesses

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