KR930006137B1 - Isolation method of semiconductor device - Google Patents

Isolation method of semiconductor device Download PDF

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KR930006137B1
KR930006137B1 KR1019900012329A KR900012329A KR930006137B1 KR 930006137 B1 KR930006137 B1 KR 930006137B1 KR 1019900012329 A KR1019900012329 A KR 1019900012329A KR 900012329 A KR900012329 A KR 900012329A KR 930006137 B1 KR930006137 B1 KR 930006137B1
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oxide film
film
field
substrate
nitride film
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KR920005355A (en
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이창재
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

The device-isolating method of a semiconductor device is characterized by (a) forming a pad oxide film (2) and a nitride film (3) on the silicon substrate (1), (b) etching the film (2,3) and the substrate (1) by the reactive ion etching method, (c) etching them with a mixed soln. of HF and HNO3, (d) implanting a channel stop ion into the field region, (e) depositing a polysilicon (4), and then oxidizing it to form a field oxide film (5), and (f) partially lifting off the film (5), and then lifting off the film (3). The method is useful for a high integrated MOS IC and a memory device.

Description

반도체소자의 소자격리방법Device isolation method of semiconductor device

제1도는 종래의 공정단면도.1 is a conventional cross-sectional view of the process.

제2도는 본발명의 공정단면도.2 is a process cross-sectional view of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2 : 패드산화막1: silicon substrate 2: pad oxide film

3 : 실리콘질화막 4 : 다결정실리콘3: silicon nitride film 4: polycrystalline silicon

5 : 필드산화막5: field oxide film

본 발명은 반도체소자의 소자격리방법에 관한 것으로, 특히 고집적 MOS IC 및 기억소자에 적합하도록 한 소자격리방법에 관한 것이다. 종래에는 일반적으로 소자간의 결리를 위한 방법으로서 실리콘질화막을 필드산화시 마스크로 이용하는 부분산화방법인 LOCOS 공정기술이 사용되었다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a device isolation method for a semiconductor device, and more particularly to a device isolation method suitable for a highly integrated MOS IC and a storage device. Conventionally, LOCOS process technology, which is a partial oxidation method using a silicon nitride film as a mask for field oxidation, has been generally used as a method for isolation between devices.

이를 첨부된 제1a 내지 d도를 참조하여 상술하면 다음과 같다.This will be described below with reference to the attached drawings 1a to d as follows.

먼저 (a)와 같이 실리콘기판(6)위에 패드산화막(7) 및 질화막(8)을 차례로 증착하고, (b)와 같이 P.R(9)을 이용하여 액티브 영역을 한정한 다음 에치한 후 채널스톱이온(I/I)을 주입한다.First, as shown in (a), the pad oxide film 7 and the nitride film 8 are sequentially deposited on the silicon substrate 6, and as shown in (b), the active area is defined using PR (9) and then etched, followed by channel stop. Ion I / I is implanted.

이어(c)와 같이 P.R(9)을 제거한 후 필드산화시켜 LOCOS 산화막(10)을 형성한 후(d)와 같이 남은 질화막(8)을 제거하므로써 공정이 완료된다.Subsequently, the process is completed by removing the P.R (9) as shown in (c) followed by field oxidation to form the LOCOS oxide film 10 and removing the remaining nitride film 8 as shown in (d).

그러나 상기 종래의 LOCOS 공정은 다음과 같은 문제점이 있었다.However, the conventional LOCOS process has the following problems.

첫째, 제2d도와 같이 버즈 비크(Bird's Beak)에 의해 소자의 액티브영역이 감소되므로 소자를 고집적화시키는데 부적합하다.First, as shown in FIG. 2D, the active area of the device is reduced by Bird's Beak, which is not suitable for high integration of the device.

둘째, 버즈 비크 주변의 잔류응력에 의해 실리콘 기판(6)에 결정결함이 발생될 수 있다.Second, crystal defects may occur in the silicon substrate 6 due to residual stress around the buzz beak.

셋째, LOCOS 산화막 형성시 채널스톱 도우펀트(Dopant)의 재분포에 따른 액티브 영역으로의 도우펀트침해(Encroachment)가 발생될 수 있다.Third, when the LOCOS oxide layer is formed, dopant encroachment into the active region may occur due to the redistribution of the channel stop dopant.

넷째, 채널스톱 이온주입이 B+도핑(Doping)일 경우 필드산화막인 LOCOS 산화막(10)내로의 도우펀트 디프리션(Depletion) 으로 인해 표면농도가 저하될 수 있다.Fourth, when the channel stop ion implantation is B + doping, the surface concentration may be reduced due to the dopant depletion into the LOCOS oxide layer 10 which is the field oxide layer.

본 발명은 상기 문제점들은 제거키 위한 방법을 제공하는데 그 목적이 있는 것으로, 이를 달성하기 위한 수단으로서 본 발명은 기판에 패드산화막과 질화막을 차례로 형성하는 공정과, P.R을 이용하여 채널스톱 영역을 한정한 후 이 영역내의 상기 질화막과 함께 필드산화막의 두께만큼 기판을 에치하는 공정, 폴리실리콘을 증착한 후 산화시켜 필드산화막을 형성하는 공정을 순차적으로 포함한다.The present invention has a purpose to provide a method for eliminating the above problems, the present invention as a means to achieve the present invention is a step of forming a pad oxide film and a nitride film on the substrate in turn, and using a PR to define a channel stop region And then etching the substrate with the nitride film in this region by the thickness of the field oxide film, and depositing and then oxidizing polysilicon to form the field oxide film.

이를 일실시예인 첨부된 제2a 내지 f도를 참조하여 상술하면 다음과 같다.This will be described below with reference to the accompanying drawings 2a to f as an embodiment.

먼저(a)와 같이 실리콘기판(1)위에 질화막(3)과 실리콘기판(1)사이에서 발생하는 스트레스를 줄이기 위한 얇은 패드 산화막(2)을 열적산화방법으로 형성하고 이어 실리콘질화막(3)을 화학증착법으로 형성한다.First, as shown in (a), a thin pad oxide film 2 is formed on the silicon substrate 1 by a thermal oxidation method to reduce stress generated between the nitride film 3 and the silicon substrate 1, and then the silicon nitride film 3 is formed. It is formed by chemical vapor deposition.

이어(b)와같이 포토리토그래피 공정을 실시하여 소자의 액티브영역과 필드영역을 구분한후 RIE(Reactive Ion Etching)법으로 상기 패드산화막(2) 및 질화막(3)과 함께 실리콘기판(1)을 필드산화막 두께(T)의 1/2 정도로 에칭하고 이어(c)와 같이 불산(HF)과 질산 (HNO3)의 혼합용액으로 된 실리콘 에쳔트(Etchant)를 이용하여 초음파베쓰(Bath)에서 습식 에치한다. 이때 필드산화막의 나머지 두께를 에치하게 된다.Subsequently, a photolithography process is performed to separate the active and field regions of the device, and then the silicon substrate 1 together with the pad oxide film 2 and the nitride film 3 by RIE (Reactive Ion Etching). Is etched at about 1/2 of the thickness of the field oxide film (T), and then in an ultrasonic bath using a silicon etchant consisting of a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO 3 ) as shown in (c). Wet etch. The remaining thickness of the field oxide film is etched at this time.

다음으로 채널스톱을 위한 이온주입(N형 필드일 경우는 붕소, P형 필드일 경우는 인 이온)(I/I)을 실시한다.Next, ion implantation (boron in the N-type field, phosphorus ion in the P-type field) (I / I) is performed for channel stop.

그리고 (d)와 같이 P.R을 제거하고 도우프되지 않은 다결정 실리콘(4)을 이후 진행되는 산화시의 볼륨팽창을 감안하여 에치된 필드의 깊이보다 약간 적은 두께로 화학증착법을 이용하여 증착한다.Then, as in (d), the P.R is removed and the undoped polycrystalline silicon 4 is deposited by chemical vapor deposition to a thickness slightly smaller than the depth of the etched field in consideration of the volume expansion during the subsequent oxidation.

이어 (e)와 같이 상기 증착된 다결정 실리콘(4)이 충분히 산화될 수 있도록 습식산화를 행한다음 (f)와 같이 건식에치법으로 실리콘질화막(3)의 노출될 때까지 표면의 다결정실리콘(4)에 의해 형성된 필드산화막(5) 일부를 제거한 후 질화막(3)을 제거하면 공정이 완료된다.Subsequently, wet oxidation is performed so that the deposited polycrystalline silicon 4 is sufficiently oxidized as shown in (e), and then polysilicon 4 on the surface is exposed until the silicon nitride film 3 is exposed by dry etching as shown in (f). The process is completed by removing the nitride film 3 after removing a part of the field oxide film 5 formed by the < RTI ID = 0.0 >

이상과 같이 본 발명에 의하면 종래의 LOCOS 공정과 같이 버즈비크가 발생하지 않게 되므로 소자의 액티브영역을 극대화시킬 수 있는 효과가 있다.As described above, according to the present invention, as the conventional LOCOS process does not generate a buzz beak, the active area of the device can be maximized.

또한 버즈비크 주변에서 발생하는 실리콘의 결정결함을 막을 수 있으므로 격리특성이 향상된다.In addition, it is possible to prevent the crystal defects of silicon generated around the Burj beak to improve the isolation characteristics.

또한 기존의 LOCOS 필드산화막 형성시 발생되는 도우펀트 재배열에 따른 도우펀트 침해가 발생되지 않는다.In addition, the dopant infringement due to the dopant rearrangement generated when the existing LOCOS field oxide film is formed does not occur.

또한, 필드산화막내로의 두우펀트 파일-업에 따라 실리콘기판 (1) 표면의 도우펀트 디프리션이 발생되지 않는다.Further, dopant dispersion of the surface of the silicon substrate 1 does not occur due to the dopant pile-up into the field oxide film.

Claims (3)

기판(1)에 패드산화막(2)과 질화막(3)을 차례로 형성하는 공정과, P.R을 이용하여 소장의 액티브영역과 필드영역을 구분하고 필드영역내의 상기 패드산화막(2) 및 질화막(3)과 함께 필드산화막의 두께 만큼 기판(1)을 에치하는 공정과, 필드영역에 채널스톱이온주입하는 공정과, 전면에 폴리실리콘(4)을 증착한 후 폴리실리콘(4)을 완전 산화시켜 필드산화막(5)을 형성하는 공정과, 상기 질화막(3)이 들어날 때까지 에치백하여 필드산화막(5)이 기판표면과 평탄하게 필드영역에 남도록 하는 공정을 구비하여 제조됨을 특징으로 하는 반도체 소자의 소자격리 방법.Forming a pad oxide film (2) and a nitride film (3) on the substrate (1) sequentially, and using a PR to distinguish between the small active region and the field region, and the pad oxide film (2) and the nitride film (3) in the field region. And etching the substrate 1 to the thickness of the field oxide film, implanting channel stop ions into the field region, depositing polysilicon 4 on the entire surface, and then completely oxidizing the polysilicon 4 to form the field. And a step of forming the oxide film 5 and etching the back film until the nitride film 3 enters so that the field oxide film 5 remains in the field region evenly on the surface of the substrate. Device isolation method. 제1항에 있어서, 기판의 에치는 질화막(3)을 마스크로 하여 형성하고자 하는 필드산화막의 두께의 절반만큼은 건식에치법으로 나머지 절반은 습식에치법으로 실시함을 특징으로 하는 반도체 소자의 소자격리 방법.The device isolation of a semiconductor device according to claim 1, wherein the etch of the substrate is carried out by dry etch and half by wet etch for the thickness of the field oxide film to be formed by using the nitride film 3 as a mask. Way. 제2항에 있어서, 습식에치는 불산과 질산의 혼합용액으로 된 실리콘 에천 용액을 사용하여 초음파 베쓰에서 행함을 특징으로 하는 반도체 소자의 소자격리 방법.The method of claim 2, wherein the wet etch is performed in an ultrasonic bath using a silicon etch solution composed of a mixed solution of hydrofluoric acid and nitric acid.
KR1019900012329A 1990-08-10 1990-08-10 Isolation method of semiconductor device KR930006137B1 (en)

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