KR100281036B1 - Field oxide film manufacturing method - Google Patents

Field oxide film manufacturing method Download PDF

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KR100281036B1
KR100281036B1 KR1019930004339A KR930004339A KR100281036B1 KR 100281036 B1 KR100281036 B1 KR 100281036B1 KR 1019930004339 A KR1019930004339 A KR 1019930004339A KR 930004339 A KR930004339 A KR 930004339A KR 100281036 B1 KR100281036 B1 KR 100281036B1
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oxide film
film
pattern
forming
nitride film
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KR1019930004339A
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KR940022789A (en
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하덕용
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김영환
현대반도체주식회사
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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 필드산화막 형성 방법에 관한것으로, 필드산화막 패턴 형성시 패턴막을 산화막, 질화막, 산화막으로 된 3층막으로 형성시켜 질화막을 두 스텝으로 에칭하여 계단형의 패턴을 형성시켜 필드산화막 형성시 버드빅이 형성되는 부위의 절연막을 얇게 형성시킴으로서 이부분에서 버드빅의 형성을 억제하고 전위결함의 발생을 줄일 수 있다.The present invention relates to a method of forming a field oxide film, wherein when forming a field oxide film pattern, the pattern film is formed into a three-layer film consisting of an oxide film, a nitride film, and an oxide film, and the nitride film is etched in two steps to form a stepped pattern, thereby forming Budvik. By forming a thin film of the insulating film at the portion to be formed, it is possible to suppress the formation of Budvik at this portion and to reduce the occurrence of dislocation defects.

Description

필드산화막 제조방법Field oxide film manufacturing method

제1도 (a)내지(f)는 종래의 필드산화막 제조공정 단면도.1 (a) to (f) are cross-sectional views of a conventional field oxide film production process.

제2도 (a)내지(h)는 본 발명의 필드산화막 제조공정 단면도.Figure 2 (a) to (h) is a cross-sectional view of the field oxide film production process of the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 반도체기판 2 : 제 1 절연막1 semiconductor substrate 2 first insulating film

3 : 제 2 절연막 3a,3b : 1,2차 제 3 절연막3: second insulating film 3a, 3b: primary and secondary third insulating film

4 : 제 3 절연막 4a : 제 3 절연막패턴4: third insulating film 4a: third insulating film pattern

6 : 감광막패턴 7 : 필드산화막6: photosensitive film pattern 7: field oxide film

8 : 채털스톱층8: Chat stop layer

본 발명은 반도체 셀의 격리 방법에 관한것으로, 특히 버드 빅(Birds Beak) 길이를 줄이기에 적당하도록 한 필드산화막 제조방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for isolating semiconductor cells, and more particularly, to a method of manufacturing a field oxide film suitable for reducing the length of Birds Beak.

제 1 도는 종래의 필드산화막 형성 방법을 설명하기 위한 공정 단면도로서, 이로부터 종래의 기술을 설명하면 다음과 같다.1 is a cross-sectional view for explaining a conventional method for forming a field oxide film, which will be described below.

제 1 도 (a)와 같이 반도체기판(P형 또는 N형)(1)의 택 영역에 N형 또는 P형 반도체층(N-웰 또는 P-웰)을 형성하고 전표면에 제 1 절연막(산화막)(2)을 형성한 후 (b)와 같이 제 2 절연막(질화막)(3)을 형성한다.As shown in FIG. 1A, an N-type or P-type semiconductor layer (N-well or P-well) is formed in the tack region of the semiconductor substrate (P-type or N-type) 1, and the first insulating film ( After the oxide film 2 is formed, a second insulating film (nitride film) 3 is formed as shown in (b).

그 다음, (c)와 같이 제 2 절연막(3)상에 감광막(5)을 도포하고 소자가 격리된 영역의 상측의 감광막(6)의 일정폭을 제거하여 패턴을 형성한 후 노출된 제 2 절연막(3)을 건식 식각하고 잔존하는 감광막(5)을 O2플라즈마(Plasma)를 이용하여 제거한다.Next, as shown in (c), the photosensitive film 5 is coated on the second insulating film 3, and a predetermined width of the photosensitive film 6 on the upper side of the region where the device is isolated is removed to form a pattern, and then the exposed second second film is exposed. The insulating film 3 is dry-etched and the remaining photosensitive film 5 is removed using an O 2 plasma.

그 다음, (d)와 같이 셀과 셀 사이를 격리하기 위해 제 2 절연막(3a) 패턴형성시 노출된 영역 하단의 반도체기판(1)에 고농도의 보론(B)이온을 주입하여 P+영역을 형성한다.Then, a second insulating film (3a) a high concentration of boron (B) ion implantation with P + region in the semiconductor substrate 1 at the bottom of the exposed areas in the pattern formation to isolate the base cell to the cell as shown in (d) Form.

그 다음, (e)와 같이 제 2 절연막(3a) 패턴형성시 노출된 영역 하단의 반도체기판(1)을 열산화시켜 이 영역에 필드산화막(7)을 형성시키고 필드산화막(7) 하단에 채널스톱층(8)을 형성한다.Then, as shown in (e), the semiconductor substrate 1 at the bottom of the exposed region is thermally oxidized to form the field oxide film 7 in the region formed during the patterning of the second insulating film 3a, and the channel at the bottom of the field oxide film 7 is formed. The stop layer 8 is formed.

다음 (f)와 같이 필드산화막(7) 성장시 제 2 절연막(3) 패턴 상측에 생긴 산화막을 불산(HF)으로 제거한 후 남아있는 제 2 절연막(3a) 패턴을 인산(H3PO4)으로 제거하여 셀과 셀 영역을 분리시킨다.As shown in (f), after removing the oxide film formed on the upper surface of the second insulating film 3 pattern with hydrofluoric acid (HF), the remaining second insulating film 3a pattern is replaced with phosphoric acid (H 3 PO 4 ). To separate the cell from the cell area.

이와같은 종래의 셀 격리 기술에서 버드 빅(Birds Beak)의 길이를 줄여 활성영역을 충분히 확보하기 위해서 스트레스 완화용 산화막(완충 또는 패드산화막)의 두께를 줄임으로써, 필드산화막 성장시 질화막과 산화막의 열팽창이 달라 질화막이 식각된 계면에서 반도체 기판쪽으로 전위 결함(Dislocation Defect)이 생겨 누설전류가 발생하므로써 셀과 셀이 격리가 불안정하여 소자 특성을 저하시키는등 문제가 있다.In the conventional cell isolation technology, the thickness of the stress relaxation oxide (buffer or pad oxide) is reduced to reduce the length of Birds Beak to sufficiently secure the active area, thereby thermally expanding the nitride and oxide films during field oxide growth. Dislocation defects are generated from the interface where the nitride film is etched to the semiconductor substrate, and a leakage current is generated, resulting in unstable cell and cell isolation, thereby degrading device characteristics.

본 발명은 이와같은 종래 기술의 문제점을 해결하기 위해 제안된것으로, 필드산화막 형성시 버드 빅(Birds Beak)이 형성되는 부위의 질화막 두께를 얇게 형성시켜 전위결함(Dislocation defect)을 줄이고 버드빅의 성장을 줄이는데 목적이 있다.The present invention has been proposed to solve the problems of the prior art, by forming a thin nitride film thickness of the site where the bird beak is formed when forming the field oxide film to reduce dislocation defects and to grow Budvik The purpose is to reduce.

상기와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.DETAILED DESCRIPTION Embodiments of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

제 2 도는 본 기술의 공정 단면도로서, (a)와 같이 반도체기판(P형또는N형)(1)의 선택 영역에 N형 또는 P형 반도체층(N-웰 또는 P-웰)을 형성하고, 상기 반도체기판(1)상에 제 1 절연막(산화막)(2)을 형성한 후 (b)와 같이 제 2 절연막(질화막 1000-1500Å)(3)과 제 3 절연막(CVD산화막 500-1000Å)(4)을 차례로 형성한다.2 is a cross sectional view of the present technology, in which an N-type or P-type semiconductor layer (N-well or P-well) is formed in a selected region of the semiconductor substrate (P-type or N-type) 1 as shown in (a). After forming the first insulating film (oxide film) 2 on the semiconductor substrate 1, the second insulating film (nitride film 1000-1500 kV) 3 and the third insulating film (CVD oxide film 500-1000 kPa) as shown in (b). (4) are formed in sequence.

이어, (c)와 같이 제 3 절연막(4)상에 감광막을 도포하고 감광막의 선택영역을 제거하며 제 3 절연막(4)의 선택영역이 노출되도록 감광막패턴(G)을 형성한다.Subsequently, as shown in (c), a photosensitive film is coated on the third insulating film 4, the selection area of the photoresist film is removed, and the photosensitive film pattern G is formed to expose the selection area of the third insulating film 4.

다음, 노출된 제 3 절연막(4)과 하단의 제 2 절연막(3)을 건식 식각하여 식각되고 남은 부분의 두께가 500-750Å의 두께를 갖는 1차 패턴된 제 2 절연막 패턴(3a)을 형성한다.Next, the exposed third insulating film 4 and the lower second insulating film 3 are dry etched to form a first patterned second insulating film pattern 3a having a thickness of 500 to 750 되고 after etching. do.

이어, 상기 감광막패턴(6)을 제거하고 (d)와 같이 제 3 절연막(4)상에 감광막패턴을 제 3 절연막의 식각부분으로 부터 양측으로 1000Å쪽이 노출되도록 형성한 후, 노출된 부분의 제 3 절연막(4)을 제거하여 제 3 절연막 패턴(4a)을 형성한다.Subsequently, the photoresist pattern 6 is removed, and the photoresist pattern is formed on the third insulating film 4 such that the photoresist pattern is exposed on both sides of the third insulating film from the etching portion of the third insulating film as shown in (d). The third insulating film 4 is removed to form the third insulating film pattern 4a.

그 다음, (e)와 같이 제 3 절연막패턴(4a)상에 남아있는 감광막을 산소(O2) 플라즈마를 이용하여 제거한 후 제 2 절연막 패턴(3a)의 노출부위를 건식식각하여 계단형의 제 2 절연막패턴(3b)을 형성하고 격리영역 형성을 위해 노출된 부위에 고농도의 보론(B)을 주입하여 반도체기판(1)에 P+영역을 형성한다.Next, as shown in (e), the photoresist film remaining on the third insulation film pattern 4a is removed using oxygen (O 2 ) plasma, and then the exposed portions of the second insulation film pattern 3a are dry etched to form a stepped film. 2 An insulating layer pattern 3b is formed and a high concentration of boron B is injected into the exposed portion to form the isolation region, thereby forming a P + region in the semiconductor substrate 1.

이어 (g)와 같이 노출된 영역하단 반도체기판(1)을 염산화시켜 필드산화막(7)을 형성한다.Subsequently, as shown in (g), the semiconductor substrate 1 at the lower portion of the exposed region is oxidized to form a field oxide film 7.

이때 필드산화막(7) 하단에 채널스톱층(8)이 형성되어 셀과 셀을 격리하게된다. 다음 (h)와 같이 잔존하는 2차 제 3 절연막패턴(4b)과 제 2 절연막 패턴(3a)을 불산(HF)과 가열된 인산(H3PO4)으로 제거한다.At this time, a channel stop layer 8 is formed at the bottom of the field oxide layer 7 to isolate the cell from the cell. Next, as shown in (h), the remaining third insulating film pattern 4b and the second insulating film pattern 3a are removed with hydrofluoric acid (HF) and heated phosphoric acid (H 3 PO 4 ).

이와같은 본 발명은 종래의 기술에서 두꺼운 질화막이 버드빅이 형성될 계면에 존재하는 상태에서 필드산화막 형성시 발생되는 전위 결함(Dislocation Defect)을 얇은 질화막이 완화시켜 줌으로써 전위결함에 의한 누설현상을 방지하여 소자 특성을 향상시킬 수 있고 얇은 질화막이 버드 빅(Birds Beak)성장을 억제시킴으로서 필드산화막을 작은 크기로 형성할 수 있는 효과가 있다.The present invention prevents leakage due to dislocation defects by mitigating dislocation defects generated during field oxide film formation in a state where a thick nitride film exists at an interface where Budvik is to be formed in the prior art. Therefore, the device characteristics can be improved, and the thin nitride film suppresses the growth of bird beak, thereby forming a field oxide film in a small size.

Claims (4)

반도체 기판상에 제 1 산화막, 질화막, 제 2 산화막을 차례로 형성하는 공정과, 상기 제 2 산화막의 표면으로부터 질화막의 일정깊이까지만 선택된 폭만큼을 식각하여 1차 질화막 패턴을 형성하는 공정과, 상기 1차 질화막 패턴의 상측에 잔존하는 제 2 산화막을 식각된 양측면으로부터 일정폭 만큼을 더 식각하여 제 2 산화막 패턴을 형성하는 공정과, 상기 제 2 산화막 패턴을 마스크로 하여 1차 질화막 패턴의 노출된 영역을 식각하여 제 1 산화막의 표면이 드러나도록 계단형의 2차 질화막 패턴을 형성하는 공정과, 상기 노출된 산화막의 표면에 채널스톱용 불순물 이온을 주입하고 주입된 영역에 열산화 공정을 수행하여 기판 표면내에 필드산화막과 채널스톱층을 형성하는 공정을 구비함을 특징으로 하는 필드산화막 제조방법.Forming a first oxide film, a nitride film, and a second oxide film sequentially on the semiconductor substrate; forming a primary nitride film pattern by etching a selected width only from a surface of the second oxide film to a predetermined depth of the nitride film; and 1 Etching the second oxide film remaining on the upper side of the first nitride film pattern by a predetermined width to form a second oxide film pattern, and an exposed region of the first nitride film pattern using the second oxide film pattern as a mask Forming a stepped secondary nitride film pattern so that the surface of the first oxide film is exposed by etching, implanting impurity ions for channel stop in the exposed oxide film surface, and performing a thermal oxidation process on the injected region A method for producing a field oxide film, comprising the step of forming a field oxide film and a channel stop layer in a surface thereof. 제1항에 있어서, 상기 1차 질화막 패턴의 잔존하는 막 두께는 500~750Å임을 특징으로 하는 필드산화막 제조방법.The method of claim 1, wherein the remaining film thickness of the first nitride film pattern is 500 to 750 Pa. 제1항에 있어서, 상기 제 2 산화막 패턴 형성시 1차 식각된 부위의 양측면으로부터 재 식각되는 폭은 1000Å임을 특징으로 하는 필드산화막 제조방법.The method of claim 1, wherein the width of the second etched pattern is re-etched from both sides of the first etched portion at 1000 μs. 제1항에 있어서, 상기 질화막위에 형성되는 제 2 산화막은 500~1000Å의 두께로 형성하는 것을 특징으로 하는 필드산화막 제조방법.The method of claim 1, wherein the second oxide film formed on the nitride film is formed to a thickness of 500 to 1000 GPa.
KR1019930004339A 1993-03-20 1993-03-20 Field oxide film manufacturing method KR100281036B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100898434B1 (en) * 2006-12-28 2009-05-21 동부일렉트로닉스 주식회사 Method for etching oxide in semiconductor cleaning procedure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04206825A (en) * 1990-11-30 1992-07-28 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH04271123A (en) * 1991-02-27 1992-09-28 Sanyo Electric Co Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04206825A (en) * 1990-11-30 1992-07-28 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH04271123A (en) * 1991-02-27 1992-09-28 Sanyo Electric Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100898434B1 (en) * 2006-12-28 2009-05-21 동부일렉트로닉스 주식회사 Method for etching oxide in semiconductor cleaning procedure

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