JPS59937A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an active region pattern which has almost no conversion error for a mask pattern by forming an impurity layer shallowly on a nonactive region and deeply on the active region. CONSTITUTION:Impurity ions of the same conductive type as a substrate 1 are implanted simultaneously on a nonactive region 4 covered with a thick insulating film 2 and on an active region exposed on the surface of the substrate, thereby simultaneously forming the shallow impurity layer 8 to become a channel stopper on the nonactive region 4 and a deep impurity layer for preventing a punch through between a source and a drain on the channel region 11 of an active region 6 and particularly on an MOS transistor channel region 11. In this manner, the channel stopper impurity layer can be formed in a self-aligning manner on the active region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for isolating elements in an MO8 integrated circuit.

Conventionally, a selective oxidation method in which an oxide film is provided buried in a substrate has been generally used as a device isolation method for MO8 integrated circuits.

This selective oxidation method covers the active region with an oxidation-resistant material and thickly oxidizes the silicon surface of the non-active region. Furthermore, using the oxidation-resistant material pattern as a mask, a so-called channel stopper impurity can be introduced only into the silicon substrate in the non-active region. This makes it possible to form a thick silicon oxide film in the inactive region and a channel stopper impurity layer in a self-aligned manner in the active region! 0, has greatly contributed to the high integration of MOB integrated circuits.

However, this selective oxidation method has been unable to meet the recent demands for miniaturization and higher performance of MO8 integrated circuits.The first disadvantage of this selective oxidation method is that the inactive region In the active region covered with an oxidation-resistant material, an oxidation film called a bird's beak appears, imitating the thick oxidation of silicon. Although the size of the bird's beak varies depending on the manufacturing process, it is necessary to take into account that the bird's beak penetrates into the active region by a value close to the thickness of the silicon oxide film on the non-active region, causing the active region to shrink. Especially in MOS transistors with small channel width,
Since the channel width reduction due to the bird's beak has a large effect on the characteristics of the transistor, the optimum value cannot be made smaller than twice the bird's beak amount. The second inconvenience is.

The process of thickly oxidizing the non-active region of the substrate using an oxidation-resistant material as a mask generates large stress at the boundary between the active region and the non-active region, making it easy for crystal defects such as dislocations to occur, resulting in junctions. This will not cause leaks.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an isolation structure suitable for high integration of MO8 integrated circuits, which eliminates the disadvantages of the conventional selective oxidation method.

The present invention comprises: - a step of forming a thick insulating film on a conductive semiconductor substrate; a step of forming a pattern using an etching-resistant material to cover a region that will become an inactive region in the future; and using this pattern as an etching mask. A step of etching away the thick insulating film on the active region, and implanting ions into the entire surface of the semiconductor substrate with an impurity of the same conductivity type as the substrate and at a higher concentration than the substrate with sufficient acceleration energy to penetrate the thick insulating film. The main point is to form the impurity layer shallowly in the non-active region and deeply in the active region.

Furthermore, in addition to the above-mentioned structure, the present invention particularly provides that the step of etching away the thick insulating film on the active region has an accelerated etching effect on the surface of the thick insulating film with respect to the isotropic etching method in the next step. Using the etching-resistant feather pattern as a mask, a part of the thick insulating film on the active region is etched and etched by an isotropic etching method, and then the etching-resistant feather pattern is used as a mask. The entire process consists of etching and removing the insulating film in a portion using an anisotropic process and a etching method.

According to the present invention, since the shape of the active region is determined by etching, there is no occurrence of bird's beaks caused by conventional selective oxidation methods. The miniaturization of the active region to the dimensions allowed by insulation technology and coating technology is a chemical film. If current general techniques with strong anisotropy are used, such as ⇠IE (rear) tipion etching, ching), it is possible to form active region patterns with almost no conversion errors for mask patterns. is easy.

Furthermore, by using the etching method as in the second invention, it is possible to provide an appropriate slope to the sidewalls of the thick insulating film surrounding the active region, which is effective in preventing disconnection in the upper wiring layer.

In the present invention, by simultaneously implanting highly concentrated impurity ions of the same conductivity type as the substrate into the non-active region covered with a thick insulating film and the active region exposed on the surface of the substrate, the non-active region has a so-called channel. Strike.

A shallow impurity layer that becomes a para layer is also used in the active region, especially in the MOB.
) In the channel region of the transistor, a deep impurity layer is simultaneously formed to prevent punch-through between the source and drain. As a result, the channel stopper impurity layer is formed in a self-aligned manner with the active region.

Furthermore, according to the present invention, there is no need for a process that generates large local stress, such as forming a thick thermal oxide film using an oxidation-resistant material as a mask, and the occurrence of crystal defects in the substrate is minimized. be able to.

A detailed explanation will be given below based on an unexploded 8At example.

The following embodiments will be described with reference to the case where they are applied to an N-channel type MO8 integrated circuit, but they can easily be applied to a general MO8 integrated circuit.

Thermal oxidation method J600 was applied on the P-type single crystal silicon substrate 1.
A silicon oxide film of 2 gold is grown at 0A. Of course, this may also be a deposited film formed by CVD, sputtering, or the like. Next, on the surface of the thick silicon oxide film 2, lXl0'' is applied with acceleration energy of phosphorus 15Qkev.
Ion implantation is performed at a dose of 7 cm 2 to form an ion implantation layer 3 near the surface of the silicon oxide film 2 . next,
A photoresist pattern 5 covering a region 4't- which will become an inactive region in the future is formed using conventional photoresist and masking techniques to obtain the cross-sectional shape shown in FIG. 1(a).

Next, when the silicon oxide film 2 is etched away by approximately 500 OA using an HF-based etching agent and a tinting liquid, the etching rate of the ion-implanted layer 3 is faster than that of the silicon oxide film in the non-implanted region, as shown in FIG. 1(b). As shown, gentle slope 1
You can get the shape you want.

Thereafter, the remaining 9 silicon oxide films 2 on the active region are etched and removed by RIE (reactive ion etching) using CFJ-based gas, and the shape of the active region 6 is determined to obtain FIG. 1(C). . In FIG. 1(C) obtained in this way, the upper part has a gentle taper, and the lower part has a
The sidewall 7 with almost no conversion error can be realized from the photoresist pattern.

In the non-embodiment, a phosphorus ion implantation layer 3 was applied to the surface of the silicon oxide film 2 using an HF-based process to form a taper on the sidewall 7.
It was formed as a speed-enhancing etching layer for the tinda solution, but
Depending on the required taper, it is possible to change the energy dose of ion implantation, use ion species other than phosphorus, and deposit a film with a high etching rate such as phosphorus silica glass. can achieve the same effect and can be selected appropriately according to the manufacturing schedule.

Next, the photoresist film 7 on the thick silicon oxide film 2 is removed, and the substrate 1 is removed by a dose of l
0Ion implantation into the entire surface. At this time, the inactive area 4
In this case, due to the presence of the thick silicon oxide film 2, there is a shallow boron implanted region 8 whose distribution center is approximately 200 OA deep from the substrate surface, and in the active region 5, there is a silicon oxide film that blocks implanted ions. Since there is no boron ion, a deep boron implanted region 9 is formed in which the distribution center of boron ions is located at a depth of about 800 OA from the silicon surface, resulting in the formation of FIG. 1(d). In the structure shown in FIG. 1(d), the non-active region 4
A high concentration boron region exists near the surface of the silicon substrate 1 and serves as a channel striker, resulting in a high field reversal voltage. , MOS) The increase in the threshold voltage of the transistor is not so large.

Further, the highly concentrated boron present deep in the channel region can serve as an impurity layer to prevent punch-through between the source and drain.

Next, a gate silicon oxide film 10 is grown on the silicon substrate surface of the active region 6 by a normal thermal oxidation method, and impurity ions for threshold voltage adjustment are implanted to form an impurity layer 11't-. obtain e). Here, the conditions for forming the threshold voltage adjusting impurity layer 11 are closely related to the conditions for forming the channel strike, impurity, and punch-through prevention boron regions described above, and can be arbitrarily set as necessary.

Of course, the above boron ion implantation conditions also apply to the field reversal voltage, MUD) transistor threshold voltage,
It can be changed appropriately according to the target value of the punch-through voltage.

Hereinafter, any known N-channel type MO8 type device manufacturing method can be applied to the steps up to completion of the integrated circuit device, and since they are not essential to the present invention, they will be omitted.

As described above, according to an embodiment of the present invention, it is possible to form an active region with almost no conversion error and to form a matching channel strike and spring pure layer in the active region with respect to a processing mask pattern. It was shown that a layer was formed. Furthermore, it has been shown that by determining the shape of the active region and selecting the electrical process and the coating, it is possible to provide an appropriate taper to the stepped portion of the thick silicon oxide film that occurs between the active region and the non-active region.

It is clear from the text of the examples that the above-described examples are merely for illustrative purposes and the invention is not limited thereto. That is, the contents of individual steps can be modified in any number of ways without departing from the gist of the present invention.

[Brief explanation of drawings]

FIGS. 1(a) to 1(8) are cross-sectional views illustrating a manufacturing method according to an embodiment of the present invention in the order of steps. In the figure, 1... P-type single crystal silicon substrate, 2...
・Thick silicon enhancement film, 3... speed-up etching layer, 4... inactive region, 5... photoresist film, 6... active region ,7...
Active region sidewall, 8...Shallow boron implantation region, 9
- Culm: deep boron implantation region, 10: gate silicon oxide film, 11: threshold voltage adjustment impurity layer.

Claims (2)

[Claims] (1) - A step of forming a thick insulating film on a conductive semiconductor substrate, a step of covering a region that will become a non-active region using an etching-resistant material, and a step of forming a Nil mark on an active region using the etching-resistant material as a mask. etching away the thick insulating film, and ion implanting impurities of one conductivity type into the entire surface of the semiconductor substrate with sufficient acceleration energy to completely penetrate the thick insulating film, and implanting the impurities into the substrate in the active region. 1. A method for manufacturing a semiconductor device, comprising the step of introducing the non-active region deeper into the substrate. (2) The step of removing the thick insulating film on the active region by etching and etching particularly forms a surface layer on the surface of the thick insulating film that has a speed-up and etching effect for the isotropic etching method in the next step. Using an etching-resistant material as a mask, a portion of the thick insulating film over the active region is etched using an isotropic etching method. and then etching away the remainder of the thick insulating film on the active region using an anisotropic etching method. A method for manufacturing a semiconductor device according to item (1).