JPS6235554A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS6235554A
JPS6235554A JP17676885A JP17676885A JPS6235554A JP S6235554 A JPS6235554 A JP S6235554A JP 17676885 A JP17676885 A JP 17676885A JP 17676885 A JP17676885 A JP 17676885A JP S6235554 A JPS6235554 A JP S6235554A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
polysilicon
polysilicon film
high resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17676885A
Other languages
Japanese (ja)
Inventor
Toru Ueda
徹 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP17676885A priority Critical patent/JPS6235554A/en
Publication of JPS6235554A publication Critical patent/JPS6235554A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the size and to increase the density of a semiconductor device by reducing the thickness of a polysilicon film of a high resistor as compared with that of a polysilicon film of a low resistor. CONSTITUTION:After an active region 12 is formed on a semiconductor substrate 11, a polysilicon film 14 is accumulated on the entire surface through an insulating film 13, and patterned. After a thin polysilicon oxide film 15 is formed by thermal oxidation, a nitride film 16 is accumulated, and patterned by a dry etching method. With the film 16 as an oxide mask a locos oxide film D is formed. After the film 16 is separated, with the film D as a mask of implanting ions high density ions are implanted to low resistors E, G. After an insulating film 17 is accumulated, it is treated at high temperature to form low resistors E', G'. Then, a contacting hole is opened, aluminum wiring electrode 18 is formed to complete a semiconductor device. The resistance value can be increased in order as compared with that at initial film thickness (d), and L' can be reduced.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、高抵抗部(抵抗素子部分)と低抵抗部(接続
配線部分)とを含むポリシリコン膜を有する半導体装置
、及びその製造方法に関するものである。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor device having a polysilicon film including a high resistance part (resistance element part) and a low resistance part (connection wiring part), and a method for manufacturing the same. It is related to.

〈従来の技術〉 近年のLSIの集積化に伴なって、例えば、スタチック
型のメモリ素子等では、セル内の負荷素子に半導体素子
を用いるようになってきている。
<Prior Art> With the recent integration of LSIs, semiconductor elements have been used as load elements in cells, for example, in static type memory elements.

プロセスの簡易さからポリシリコンにより抵抗素子を形
成するのが盛んである。
Resistance elements are often formed from polysilicon because of the simplicity of the process.

第2図に従来の半導体装置の構造及びその製造工程の一
例を示す。
FIG. 2 shows an example of the structure of a conventional semiconductor device and its manufacturing process.

半導体基板1に活性領域2を形成した後、絶縁膜3を介
して全面にポリシリコン膜4を形成する。
After forming an active region 2 on a semiconductor substrate 1, a polysilicon film 4 is formed on the entire surface with an insulating film 3 interposed therebetween.

ポリシリコン膜4をバターニング後、レジスト5をマス
クにして、As あるいはPを高濃度イオン注入し、低
抵抗部(接続配線部分)A、Cを形成する。BXは高抵
抗部である。レジスト5を除去し、絶縁膜6を形成した
後、イオン注入した不純物の活性化の為の熱処理を施し
、低抵抗部A’ 、 C’を形成する。コンタクトホー
ルを開けた後、アルミ配線電極7を設け、半導体装置を
完成する。イオン注入した不純物の活性化の為の熱処理
時に、不純物の横方向拡散により高抵抗部(抵抗素子部
分)B′の長さはLからL′に縮小される。高抵抗値は
L′により決定される。
After patterning the polysilicon film 4, high concentration As or P ions are implanted using the resist 5 as a mask to form low resistance parts (connection wiring parts) A and C. BX is a high resistance section. After removing the resist 5 and forming an insulating film 6, heat treatment is performed to activate the ion-implanted impurities to form low resistance parts A' and C'. After opening the contact holes, aluminum wiring electrodes 7 are provided to complete the semiconductor device. During heat treatment for activating the ion-implanted impurities, the length of the high resistance portion (resistance element portion) B' is reduced from L to L' due to lateral diffusion of the impurities. The high resistance value is determined by L'.

〈発明が解決しようとする問題点〉 しかしながら、上記従来の半導体装置は、その高い抵抗
値の制御ということで、高抵抗部の素子寸法が大きくな
るという問題点を有していた。
<Problems to be Solved by the Invention> However, the conventional semiconductor device described above has a problem in that the element size of the high resistance portion becomes large due to the control of the high resistance value.

本発明は上記の点に鑑みてなされたものであり、高抵抗
部の素子寸法が非常に小さい半導体装置及びその製造方
法を提供することを目的としているものである。
The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device in which the element size of the high resistance portion is extremely small, and a method for manufacturing the same.

く問題点を解決するだめの手段〉 高抵抗部のポリシリコン膜厚を低抵抗部のポリシリコン
膜厚より薄くする。選択酸化法によってポリシリコン膜
を部分的に薄くすることにより上記高抵抗部を形成する
The only way to solve the problem is to make the polysilicon film thickness of the high resistance part thinner than the polysilicon film thickness of the low resistance part. The high resistance portion is formed by partially thinning the polysilicon film by selective oxidation.

〈実施例〉 第1図に、本発明に係る半導体装置の構造及びその製造
工程を示す。
<Example> FIG. 1 shows the structure of a semiconductor device and its manufacturing process according to the present invention.

(1)半導体基板11に活性領域12を形成した後、絶
縁膜13を介して全面にポリシリコン膜14を3000
A堆積し、パターニングを施す。
(1) After forming the active region 12 on the semiconductor substrate 11, a polysilicon film 14 is formed on the entire surface with a film thickness of 3000 nm with an insulating film 13 interposed therebetween.
A is deposited and patterned.

(2)熱酸化により薄いポリシリコン酸化膜15を形成
した後、CVD法で窒化膜(Si3N4)16を堆積し
、ドライエツチング法でパターニングする。
(2) After forming a thin polysilicon oxide film 15 by thermal oxidation, a nitride film (Si3N4) 16 is deposited by CVD and patterned by dry etching.

(3)窒化膜16を酸化マスクとしてロコス酸化膜りを
形成する。窒化膜16を剥離した後、酸化膜りをイオン
注入のマスクとして、低抵抗部E。
(3) A LOCOS oxide film is formed using the nitride film 16 as an oxidation mask. After peeling off the nitride film 16, the low resistance portion E is formed using the oxide film as a mask for ion implantation.

Gに高濃度イオン注入する。Fは高抵抗部である。酸化
膜りは、イオン注入のマスク性及び上層ドープドガラス
層からの影響を考慮すると、1000A以上は必要であ
る。
High concentration ion implantation into G. F is a high resistance part. The oxide film needs to be 1000 A or more, considering the masking properties of ion implantation and the influence from the upper doped glass layer.

(4)絶縁膜(ドープドガラス層)17を堆積した後、
イオン注入した不純物の活性化の為の高温処理を施し、
低抵抗部E’、G’を形成する。次に、コンタクトホー
ルを開孔し、アルミ配線電極18を設けて、半導体装置
を完成する。
(4) After depositing the insulating film (doped glass layer) 17,
High-temperature treatment is performed to activate the ion-implanted impurities,
Low resistance parts E' and G' are formed. Next, contact holes are opened and aluminum wiring electrodes 18 are provided to complete the semiconductor device.

イオン注入した不純物の活性化の為の熱処理時に、不純
物の横方向拡散により高抵抗部(抵抗素子部分)F′の
長さはLからL′に縮小される。高抵抗値は、長さ方向
に対してはL′、厚み方向は選択酸化後のポリシリコン
膜厚d′で決定される。
During the heat treatment for activating the ion-implanted impurities, the length of the high resistance portion (resistance element portion) F' is reduced from L to L' due to lateral diffusion of the impurities. The high resistance value is determined by L' in the length direction and by the polysilicon film thickness d' after selective oxidation in the thickness direction.

d’<200OAとすることにより、初期膜厚dの時と
比べて、オーダー的に抵抗値を増大することができ、L
′をより小さくすることが可能となる。
By setting d'<200OA, the resistance value can be increased in an orderly manner compared to the initial film thickness d, and L
′ can be made smaller.

上記実施例に於いては、イオン注入により低抵抗部形成
のための不純物導入を行っているが、イオン注入の代わ
りに熱拡散によってもよい〇〈発明の効果〉 以上詳細に説明したように本発明によれば、高抵抗部(
抵抗素子部分)と低抵抗部(接続配線部分)とを含むポ
リシリコン膜を有する半導体装置に於いて、高抵抗部の
素子寸法を非常に小さくすることかできるものであり、
これにより半導体装置の小型化・高密度化が達成される
ものである。
In the above embodiment, impurities are introduced to form a low resistance part by ion implantation, but thermal diffusion may also be used instead of ion implantation. According to the invention, the high resistance part (
In a semiconductor device having a polysilicon film including a resistance element part) and a low resistance part (connection wiring part), the element size of the high resistance part can be made extremely small.
This achieves miniaturization and higher density of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

拵1図は本発明に係る半導体装置の構造及びその製造工
程を示す図、第2図は従来の半導体装置の構造及びその
製造工程の一例を示す図である。 符号の説明 11:半導体基板、12:活性領域、 13.17 :絶縁膜、14:ポリシリコン膜、15:
薄いポリシリコン酸化膜、16:窒化膜、18ニアルミ
配線電極、D:ロコス酸化膜、E’、G’:低抵抗部、
F′:高抵抗部。 代理人 弁理士 福 士 愛 彦(他2名)莫 1ll
121 fつ鳴1ツエ1iゴ刷憲示T図 TA2 図
FIG. 1 is a diagram showing the structure of a semiconductor device and its manufacturing process according to the present invention, and FIG. 2 is a diagram showing an example of the structure of a conventional semiconductor device and its manufacturing process. Explanation of symbols 11: semiconductor substrate, 12: active region, 13.17: insulating film, 14: polysilicon film, 15:
Thin polysilicon oxide film, 16: nitride film, 18 Ni aluminum wiring electrode, D: LOCOS oxide film, E', G': low resistance part,
F': High resistance part. Agent Patent attorney Aihiko Fuku (and 2 others) Mo 1ll
121

Claims (3)

【特許請求の範囲】[Claims] (1)高抵抗部(抵抗素子部分)と低抵抗部(接続配線
部分)とを含むポリシリコン膜を有する半導体装置に於
いて、上記高抵抗部のポリシリコン膜厚を上記低抵抗部
のポリシリコン膜厚より薄くしたことを特徴とする半導
体装置。
(1) In a semiconductor device having a polysilicon film including a high resistance part (resistance element part) and a low resistance part (connection wiring part), the polysilicon film thickness of the high resistance part is determined by the polysilicon film thickness of the low resistance part. A semiconductor device characterized by being thinner than a silicon film.
(2)高抵抗部(抵抗素子部分)と低抵抗部(接続配線
部分)とを含むポリシリコン膜を有する半導体装置であ
って、上記高抵抗部のポリシリコン膜厚を上記低抵抗部
のポリシリコン膜厚より薄くした半導体装置の製造方法
に於いて、選択酸化法によってポリシリコン膜を部分的
に薄くすることにより上記高抵抗部を形成することを特
徴とする、半導体装置の製造方法。
(2) A semiconductor device having a polysilicon film including a high resistance part (resistance element part) and a low resistance part (connection wiring part), wherein the polysilicon film thickness of the high resistance part is equal to the polysilicon film thickness of the low resistance part. 1. A method of manufacturing a semiconductor device which is made thinner than a silicon film, characterized in that the high resistance portion is formed by partially thinning a polysilicon film using a selective oxidation method.
(3)選択酸化法によって高抵抗部上に形成されたポリ
シリコン酸化膜をマスクにして、低抵抗部形成のための
不純物イオン注入又は不純物熱拡散を行うことを特徴と
する、特許請求の範囲第(2)項に記載の半導体装置の
製造方法。
(3) A claim characterized in that impurity ion implantation or impurity thermal diffusion for forming a low resistance part is performed using a polysilicon oxide film formed on a high resistance part by a selective oxidation method as a mask. The method for manufacturing a semiconductor device according to item (2).
JP17676885A 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof Pending JPS6235554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17676885A JPS6235554A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17676885A JPS6235554A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6235554A true JPS6235554A (en) 1987-02-16

Family

ID=16019481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17676885A Pending JPS6235554A (en) 1985-08-08 1985-08-08 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6235554A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6468959A (en) * 1987-09-09 1989-03-15 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6468959A (en) * 1987-09-09 1989-03-15 Nec Corp Semiconductor device

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