JPS62128542A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the concentration of an isolation diffusion layer as source- drain withstanding voltage is left as it is maintained by separating and forming source-drain regions and the isolation diffusion layer without damaging the self-alignment properties of a thick oxide film and the isolation diffusion layer. CONSTITUTION:A wall body 26 consisting of polycrystalline silicon is shaped to the side surface of the inner circumference of an opening section 24 in an silicon nitride film 23, boron ions are implanted and activated to form a p-type isolation diffusion layer 27 on the surface of an silicon substrate 21, and a thick oxide film 28 is shaped in a self-alignment manner with the p-type isolation diffusion layer 27 through selective oxidation while the end sections of the thick oxide film 28 and the end sections of the diffusion layer 27 can be formed at desired distances. Accordingly, since source-drain regions 29, 30 are shaped, using the thick oxide film 28 as a mask and the isolation diffusion layer 27 can be separated, the concentration of the isolation diffusion layer 27 can be increased independently while source-drain withstanding voltage is left as it is kept, thus allowing fining without damaging transistor characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a MIS type semiconductor integrated circuit having a high voltage isolation region.

[Technical background of the invention and its problems]

In MIS type semiconductor integrated circuits, element isolation consists of a thick insulating film and an isolation diffusion layer with a high impurity concentration on the surface of the semiconductor substrate below the insulating film in order to isolate each element that makes up the integrated circuit. forming an area. The thick insulating film and the isolation diffusion layer must be formed in alignment within a certain tolerance for the purpose of device isolation.

The above-mentioned element isolation region has conventionally been formed by the following method. That is, after depositing an oxidation-resistant film on a semiconductor substrate (for example, a p-type silicon substrate), the fit oxidation film corresponding to the element isolation region is selectively removed to form an opening. Next, using the oxidation-resistant film as a mask, impurities of the same → electrical type as the substrate are doped into the substrate through the openings, and then thermal oxidation treatment is performed using the oxidation-resistant film as a mask, and then A thick oxide film is formed on the substrate surface corresponding to the hole. By this method, as shown in FIG. 2, a thick oxide film 2 serving as an element isolation region and a p-type isolation diffusion layer 3 are formed on a Kp-type silicon substrate 1 in a mutually self-aligned manner.

By the way, with the miniaturization of elements, the element isolation regions are also miniaturized, and it becomes necessary to further increase the a degree of the isolation diffusion layer in order to maintain isolation performance.

However, after forming the element isolation regions using the circular method described above, the n-type source and drain regions 4 and 5 are formed using the thick oxide film 2 as a mask as shown in FIG.
The source and drain regions 4 and 5 are in contact with the p-type isolation diffusion layer 3 to form a junction 6. At this time, if the isolation diffusion layer 30a is increased by 1 degree, the breakdown voltage of the junction 6 is lowered, so that the concentration of the isolation diffusion layer 3 cannot be increased independently with respect to 1 degree of the source and drain regions 4 and 5.

For this reason, the method shown in FIG. 3 has been proposed (% Publication No. 59-47471).

First, an oxidation-resistant film 13t is deposited on a p-type silicon substrate 11 via an oxide film 12, and then removed by photolithography to form a first opening 14. Next, the oxidized FJX is exposed from the first opening I4 by photolithography again.
12 is removed to form a second opening I5 spaced a predetermined distance from the inner surface of the opening 14 (3fJ (a1 shown)).Then, the oxidation-resistant film 13 and the oxide film 12 are masked. After doping p-type impurities into the substrate 1 through the second opening 15, a thick oxide film 16 is formed by thermal oxidation using the oxidation-resistant film 13 as a mask, and a p-type isolation diffusion layer 17 is formed. After that, the oxidation resistance 1413 and the oxide film 12 are removed, and the substrate 11 is doped with n-type impurities using the thick oxide film 16 as a mask.
), n-type source and drain regions 18 and 19 are formed separated from the p-type isolation diffusion layer 17. However, since this method employs two photo-etching methods,
The thick oxide film 16 is one of the characteristics of the selective oxidation method described above.
There is a drawback that self-alignment between the layer and the isolation diffusion layer 17 is sacrificed.

[Purpose of the invention]

According to the present invention, the source and drain regions and the isolation diffusion layer are formed apart from each other without impairing the self-alignment between the thick oxide film and the isolation diffusion layer.

It is an object of the present invention to provide a method for manufacturing a semiconductor device that makes it possible to increase the temperature of the isolation diffusion layer by 211 degrees while maintaining the drain breakdown voltage, and also makes it possible to form a predetermined thick oxide film during selective oxidation.

[Summary of the invention]

The present invention includes a step of depositing an oxidation-resistant film on a 14th layer type semiconductor substrate via an oxide film, and a step of selectively removing the oxidation-resistant film to form an opening. forming a polycrystalline silicon wall on the inner surface of the opening; doping the semiconductor and board with a first conductive type 1 impurity using the oxidation-resistant film and the wall as a mask; After removing the wall, selectively oxidizing the surface of the semiconductor substrate except for the area where the oxidation-resistant film is present to form a thick oxide a, and after removing the oxidation-resistant film, using the thick oxide film as a mask. The surface of the semiconductor substrate is doped with a second conductive type impurity to form a source.

The method is characterized in that it includes a step of forming a drain region. According to the present invention, the source and drain regions and the anatomical isolation diffusion layer are formed apart from each other without impairing the self-alignment between the thick oxide film and the 5+ isolation diffusion layer, and the source and drain breakdown voltages are maintained. This makes it possible to increase the concentration of the eyebrow expanding layer, and furthermore, it is possible to form a predetermined thick oxide film during selective oxidation.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1f and 1 to (c+).

First, after acclimating the p-type silicon substrate 2) and forming an oxide film 22 with a thickness of, for example, 100 OA on its surface,
A silicon nitride film 23 was deposited as an oxidation-resistant film to a thickness of, for example, 2000 A' over the entire surface. Subsequently, the silicon nitride film 23 is selectively removed using photoetching technology to form an opening 24, and then a polycrystalline silicon film 25 with a thickness of, for example, 3,500 mm is deposited on the entire surface (first step). Figure (a) shown).

Next, the polycrystalline silicon layer 25 was subjected to anisotropic etching such as reactive ion etching to form a wall 26 made of polycrystalline silicon of g3sooA' on the inner peripheral side surface of the opening of the silicon nitride film 23. Subsequently, zolon was ion-implanted using the silicon nitride EM 23 and the wall 26 as a mask, and was activated to form a p-type isolation diffusion layer 27 with a concentration IQ "CIrL-" (as shown in FIG. 12(b)).

Next, after removing the polycrystalline silicon wall 26t by isotropic etching such as chemical dry etching, the silicon nitride film 23t and the silicon grave 2I exposed as an oxidation-resistant mask are selectively oxidized and removed, and the oxide film 28t is removed. - formed. Subsequently, after forming a dirt oxide film and a dirt magnetic pole (not shown), using the dirt electrode and thick oxide film 28 as a mask, n-type impurities such as arsenic are ion-implanted into the substrate 21 and activated to form n-type sources and drains. Area 29,
A 3θ MOS) transistor was manufactured (the same IN(
C) As shown) According to the present invention, the polycrystalline silicon wall 26 is formed on the inner peripheral side of the opening 24 of the silicon nitride film 23.
Using the silicon nitride film 23 and the wall 26 as a mask, boron ions are implanted and activated to form a p-type isolation diffusion l1i27 on the surface of the silicon substrate 21, and then the wall 26 is removed and the silicon nitride film 23 is removed. By performing selective oxidation using .
8 and the end of the diffusion layer 27 can be separated from each other by a desired distance. In other words, the ends can be separated by about the width of the wall 26. As a result, a thick oxide film 2
Source and drain regions 29 formed using 8 as a mask
, 30 and the separation diffusion layer 27 can be separated from each other.

Since the concentration of the isolation diffusion fi12v can be increased independently while maintaining the drain breakdown voltage, miniaturization can be achieved without impairing the transistor characteristics.

Further, since the wall body 26 is made of polycrystalline silicon and can be selectively removed without causing etching around the opening 24 of the silicon nitride film 23 during etching removal after the separation diffusion layer 27 is formed, the silicon nitride film By performing selective oxidation using 23 as an oxidation-resistant mask, a thick oxide film 28 having a desired size can be formed with high precision and high reproducibility.

Note that the thickness of the silicon nitride film is based on the above value (2000A'
), but may be in the range of 1000 to 3000A0. The reason for this is that the thickness of the silicon nitride film is 100O
If A° is not dropped, the function as an oxidation-resistant mask will be insufficient, and on the other hand, if it exceeds 3000A0t-, the stress strain applied to the silicon substrate during oxidation will increase.

In addition, since the thickness of the polycrystalline silicon film corresponds to the width of the wall that determines the distance between the end of the isolation diffusion layer and the end of the thick oxide film, it is necessary to
What is necessary is just to set it in the range of 00-5000A.

〔Effect of the invention〕

As detailed above, according to the present invention, the sauce.

Semiconductor device IX with high performance and fine element isolation area while maintaining drain breakdown voltage! We can provide A construction method.

[Brief explanation of drawings]

FIG. 1 (al to (C)) shows MOS in the embodiment of the present invention.
Transistor manufacturing process? Figure 2 is a cross-sectional view of a conventional MOS transistor, Figure 3 (a), (bl is another conventional MOS
) FIG. 2 is a cross-sectional view showing the manufacturing process of the transistor. 21... P type 'i' J-con board, 23... Silicon nitride film, 24... Opening part, 26... Wall body, 27
... p-type isolation ripple region, 28 ... thick oxide film, 29
．． 30... Source, drain region. Applicant's representative Patent attorney Takehiko Suzue C) Figure 2 Procedural amendment (method) 1. Indication of the case Japanese Patent Application No. 1983-269650 2. Name of the invention Method for manufacturing semiconductor devices 3. Arrest 1 Related Patent Applicant: (307) Toshiba Corporation 4, Agent Residence 1 1-1 Toranomon, Minato-ku, Tokyo. I261Tr 5
'; 17th Mori Building 〒105 Telephone 0: ((!'
102) :(l 81 (Major Representative) February 2, 1986
5th, 6, i + Ichimasa's original drawing, 1t) 7. Contents of the amendment The figure number of Figure 3 of the drawing is corrected so that it is not attached to the attached sheet. °1

Claims (1)

[Claims] A step of depositing an oxidation-resistant film on a semiconductor substrate of a first conductivity type via an oxide film, a step of selectively removing the oxidation-resistant film to form an opening, and a step of forming an opening in the opening. a step of forming a wall made of polycrystalline silicon on an inner surface; a step of doping the semiconductor substrate with an impurity of a first conductivity type using the oxidation-resistant film and the wall as a mask; and after removing the wall. , forming a thick oxide film by selectively oxidizing the surface of the semiconductor substrate except for the region where the oxidation-resistant film is present; 1. A method of manufacturing a semiconductor device, comprising the step of selectively doping impurities of two conductivity types to form source and drain regions.