JPH04113632A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress generation of hot electrons by providing a step of forming an oxide film, a step of forming a resist pattern, a step of implanting first impurity, a step of reducing the size of the pattern, a step of implanting second impurity, and a step of forming a gate electrode. CONSTITUTION:A field oxide film 2 is formed on a P-type semiconductor substrate l, and a gate oxide film 3 is formed. Then, a resist pattern 4 is formed on the film 3, with it as a mask arsenic ions 5 are implanted to form an N<+> type impurity layer 6. Thereafter, the pattern 4 is isotropically etched to reduce the width of the pattern. Then, with the pattern 4 as a mask, phosphorus ions 7 are implanted to form an N<-> type impurity layer 8. Then, after the pattern 4 is removed, a gate electrode 9 is formed. Subsequently, an oxide film 10 is formed on the electrode 9 by a thermal oxidizing method, and impurities are then diffused simultaneously to form an N<+> type diffused layer 11 and an N<-> type diffused layer 12. Further, an interlayer insulating film 13 is deposited, a contact hole is opened, an aluminum wiring layer 14 is then formed, and a surface protective film 15 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a highly reliable semiconductor device, and particularly to a method for manufacturing a fine MO8h transistor with improved hot electron resistance. In order to improve the hot electron resistance of micro MO5h transistors, lightly doped drains (hereinafter referred to as LDD structure) using sidewall spacers have been used. Figure 2 is a partial enlarged cross section of a conventional LDD structure MOS transistor. It is a diagram.

The conventional method for manufacturing a semiconductor device will be explained below with reference to FIG.
2. Machine for forming gate oxide film 103 and gate electrode 109 made of polysilicon. Using gate electrode 109 as a mask, ions are implanted to form N- diffusion layer 112. Next, a silicon oxide film (Si02 film) is deposited and reacted. Etch back using reactive ion etching (RIE) 1. % side wall spacer 116 is formed. Next, ion implantation is performed using the gate electrode 109 and sidewall spacer 116 as a mask to form the N diffusion layer 111.
Next, an oxide film 110 is formed by dry oxidation, and a contact hole is opened to form an interlayer insulating film 113.
An aluminum wiring layer 114 is formed. Finally, a surface protective film! 1
form 5.

In the conventional method for manufacturing a semiconductor device configured as described above, even if the field strength in the lateral direction is relaxed by forming the ItN- diffusion layer 112, there are still problems to be solved by the invention. Length 0゜8μ
In a miniaturized MOS transistor of less than m, the lateral electric field strength at the surface of the N-diffusion layer 112 becomes high, and hot electrons are generated. this is
This is because the gate electrode 109 is not present directly above the N- diffusion layer 112 and the non-conductive sidewall spacer 116 is present.4 When hot electrons are generated, the performance of the transistor deteriorates and its life is shortened. Therefore, in order to realize a semiconductor device with high performance and high reliability, it is necessary to suppress the generation of hot electrons.

The present invention solves the above-mentioned conventional problems, and aims to provide a manufacturing method for realizing a high-performance, highly reliable semiconductor device that can suppress the generation of hot electrons. In order to achieve the object, the method for manufacturing a semiconductor device of the present invention includes a step of forming an oxide film on a semiconductor substrate, a step of forming a resist pattern on the oxide film, and a first step using the resist pattern as a mask. A step of implanting an impurity, a step of reducing the dimensions of the resist pattern by isotropic etching, a step of implanting a second impurity using the reduced resist pattern as a mask, and an oxide film after removing the resist pattern. This configuration includes a step of forming a gate electrode thereon.

Effect: With this configuration, a conductive gate is formed directly above the low concentration impurity diffusion layer (N- diffusion layer in the case of an Nch transistor) and directly above a part of the high concentration impurity diffusion layer (N0 diffusion layer in the case of an Nch transistor). In addition to having electrodes, the lateral electric field strength on the surface of the low concentration impurity diffusion layer is lower than that in the conventional method.

Therefore, it is possible to suppress the generation of hot electrons and realize a highly reliable semiconductor device with a long life.In addition, the low concentration impurity diffusion layer and the high concentration impurity diffusion layer are formed in a self-aligned manner.8 What is the width of the low concentration impurity diffusion layer? The parts can also be made uniform, making it possible to realize high-precision, high-performance semiconductor devices.

Example Hereinafter, the present invention will be explained based on the drawings.

1(a) to 1(e) are process cross-sectional views showing a method for manufacturing a semiconductor device in an embodiment of the present invention.
) As shown in E, LOCO is placed on the P-type semiconductor substrate 1.
A field oxide film 2 is formed using three methods, and a gate oxide film 3 is formed by thermal oxidation.Next, as shown in FIG. 3(b), a resist pattern 4 is formed on the gate oxide film 3. Using pattern 4 as a mask, arsenic (
As > ions 5 are implanted at 5×15 cm −2 . After the N impurity layer 6 is formed on the P-type semiconductor substrate 1 in this way, the resist pattern 4 is then isotropically etched using oxygen plasma. Reduce the pattern width and then use resist pattern 4 as a mask to irradiate phosphorus (P) ions 7 with 3X
13cm-2 implantation LN=impurity layer 8 is formed.Next, as shown in the same figure (d), after removing the resist pattern 4,
A gate electrode 9 made of polysilicon is formed. The photomask used to form the gate electrode 9 may be the same as the resist pattern 4 used as a mask during arsenic ion implantation, or one with a wider width.
As shown in Figure 2, an oxide film 10 is formed on the gate electrode 9 by thermal oxidation, and at the same time impurity diffusion is performed to form X, N
After forming the diffusion layer 11 and the N-diffusion layer 12, depositing the interlayer insulating film 13, and opening the contact hole,
An aluminum wiring layer 14 is formed, and a surface protection film 15 is formed.

In the structure obtained in this way, a gate electrode 9 made of conductive polysilicon is provided directly above the N-diffusion layer 12 and a portion of the N-diffusion layer 11. The lateral electric field strength at the surface is lower than in the conventional method, suppressing the generation of hot electrons, and making it possible to realize a long-life and highly reliable semiconductor device. 12 is the number N formed in a self-aligned manner using the same resist pattern.
- The width of all the diffusion layers 12 can be formed uniformly. Therefore, no matter which one of the z N° diffusion layers 11 shown in FIG. 1(e) is used as a source or a drain, exactly the same characteristics can be obtained. Although it is possible to form a high-performance semiconductor device, in this embodiment, an It P-type semiconductor substrate 1 is used, a resist pattern 4 is formed, As is ion-implanted using this as a mask, and then the width of the resist pattern 4 is narrowed by etching. The same effect can be obtained even if the order of ion implantation is reversed. In other words, a resist pattern 4 is formed, and P is ion-implanted using it as a mask.The width of the resist pattern 4 is widened by heating and flowing the resist, and then As can be ion-implanted. Further, in this embodiment, an N-type semiconductor substrate using a P-type semiconductor substrate or an N-well formed on a P-type semiconductor substrate may be used. When using an N-well formed on an N-type semiconductor substrate or a P-type semiconductor substrate, boron (B) or boron fluoride (BFa) is used instead of C; t, As, and P ions.
A P' impurity layer and a P- impurity layer are formed using ions. Further, if the gate oxide film 3 is removed by wet etching and then formed again by thermal oxidation before forming the gate electrode 9, the reliability of the gate oxide film 3 is further improved. Furthermore, in forming the gate electrode 9, the overlap area between the gate electrode 9 and the N diffusion layer 11 can be increased by making the gate width wider than the width of the resist pattern 4, which is an ion implantation mask for forming the No or P impurity layer. As the gate capacitance increases, the hot carrier resistance further improves.4However, it is necessary to take into account in the design that the gate capacitance increases and the device speed decreases.

Effects of the Invention As described above, when a semiconductor device is manufactured using the method according to the present invention, there are In this case, even if a conductive gate electrode is formed directly above a part of the N diffusion layer, the lateral electric field strength at the surface of the low concentration impurity diffusion layer is lower than in the conventional LDD formation method. It is possible to suppress the generation of hot electrons and realize a highly reliable semiconductor device with a long life.In addition, the low-concentration impurity diffusion layer and the high-concentration impurity diffusion layer are formed in a self-aligned manner using the same resist pattern as a mask. The width of the low concentration impurity diffusion layer can be made uniform for all transistors. Therefore, it is possible to realize high-precision, high-performance semiconductor devices with uniform characteristics.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are process cross-sectional diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram showing a conventional L
DD structure MO3) Cross-sectional view of transistor: 1... P-type semiconductor substrate (semiconductor substrate), 3... Gate oxide film (thin oxide film), 4... Resist pattern, 5... As ion (first impurity), 7...
P ion, (second impurity) 9...Ga upper electrode.

Claims (4)

[Claims] (1) A step of forming a thin oxide film on the semiconductor substrate,
forming a resist pattern on the thin oxide film; implanting a first impurity using the resist pattern as a mask; reducing the dimensions of the resist pattern by isotropic etching; A method for manufacturing a semiconductor device, comprising the steps of: implanting a second impurity using a thinned resist pattern as a mask; and after removing the resist pattern, forming a gate electrode on the thin oxide film. (2) forming a thin oxide film on the semiconductor substrate;
a step of forming a resist pattern on the thin oxide film, a step of implanting a first impurity using the resist pattern as a mask, a step of heating the resist pattern to increase its dimension, and a step of increasing the dimension. A method for manufacturing a semiconductor device, comprising the steps of implanting a second impurity using a thickened resist pattern as a mask, and forming a gate electrode on the thin oxide film after removing the resist pattern. (3) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein after implanting the second impurity and before forming the gate electrode, the thin oxide film is removed and a new gate oxide film is formed. (4) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the gate electrode is formed to be wider than the width of a resist pattern that is wider among ion implantation masks for implanting the first or second impurity.