JPS62293636A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high performance CMOSIC, by using first-fourth mask materials, alternately forming conductivity type semiconductor regions, thereby forming a trench type isolating region characterized by excellent isolating property. CONSTITUTION:On a first conductivity type semiconductor substrate 101, first mask materials 102a and 103a are formed. The mask materials 102a and 103a on an element-isolating-part forming region in the substrate 101 are selectively removed, and a first hole is formed. With the mask materials 102a and 103a as masks, a tapered groove is formed at the bottom part of the first hole. A second mask material 105a is made to remain in the first hole. A pattern of a third mask material 107 is formed on the remaining mask material 105a. A second hole is formed in the mask material 105a. A second conductivity type semiconductor regions 110 is formed in the substrate 101 through the second hole. A fourth mask material 111a is made to remain in the second hole. The mask material 105a is removed, and a third hole is formed. A first conductivity type semiconductor region 112 is formed in the substrate 110 through the third hole.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
This invention relates to a manufacturing method that improves element isolation technology for MO3 integrated circuits and the like.

BACKGROUND OF THE INVENTION Normally, in order to prevent parasitic channel currents around elements and isolation regions in semiconductor devices, especially MO5ICs, it is common to form highly doped n-type or p-type semiconductor regions. It is a method. For example, as shown in FIG.
+Area 219&.

219b as the drain and source regions, respectively, and an n-channel MO8 formed in the P-type substrate 201.
0MO composed of an n-channel MOS in which regions 220& and 220b are drain and source regions, respectively.
In the 5 elements, an n+ type silicon semiconductor region 210a,
The P type silicon semiconductor region 212a and the like are used as channel cut regions. In conventional manufacturing processes, these channel cut regions are formed by separate photomask processes. Further, other photomask processes are performed, such as a photomask process for forming the n-type well region 208, and a trench-type element isolation region with excellent isolation formed by the polysilicon 216& and the silicon oxide film 202d. In contrast to the photo-mask process, the aforementioned channel cut region was often formed in a separate photo-mask process.

Problems to be Solved by the Invention In general 0MO5IC manufacturing as shown in FIG. A photomask for forming a groove-type element isolation region, a photomask for forming an n-type well portion, and a photomask for forming an n-type channel cut region.

Four photomasks for forming the P+ type channel cut region are used as separate photomasks, and the large number of masks deteriorates the process yield. Further, conduction type reversal occurs on the side surface of the trench type element isolation, which acts as a parasitic bipolar, deteriorating element isolation characteristics or element characteristics.

The present invention solves these problems by reducing the number of masks and their processes, improving manufacturing yield, and eliminating mask alignment margins by increasing self-alignment between each mask process. , to improve the miniaturization of elements, and further,
By forming the element isolation groove into a tapered groove and forming a channel cut region below the tapered groove, parasitic bipolar operation on the side surface of the groove type element isolation is suppressed, and element isolation characteristics and element characteristics are improved. Especially 0MO5I
The present invention provides a method for improving C integration degree and element isolation.

Means for Solving the Problem In order to solve this problem, the present invention provides a step of forming a first mask material on the main surface of a semiconductor substrate of a first conductivity type, and a step of separating elements of the semiconductor substrate. a step of selectively removing the first mask material on the area to be formed and forming a first opening with a first mask material pattern; forming a tapered groove, leaving a second mask material in the first opening, and forming a third mask material pattern having an end on the remaining second mask material. forming a second opening in the remaining second mask material using the first mask material and the third mask material as masks; forming a semiconductor region of a second conductivity type; leaving a fourth mask material in the second opening; selectively removing the second mask material remaining in the first opening; forming a third opening defined by the first mask material and the fourth mask material; and forming a semiconductor region of a first conductivity type in the substrate through the third opening. It is equipped with the following.

Function: With this method, it is possible to form a trench-type isolation region with excellent element isolation by reducing the number of steps using conventional photomasks, and also to realize a miniaturized structure with good self-alignment.
It becomes possible to provide highly integrated, high-performance CMOSICs.

Example An embodiment of the present invention will be described below.

First, for example, on the main surface of a P-type silicon semiconductor substrate, a first
form a mask film. As such mask material, about 5
000 thermal oxide film, silicon nitride film, etc. In some cases, a composite membrane composed of two or more types of membrane materials can be used; for example, one
Approximately 3,000 layers of base CV D-5in2 and 2
A two-layer film composed of approximately 2,000 silicon nitride films can be employed, and combinations of various film materials such as polysilicon films, polycide films, and metal films can also be considered. For convenience, such a diverse coating structure will be regarded as the first mask coating material.

Next, in order to open the intended element isolation portion, for example, the following is formed on the first mask film by a first photomask process.
A resist pattern is formed in which the intended element isolation portion has an opening with a width of submicron or several microns. Using this resist pattern, the first mask coating material is partially or completely removed in the thickness direction to form an opening. Next, using the first mask coating material as a mask, a tapered groove opening upward is formed at the bottom of the opening of the intended element isolation region formed by the first mask coating material. Next, a second mask material is left in the opening of the intended element isolation region formed by the first mask coating material. For example, the following materials can be considered as this second mask material. An oxide film with a thickness of approximately 100 mm is formed by thermal oxidation on the exposed surface of the semiconductor substrate in the intended element isolation area opened by the first mask material, and polysilicon is applied over the entire surface of the intended element isolation area. Polysilicon can be deposited to a thickness sufficiently thicker than half the width of the opening, and can be used as a second mask material by using a back-etching method to leave polysilicon in the opening in the area where element isolation is to be formed.

Then, by a second photo mask process, the CMO
A third mask film is formed to cover the portion of S where the well portion is not formed. It is preferable that the end of the third mask material pattern be located at approximately the midpoint of the opening width of the element isolation formation planned portion where the second mask material is left. Using the thickness of the third mask material, it is possible to selectively implant well-forming n-type impurities into the P-type substrate into the well-forming portion by a method such as ion implantation. In such ion implantation, by changing and combining the implantation energy in various ways, it is possible to create an arbitrary well shape without causing too much high-temperature thermal diffusion.

Then, the exposed second mask material is etched by the masking effects of the first mask coating material and the third mask coating pattern. This makes it possible to expose half of the tapered groove on the surface of the semiconductor substrate at the bottom of the well side of the opening in the planned element isolation formation area, and an n-type impurity region is formed in this area by ion implantation, etc. An n+ type semiconductor region can be used as a channel cut region.

Next, a fourth mask material is left in the half opening on the well side. The fourth mask material is the second mask material described above.
It is necessary to have etching selectivity for the mask material. For example, as the fourth mask material, in addition to an oxide film formed by thermal oxidation, cvn-sio2. By depositing a silicon nitride film or the like to a thickness sufficiently thicker than that of the opening, and then back-etching the film to make it flat, it is possible to use a film that remains in the half opening.

Next, the third mask material is selectively removed by etching to expose the remaining surface of the second mask material. Here, in the opening of this element isolation formation planned portion,
selectively etching the remaining second mask material;
The remaining half of the tapered groove of the P-type semiconductor substrate is exposed, and a P-type channel cut region is formed near the surface of the semiconductor substrate by a method such as ion implantation.

Next, by selectively removing the fourth mask material, the surface of the first half of the semiconductor substrate at the bottom of the opening in the area where element isolation is to be formed is exposed again, and the bottom surface of the area where element isolation is to be formed is completely covered. An opening is made, and a fifth mask material is deposited on the entire surface of this semiconductor system. In this case, the fifth mask material needs to be deposited to a thickness that does not embed the aforementioned element isolation formation area, that is, a thickness smaller than half the width of the opening of the element isolation formation area. For example, as the fifth mask material, CVD-8in2. Examples include deposited films such as silicon nitride films.

Next, reactive ion etching (FtII
The sixth mask material is etched using anisotropic etching such as C) to form a layer with approximately the thickness of the sixth mask material on the side surface of the first mask material that defines the opening of the area where element isolation is to be formed. ,
The surface of the semiconductor substrate is exposed while leaving this sixth mask material.

Next, the exposed semiconductor surface is etched using the first masking material pattern and the fifth masking material pattern left on the side surface thereof as a mask to form a trench for element isolation, and further, this trench is etched. An isolation material is left inside to form a deep element isolation region. Here, the isolation material is an insulating material such as C'i D -5in2, or after the surface of the groove is thinly insulated with a silicon oxide film, etc.
A buried non-conductive or conductive material such as polysilicon can be used.

By this series of means, a well portion of 0 MO3 and n
It is possible to form channel cut regions of type and P type and deep element isolation regions made of an insulator.

The method according to the invention can also be used for manufacturing general semiconductor devices. For example, means are provided for forming complementary P-type and n-type semiconductor regions in a specific region of a semiconductor device, that is, in a first opening formed by a first mask material pattern. For example, the end of the well in 0MO8 can be considered as an electrical element isolation region by a Pn junction, and the P-type, n-type Since the channel cut region maintains self-alignment and is constructed by a means suitable for miniaturization, the element isolation in the present invention does not necessarily have to be limited to a structure having an insulator in a trench-type groove. Good too. Therefore, the means according to the present invention can be employed in various forms as a method for manufacturing semiconductor devices.

Next, a specific example of an 0MO8 element produced by the manufacturing method of the present invention will be described based on FIGS.

(1) First, approximately 3
After forming a thermal oxide film 102 of about 3,000 layers, a silicon nitride film 103 of about 3,000 layers was deposited, and this two-layer composite film was used as a first mask material. Furthermore, a resist pattern 1 for opening the intended element isolation portion is formed on this first mask material by a first photomask process.
04&, 104b was formed [Fig. 2a].

(11) Next, the resist pattern 1042L.

Using the mask 104b as a mask, the silicon nitride film 103 and the thermal oxide film 102, which are the first mask materials, are etched using an anisotropic etching method such as RIE to form an opening approximately 1 μm wide. exposed surface. Further, the exposed portion is etched by an isotropic etching method such as CD1 or an anisotropic etching method to form a tapered groove. Approximately 1
After forming the thin oxide film 102C of 0.00% polysilicon 102C, a polysilicon 102C with a thickness sufficiently thicker than half the width of this opening is formed.
6 was deposited [Fig. 2b].

Ui+) Next, polysilicon 1 is etched back using an etch-back method.
06 was etched flat, and polysilicon 1052L was left in the opening where the element was to be formed, and this was used as a second mask material. Furthermore, after forming an oxide film 106 of approximately 1,000 layers on the surface of the polysilicon 106 of the second mask material by thermal oxidation, a second photomask process is performed to form a portion where an n-channel MOS transistor is to be formed. A covering resist pattern 107 was formed, and ions were implanted using this resist pattern 107 as a mask material to form an n-type impurity region 108. The end of this third mask material connects the formed n-type impurity region to a P-channel MO.
In order to function as a well part for five elements, it is located approximately at the center of the width of the opening in the area where element isolation is to be formed [FIG. 2 CD].

(1v) Next, using the resist pattern 107 as a mask material, the exposed portion of the oxide film 106 is removed to form an oxide film pattern 106&, the resist pattern 107 is removed, and heat treatment is applied to activate the n-type impurity region 108. [Figure 2 d].

(V) Next, using the silicon nitride film 1o3& and the oxide film pattern 1062L as mask materials, an opening 1094 is formed in an area approximately half the width of the area where element isolation is to be formed on the well side. Thin oxide film 102C
A pn+ type channel cut region 110 was formed through the ion implantation method [FIG. 2e].

(■1) Next, CVD-8 inch 2111 was deposited to a thickness sufficiently thicker than the width of the opening 1092L [Fig. 2 f
].

(vt+) Next, OV D -S using the etch pack method
Etch i○2111 flat and make opening 1092L.
CV D 53-02111a was left inside, and this was used as the fourth mask material [Fig. 2g].

(vHi) Next, the silicon nitride film 103b and the fourth
After removing the polysilicon 105b left in the element isolation formation planned area on the side of the n-channel MO3 formation area using the O-machining material CVD S102111a as a mask material and forming an opening 109b, the opening 109b is P is applied by ion implantation through the thin oxide film 102° on the bottom surface.
A channel cut region 112 of the mold was formed (Fig. 2h).

(IX) Next Ec', CVD-8, the fourth mask material
After removing i02111&, approximately 2o is applied to the entire surface of the semiconductor system.
0VD-5in2113 was deposited and used as the sixth mask material [2nd drawing].

(x) Next, etching is performed perpendicularly to the main plane of the semiconductor using an anisotropic etching method such as RIE.
The oxide film 102 of the mask material.

CVI)-8 on the side surface of the opening in the planned element formation area of 102b.
i021132L, 113b about 2000 to the side
I left it at a human thickness [Figure 2 j].

(×1) Next, the oxide film 102J which is the first mask material
102b and the remaining sixth mask material CVD-5
in□113&, 113b as a mask, RIK
Using an anisotropic etching method such as etching, the bottom surface of the area where element isolation is to be formed is etched to a width of approximately 6o○0 and a depth of 1.6μ.
A groove portion 114 of m length was formed. Through this process, CVD
-5in.

Immediately below 113a and 113b are n-type channel cut regions 110 &, P+-type channel cut regions 112I! L was left behind. Furthermore, a thermal oxide film 102a with a thickness of approximately 200 mm was formed on the surface of the semiconductor substrate within the groove 114, and a P-type channel cut region 115 was further formed by ion implantation (FIG. 2k).

(X+0) Next, polysilicon 116 was deposited on the entire surface of the semiconductor system to a thickness sufficiently thicker than half the width of this groove 114 [FIG. 2 1].

(xii+) Next, the polysilicon 116 is etched flat by a back etching method to form an oxide film 102&.

The surface of the polysilicon 102b was exposed, the polysilicon 116 was left in the groove 114, and the surface was thermally oxidized to form an oxide film 117 [FIG. 2 m''l].

(XIV) Next, polysilicon 118& is formed as a gate electrode and P type region 119a by normal 0MO5 manufacturing means.
, 119b as the drain and source portions, respectively, an n-channel MOS transistor with the polysilicon 118b as the gate electrode, and the n-type regions 120 & , 120b as the drain and source portions, respectively [Fig. 2n] . 121a and 121b are silicon oxide films, and 1221L to 122d are electrodes.

It is a material.

Through the above series of steps, a desired 0MO8 element structure was formed.

Effects of the Invention The manufacturing method according to the present invention reduces the number of conventional photomask steps, improves the yield of IC manufacturing, and provides trench-type isolation regions with excellent element isolation. Since a structure that can be formed, has high self-alignment, and is suitable for miniaturization has been realized, it is possible to provide a highly integrated and high-performance 0MO5IC.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor device obtained by a method according to an embodiment of the present invention, FIGS. FIG. 101...Semiconductor substrate, 102...Thermal oxide film, 103...Silicon nitride film, 104...
...Resist pattern, 106...Polysilicon, 106...Thermal oxide film, 1o7・River・
・Resist pattern, 108... impurity region,
109...Opening, 110...N+ type channel cuff) region, 111...G V
D -SiO□, 112...P+ type channel cut region, 113...CVD-5iO□,
114...Element isolation trench opening, 115...
...P+ type channel cut area, 116...
・Poly7 silicon, 117...Thermal oxide film, 118
...Polysilicon gate, 119...
P channel MO8) Source and drain region of transistor, 12o... N channel MO5) Source and drain region of transistor, 121... Oxide film, 122... Electrode material, 201 ... Semiconductor substrate, 202 ... Thermal oxide film, 208 ...
...Impurity region, 210...N type channel cut region, 212...P type channel cut region, 216...P+ type channel cut region, 216... ...Polysilicon, 217.
...Thermal oxide film, 218...Polysilicon gate, 219...P channel MO5) Source and drain region of transistor, 22o...n
Channel MO5) Source and drain regions of transistor, 221...oxide film, 222...electrode material. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 2 Figure 2 Figure 2 /

Claims (1)

[Claims] forming a first mask material on the main surface of a semiconductor substrate of a first conductivity type; selectively removing the first mask material on a portion of the semiconductor substrate where element isolation is to be formed; forming a first opening using a mask material pattern; forming a tapered groove at the bottom of the first opening using the first mask material as a mask; and forming a first opening in the first opening. a step of leaving the second mask material; and a step of leaving the second mask material remaining.
forming a third mask material pattern having an end on the mask material; and forming a second mask material pattern on the remaining second mask material using the first mask material and the third mask material as masks. forming a second conductivity type semiconductor region in the substrate through the second opening;
a step of leaving a fourth mask material in the second opening, and selectively removing the second mask material left in the first opening to separate the first mask material and the fourth mask material. A method for manufacturing a semiconductor device, comprising the steps of forming a third opening defined by a mask material, and forming a first conductivity type semiconductor region in the substrate through the third opening.