JPH02148864A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the formation of a parasitic channel along the sidewall of a groove and to prevent the generation of leaking currents by forming the groove in a semiconductor substrate, doping impurities into the upper part of the side wall of said groove, and forming a channel stopping region. CONSTITUTION:An n<+> type channel stopping region 13 is formed on the sidewall of a deep groove 3 on the side of a p-type well 2. Even if fixed positive charge is present at the interface of SiO2/Si in the groove 3, the formation of a parasitic n-type channel is prevented at the part of said channel stopping region 13. Therefore, even if the parasitic-type channel is supposed to the formed along the sidewall at a part other than the channel stopping region 13 of the deep groove 3, the channel is discontinued at the part of the channel stopping region 13. Thus, the generation of leaking currents between a source region 9 and a drain region 10 and the generation of leaking currents between the source and drain regions 9 and 10 and an n-type Si substrate 1 through said parasitic n-type channel can be prevented. In this way, defects in CMOSLSI due to the leaking currents can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device.
This is suitable for application to the manufacture of SLSI.

[Summary of the invention]

In a method for manufacturing a semiconductor device, the present invention includes forming a groove in a semiconductor substrate and then forming a channel stop region by doping at least the upper part of the side wall of the groove. This prevents the formation of parasitic channels and current leakage. In this case, you can form a deep trench and form a channel stop region on its sidewall, or you can first form a shallow trench, form a channel stop region on its sidewall, and then dig this shallow trench to form a channel stop region on its sidewall. Grooves may be formed, and ion implantation is suitably used as the impurity doping method.

[Conventional technology]

In recent years, in CMO3LSI, technology has been developed to separate a semiconductor substrate and a well of the opposite conductivity type formed in the semiconductor substrate by a deep trench (so-called deep trench).
15olation technology) is used.

FIGS. 6 and 7 show a conventional CMOS LSI using this deep trench isolation technique. As shown in FIGS. 6 and 7, in this conventional CMOS LSI,
For example, a p-well 1 is placed in an n-type silicon (Sl) substrate 101.
02 is formed. Reference numeral 103 is an n-type St substrate 10
1 and the p-well 102;
04 also indicates shallow isolation grooves, these grooves 103
, 104, SiO□ 105 is embedded. A gate insulating film 106 such as a SiO□ film is formed on the n-type St substrate 101 and the p-well 102, and a gate electrode 10 is formed on this gate insulating film 106.
7 is formed. In the p-well 102,
For example, an n-type source region 108 and drain region 109 are formed in self-alignment with this gate electrode 107. These gate electrodes 107 and source regions 10
8 and drain region 109 to form an n-channel MOS
FET T + is configured. On the other hand, n-type St
In the substrate 101, a p1 type source region 110 and a drain region 111, for example, are formed in self-alignment with the gate electrode 107. These gate electrodes 107,
The source region 110 and drain region 111 allow p-channel MO3FET! is configured.

A CMOS inverter is constituted by these n-channel MO3FETTI and p-channel/L/MOS FETTz.

Note that the isolation technology using grooves is described in, for example, Japanese Patent Publication No. 12380/1983, and CMO3LS
Regarding the manufacturing method of I, for example, Japanese Patent Publication No. 63-48179
It is stated in the No.

[Problem to be solved by the invention]

In the conventional CMO3LSI shown in FIG. 6 and FIG. An n-channel 112 is formed. Therefore, the source region 10 of the n-channel MOS FET T I passes through this parasitic n-channel 112.
There is a problem in that leakage current flows between the source region 108 and drain region 109 and between the source region 108 and drain region 109 and the n-type St substrate 101, resulting in failure of the LSI.

Therefore, an object of the present invention is to perform separation using grooves.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent current leakage from occurring due to the formation of a parasitic channel along the sidewalls of the trench.

Another object of the present invention is to provide a method for manufacturing a semiconductor device that can form deep trenches and shallow trenches in a self-aligned manner when isolation by deep trenches and isolation by shallow trenches are used. be.

Another object of the present invention is to provide a method for manufacturing a semiconductor device that allows highly accurate impurity doping for forming a channel stop region.

Another object of the present invention is to provide a method for manufacturing a semiconductor device that can form a mask used for forming a channel stop region with high precision.

Another object of the present invention is to
An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent current leakage caused by the formation of a parasitic channel along the sidewalls of the trench in SI.

[Means to solve the problem]

In order to achieve the above object, the invention of claim 1 provides a method for manufacturing a semiconductor device, in which grooves (3, 4) are formed in a semiconductor substrate (1).
) and forming a mask (1) on the semiconductor substrate (1) so that at least the upper portions of the side walls of the grooves (3, 4) are exposed.
6, 17, 20, 21) and the process of forming a mask (1
The invention of claim 2 is characterized by the step of forming channel stop regions (13, 14) by selectively doping the exposed sidewalls with impurities using In the invention, the groove includes a semiconductor substrate (1) of the first conductivity type and a semiconductor substrate (1) of the first conductivity type.
) is a deep trench (3) for separating the well (2) of the second conductivity type formed in the trench.

In the invention of claim 3, in the invention of claim 1, the groove is a shallow groove (4), and the channel stop region (13, 14)
After forming a shallow groove (4) by anisotropic etching, the semiconductor substrate vi (1) of the first conductivity type and the second semiconductor substrate (1) formed in the semiconductor substrate (1) of the first conductivity type are formed.
A deep groove (3) to separate the conductive type well (2)
According to a fourth aspect of the present invention, in the first aspect of the invention, impurity doping is performed by ion implantation.

The invention according to claim 5 is the invention according to claim 1.2 or 4, in which the masks (16, 17) are formed using a multilayer resist technique.

The invention of claim 6 is the invention of claim 1, 2, 3.4, or 5, wherein the semiconductor device is a CMO3LSI.

[Effect]

According to the first aspect of the invention, since the channel stop region can be formed in the upper part of the side wall of the trench, it is possible to prevent a parasitic channel from being formed in the channel stop region. Therefore, even if a parasitic channel is formed along the sidewall of the groove in a portion other than the channel stop region, this parasitic channel will be interrupted in the channel stop region.

Therefore, it is possible to prevent current leakage due to the formation of a parasitic channel along the sidewalls of the trench.

According to the invention of claim 2, the channel stop region can be formed at least on the sidewall of the deep trench for separating the semiconductor substrate of the first conductivity type and the well of the second conductivity type. Current leakage due to the formation of parasitic channels along the sidewalls of the trench can be prevented.

According to the third aspect of the invention, since the channel stop region can be formed at least on the upper part of the side wall of the shallow groove, after the deep groove is formed by digging the shallow groove, at least the side wall of the deep groove can be formed. This channel stop region will exist at the top. This can prevent current leakage due to the formation of a parasitic channel along the sidewalls of this deep trench.

According to the fourth aspect of the invention, impurity doping can be performed with high precision by performing impurity doping by ion implantation.

According to the fifth aspect of the present invention, by forming the mask using multilayer resist technology, the mask can be formed with high precision without being affected by steps on the surface of the semiconductor substrate. Thereby, using this mask, impurity doping can be accurately performed only in necessary regions.

The invention of claim 6 is a CMO3LS that performs separation using a groove.
In I, it is possible to prevent a parasitic channel from being formed along the sidewall of this trench and causing current leakage.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. The following three examples are examples in which the present invention is applied to the manufacture of CMO3LSI using deep trench isolation.

First, for convenience of explanation, a CMOSL according to Example I of the present invention will be described.
The configuration of CMO3LSI manufactured by the SI manufacturing method will be described. FIG. 1 is a plan view of the main part of this CMOS LSI, and FIG. 2 is a sectional view taken along line nn in FIG.

As shown in FIGS. 1 and 2, C according to this embodiment I
In MOSLSI, for example, p
Well 2 is formed. Reference numeral 3 denotes an n-type Si substrate 1
The reference numeral 4 indicates a deep groove for isolation between the p-well 2 and the p-well 2, and reference numeral 4 indicates a shallow isolation groove.

Here, the depth of the deep groove 3 is, for example, 2 to 3 μm, and the depth of the shallow groove 4 is, for example, 0.5 to 1.0 μm. 5iOz5 is embedded inside these grooves 3 and 4. In addition, for example, Sin! is formed on the n-type Si substrate 1 and the p-well 2. A gate insulating film 6 like a film is formed, and a gate electrode 7 is formed on this gate insulating film 6.

The gate electrode 7 can be formed of a polycrystalline Si film doped with impurities or a polycide film in which a refractory metal silicide film is superimposed on a polycrystalline Si film doped with impurities. The side walls of this gate electrode 7 are made of, for example, a sinusoid.
, a sidewall spacer 8 is formed. In the p-well 2, a source region 9 and a drain region 10 of, for example, an n-type are formed in self-alignment with the gate electrode 7. These gate electrodes 7,
Source region 9 and drain region 10 allow n-channel M
An O3FETQ1 is configured. On the other hand, in the n-type Si substrate 1, for example, p
A type source region 11 and drain region 12 are formed. These gate electrode 107, source region 11 and drain size J>112 form a P-channel MO3FET.
Q is configured. And these n-channel M
A CMOS inverter is configured by the O3FETQ and the p-channel MO3FETQ. In this case, in the source region 9 and drain-in region 10 of the n-channel MO3FETQ+, for example, n-type low impurity concentration regions 9a and 10a are formed below the sidewall spacer 8. Therefore, this n-channel MO3FET Q1 has an LDD (Lightly Doped
Drain) structure. Similarly, p-channel M
In the source region 11 and drain region 12 of the OS FET Qt, for example, p-type low impurity concentration parts 11a and 12a are formed below the sidewall spacer 8, and have an LDD structure.

Furthermore, in this CMOS LSI, a p0 type channel stop region 13, for example, is formed on the sidewall and/or bottom surface of the trench 3.4 in the p well 2. On the other hand, n
For example, an n'-type channel stop region 14 is formed on the sidewall and/or bottom surface of the groove 3.4 in the Si substrate 1.

Next, a method of manufacturing a CMOS LSI according to this embodiment (2) will be explained.

As shown in FIG. 3A, first, a p-well 2 is formed by selectively ion-implanting a p-type impurity, such as boron (B), into an n-type Si substrate 1. To give a specific example of the conditions for this ion implantation, the dose t1.6X10I3
ell-”, injection!nel-f-550 keV (when 84+1 is used).

Next, on this n-type Si substrate 1, for example, thermal oxidation or CV
An insulating film 15 such as a SiO□ film is formed by the D method. Next, a predetermined portion of this insulating film 15 is removed by etching to form an opening 15a, and then, using this insulating film 15 as a mask, the semiconductor substrate 1 is etched in a direction perpendicular to the substrate surface by, for example, reactive ion etching (RIE). A deep groove 3 is formed by anisotropic etching.

Next, as shown in FIG. 3B, a first layer of resist 16 is applied to the entire surface so that the groove 3 is completely filled, and SOG (Spin) is applied on top of this first layer of resist 16.
on Glass) film 17 and second layer resist 1
8 to form a 3N resist, a second layer of resist 18 is patterned into a predetermined shape. Next, using this second layer resist 18 as a mask, the SOG film 17 is
is etched into the shape shown in FIG. 3B. After this,
The second layer of resist is removed for one day. Note that it is not necessarily necessary to use a 3N resist as described above; for example, a 2N resist is used.
It is also possible to use an N resist.

Next, using the SOG film 17 as a mask, the first layer resist 16 is anisotropically etched by, for example, RIE to expose the upper part of the sidewall of the trench 3 on the P-well 2 side, as shown in FIG. 3C. Next, by ion-implanting a p-type impurity such as B from a direction oblique to the substrate surface, the above-mentioned exposed upper part of the sidewall is doped with the p-type impurity. To give a specific example of the conditions for this ion implantation, the dose amount is 3 x 101! cm-”, injection energy 30ke
It is V. By this ion implantation, the p-well 2 of the groove 3 is
For example, a p0 type channel stop region 13 is formed in the upper part of the side wall. After this, the SOG film 17 and the first layer resist 16 are removed.

Next, by performing oblique ion implantation of an n-type impurity such as phosphorus (P) in the same manner as described above, an n-type impurity, for example, is implanted into the upper part of the other side wall of the trench 3, as shown in Figure 3. A channel stop region 14 is formed. To give a specific example of the conditions for this ion implantation, the dose it 3 x 10
l3C11-”% implantation energy 30 k e V
It is. Thereafter, the insulating film 15 is removed by etching.

Next, as shown in FIG. 3C, the inside of the groove 3 is made of, for example, SiO2.
□Fill in with 5. Specifically, for example, 5i
After forming the 0z film on the entire surface so thick that the inside of the trench 3 is completely filled with the 5iCh film, this Sin film may be etched back.

Next, as shown in FIG. 3F, after forming a shallow groove 4 in the p-well 2 and the n-type Si substrate 1, diagonal ion implantation is performed on both side walls and the bottom of the groove 4 in the p-well 2 to form a p° type. While forming the channel stop region 13, the n-type Si substrate 1
Similarly, n0 type channel stop regions 14 are formed on both side walls and the bottom of the inner groove 4 by oblique ion implantation. Thereafter, the inside of this groove 4 is filled with 5iOz5.

Next, for example, a SiO□ film is formed on the surfaces of the n-type Si substrate 1 and the p-well 2 by, for example, a thermal oxidation method, and this SiO□
After forming a polycrystalline Si film doped with impurities on the film, the polycrystalline Si film and the Si film are patterned into a predetermined shape by etching to form gates as shown in FIGS. 1 and 2. An insulating film 6 and a gate electrode 7 are formed. Next, first, with the surface on the P-channel MO3FETCh side covered with a resist or the like, an n-type impurity such as P is ion-implanted at a low concentration into the p-well 2 using the gate electrode 7 as a mask, and then the same method is used. n-type Si group vi
1, using the gate electrode 7 as a mask, for example, a p
For example, CV
After forming, for example, a Si0g film on the entire surface by method D, this stag film is anisotropically etched by, for example, RIE method to form sidewall spacers 8 on the side walls of gate electrode 7.Next, first, for example, p-channel MOS F E
After ion-implanting an n-type impurity such as arsenic (As) at a high concentration into the p-well 2 using the sidewall spacer 8 and gate electrode 7 as a mask with the surface on the TQ side covered with a resist or the like, , n-type S
P-type impurities such as B are ion-implanted into the i-substrate 1 at a high concentration using the sidewall spacers 8 and the gate electrode 7 as masks. Thereafter, the implanted impurities are electrically activated by heat treatment. This allows the first
As shown in the figure and FIG. 2, a source region 9 and a drain region 10 having low impurity concentration portions 9a and 10a are formed in the p-well 2 in a self-aligned manner with respect to the gate electrode 7. Channel MOS FET Q
I is formed. Similarly, a source region 11 and a drain region 12 having low impurity concentration portions 11a and 12a are formed in the n-type Si substrate 1 in a self-aligned manner with respect to the gate electrode 7, and a p-channel MOSFETQa having an LDD structure is formed. be done. In this way, the target CMO3LSI is completed as shown in FIGS. 1 and 2.

According to this embodiment (2), since the n1 type channel stop region 13 is formed on the side wall of the deep groove 3 on the p-well 2 side, the Sin! Even if a fixed positive charge exists at the /St interface, a parasitic n-channel can be prevented from being formed in this channel stop region 13. Therefore, even if a parasitic n-channel is formed along the sidewall of the deep trench 3 in a portion other than the channel stop region 13, this parasitic n-channel is interrupted at the channel stop region 13, so the parasitic n-channel Current leakage between the source region 9 and the drain region 10 through the source region 9 and the drain region 1
Current leakage between the n-type Si substrate 1 and the n-type Si substrate 1 can be prevented from occurring.

As a result, the CMOS LSI due to this current leakage
It is possible to prevent defects. In addition, the channel stop region 13 formed on the side wall of the deep trench 3 can prevent current leakage through the parasitic n-channel, so for example, if a shallow trench is formed between the deep trench 3 and the source region 9, There is no need to form an element isolation region. As a result, a high concentration of CMO3LSI v
i density can be achieved.

Furthermore, since the masks 16 and 17 used when forming the channel stop regions 13 and 14 by ion implantation are formed using 3N resist technology, the n-type St
The mask 16 is not affected by the step on the surface of the group vi1.
．． 17 can be formed with high precision, and as a result, the channel stop regions 13 and 14 can be formed in desired regions with high precision. Furthermore, since impurity doping is performed by ion implantation, impurity doping can be performed with high precision.

Back side patch work Figures 4A to 4E are CMO3 according to Example H of the present invention.
A method for manufacturing an LSI will be shown in order of steps.

In this embodiment (2), as shown in FIG. 4A, a p-well 2 is first formed in an n-type Si substrate 1, and then an insulating film 15 such as an SiO□ film is formed on this n-type Si base Fi1. form. Next, a predetermined portion of this insulating film 15 is removed by etching to form an opening 15b.
Using this as a mask, the n-type S1 substrate 1 is anisotropically etched by RIEi to form a shallow groove 4.

Next, as shown in FIG. 4B, the first
After forming a three-layer resist consisting of the first resist layer 16, the SOG film 17, and the second resist layer 18, the second resist layer is patterned into a predetermined shape. In this case, only a shallow groove 4 is formed, and n
Since the level difference on the surface of the type Si substrate 1 is not so severe, it is sufficient to simply apply one layer of ordinary resist without forming the 3N resist as described above.

Next, using the second layer resist 18 as a mask, 5OG1
*After etching 17, this second layer of resist 1
Next, using the SOG film 17 as a mask, the first
By anisotropically etching the resist layer 16 using the RIE method, for example, the SOG film 17 and the
For example, if the i-th resist 16 is used as a mask,
For example, a p-type channel stop region 13 is formed by oblique ion implantation of type impurities.Next, the side walls and bottom surface of the trench 4 in the portion covered with the first layer resist 16 are formed in a similar manner. For example, an n-type channel stop region 14 is formed by performing oblique ion implantation of an n-type impurity such as P. After this, the SOG film 17
Then, the 1Nth resist 16 is removed.

Next, as shown in the fourth diagram, a resist 19 is applied to the entire surface, and then this resist 19 is patterned into a predetermined shape to expose the surface of the area where the deep groove is to be formed.

Next, using the resist 19 and the insulating film 15 as a mask, anisotropic etching is performed by, for example, RIE to dig the shallow groove 4 described above, and as shown in FIG. After forming a deep groove 4 for separation from the resist 19, the resist 19 is removed.

After this, proceed with the process in the same manner as described in Example ①,
Complete the target CMO3LSI.

According to this embodiment (■), in addition to the same advantages as in embodiment I,
It also has the following advantages: That is, first, a shallow groove 4 is formed, and then only the shallow groove 4 that will become a deep groove is dug by anisotropic etching to form a deep groove 3.
, these deep grooves 3 and shallow grooves 4 can be formed in a self-aligned manner. By this, C
Further higher integration density of MOSLSI can be achieved.

Furthermore, since the deep groove 3 and the shallow groove 4 can be formed in a self-aligned manner, it is possible to achieve even higher integration density of the CMOS LSI.

1. Figures 5A to 5 are CMOS according to the embodiment of the present invention.
A method for manufacturing an LSI will be shown in order of steps.

In this embodiment (2), as shown in FIG. 5A, the steps are first carried out in the same manner as in the embodiment (2) to form shallow grooves 4. Next, after applying resist 20 to the entire surface, this resist 20 is patterned into a predetermined shape. Next, by performing oblique ion implantation of a p-type impurity such as B using this resist 20 as a mask, a p4-type channel stop region 13, for example, is formed on the side wall and bottom of the trench 4. After this, the resist 20 is removed.

Next, as shown in FIG. 5B, a resist 21 is applied to the entire surface, and then this resist 21 is patterned into a predetermined shape.

Next, using this resist 21 as a mask, oblique ion implantation of an n-type impurity such as P is performed, so that, for example, an n-type channel stop region 14 is formed on the side wall and bottom surface of the trench 4 that is not covered with this resist 21. form. After that, the resist 21 is removed.

Next, as shown in FIG. 5C, a resist 22 is applied to the entire surface, and then this resist 22 is patterned into a predetermined shape.

Next, a part of the insulating film 15 is etched away by performing anisotropic etching by, for example, RIE using the resist 22 as a mask. Etching away a part of the insulating film 15 in this way is done by etching the n-type S in the shallow trench 4 described above.
This is because the P+ type channel stop region 13 formed on the sidewall on the i-substrate I side needs to be removed. In this case, if the width of the removed portion of the insulating film 15 is a, then a≧alignment error+depth of channel stop region 13. After this, the resist 22 is removed.

Next, as shown in the fifth diagram, a resist 23 is applied to the entire surface, and then this resist 23 is patterned into a predetermined shape to expose the surface of the area where the deep groove is to be formed. Here, α and β in the fifth diagram are 0th order larger than the alignment error. Using the resist 23 and the insulating film 15 as a mask, the n-type St substrate 1 is anisotropically etched by, for example, the RIE method to form deep grooves. form 3. In this case, if the depth of this anisotropic etching is t, it is necessary that t≧s+d. Here, S is the depth of the shallow groove 4, and d is the thickness of the channel stop region 13. Specifically, t is, for example, 0.6 to 1.1 μm.

After this, the resist 23 is removed. After the product was formed in this way, the process was carried out in the same manner as described in Example ①.
Complete the target CMOS LSI.

According to this embodiment m, in addition to the same advantages as the embodiment
Since the width of the deep groove 3 can be reduced, CMOS
This has the advantage that it is possible to achieve even higher integration density of LSI.

In this embodiment (2), the p-type channel stop region 13 is formed only to the depth of the shallow groove 4, but if the channel stop region 13 is to be formed deeper, for example, a so-called retrograde p-well is formed. When forming the groove 2 by ion implantation of B, the implantation energy and dose may be selected so that the peak concentration of B is deeper than the shallow trench 4.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications are possible based on the technical idea of the present invention.

For example, in the above embodiment (2), the n'' type channel stop region 14 is replaced by the p'' type channel stop region 13.
Although the channel stop region 14 is formed by a method similar to that of the above, the channel stop region 14 can also be formed using, for example, the following method. That is, by implanting n-type impurity ions over the entire surface without forming a mask at a dose lower than the dose of the p-type impurity ion implanter for forming the P0 type channel stop region 13, n. It is possible to form a channel stop region 14 of the type. In this case, the impurity concentration in the p+ type channel stop region 13 is reduced due to impurity compensation, but the dose of the n type impurity is set to be more than the dose of the p type impurity for forming the p type channel stop region 13. If the p-type impurity dose is selected to be as low as 3×10”ell −, no practical problem will arise.
”, the dose of n-type impurity is, for example, 11
5, that is, about 6×10” cm.

Further, in Example I, the p' type channel stop region 13 in the deep trench 3 may have a shape as shown by the dashed line in FIG. 3C. Furthermore, it is not always necessary to form the n0 type channel stop region 14 on the side wall of the deep groove 3 on the n type Si substrate 1 side.

Furthermore, it is also possible to use a material other than resist as a mask material when forming the channel stop regions 13, 14 by ion implantation.

Furthermore, in the above-mentioned Examples I, Il, and III, the n-channel MOSFET Q + and the p-channel MOSFETQ have an LDD structure.
ETQ does not necessarily have to have an LDD structure.

In addition, in the above-mentioned Examples I, n, and III,
Although the present invention has been described for the case where it is applied to the manufacture of CMOS LSI, the present invention can be applied to, for example, bipolar-CMOS LSI.
It is also possible to apply it to the production of SI.

〔Effect of the invention〕

Since the present invention is configured as described above, it has the following effects.

According to the invention of claim 1, it is possible to prevent current leakage from occurring due to the formation of a parasitic channel along the sidewalls of the trench.

According to the second aspect of the invention, when a semiconductor substrate and a well are separated by a deep trench, it is possible to prevent current leakage from occurring due to the formation of a parasitic channel along the sidewalls of the deep trench.

According to the third aspect of the invention, when a semiconductor substrate and a well are separated by a deep trench, it is possible to prevent a parasitic channel from being formed along the sidewalls of this deep trench and cause current leakage. The groove and the shallow groove can be formed in a self-aligned manner.

According to the fourth aspect of the invention, impurity doping for forming a channel stop region can be performed with high precision.

According to the fifth aspect of the invention, a mask used when forming a channel stop region can be formed with high precision.

According to the invention of claim 6, the CMO using groove separation
In SLSI, it is possible to prevent current leakage due to the formation of a parasitic channel along the sidewalls of this trench.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the main parts of a CMOS LSI manufactured by the CMOS LSI manufacturing method according to Example I of the present invention;
Figure 2 is a sectional view taken along the line ■-■ in Figure 1, Figure 3A
- FIG. 3F are cross-sectional views showing the method for manufacturing a CMOS LSI according to the embodiment (2) of the present invention in the order of steps, and FIGS. 5A to 5A are cross-sectional views showing the manufacturing method of a CMOS LSI according to the embodiment (1) of the present invention in the order of steps, and FIG. 6 is a plan view of the main parts of a conventional CMOS LSI.
FIG. 7 is a sectional view taken along the line ■-■ in FIG. 6. Explanation of main symbols in the drawings 1: n-type Si substrate, 2: p-well, 3: deep groove,
4: Shallow groove, 5: 5iOz, 7: Gate electrode,
9.11: Source region, 10, 12 Nidrain region, i3. t4: Channel stop region, 15:
Insulating film, 16, 18.19, 20.21, 22.23
Niresist, 17:50G film, Q: n-channel MOS FET, Qz: p-channel MO3FE
T.

Claims (1)

[Claims] 1. A step of forming a groove in a semiconductor substrate; a step of forming a mask on the semiconductor substrate so that at least an upper part of the side wall of the groove is exposed; A method of manufacturing a semiconductor device, comprising the step of forming a channel stop region by selectively doping the sidewall with an impurity. 2. Claim 1, wherein the groove is a deep groove for separating the semiconductor substrate of the first conductivity type from the well of the second conductivity type formed in the semiconductor substrate of the first conductivity type. A method of manufacturing the semiconductor device described above. 3. The groove is a shallow groove, and after forming the channel stop region, the shallow groove is dug by anisotropic etching to form a semiconductor substrate of a first conductivity type and a semiconductor substrate of the first conductivity type. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a deep groove for separating the well of the second conductivity type. 4. The method of manufacturing a semiconductor device according to claim 1, 2 or 3, wherein the impurity doping is performed by ion implantation. 5. The method of manufacturing a semiconductor device according to claim 1, 2 or 4, wherein the mask is formed using a multilayer resist technique. 6. The method of manufacturing a semiconductor device according to claim 1, 2, 3, 4 or 5, wherein the semiconductor device is a CMOS LSI.