TW468250B - An advanced low-leakage architecture for sub-0.18 μm salicided CMOS device - Google Patents

Abstract

A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduced contact leakage.

Description

4 6 82 5 〇. Winning the number V. Description of the invention (1) [Background of the invention 〇) The invention of the invention

It's about the method. (2) Xi reason to use Wuzui) In addition to the lack of pad oxidation and thus the shallow 2 * 7 in the main pole 30 series' will be produced by a kind of know-how and the traditional limitations of the device. The illustrated technology, which is moved into a corner trench isolation region in a cross-section, is related to the manufacture of integrated circuit devices, and more specifically, the formation of low leakage shallow trench isolation technology in integrated circuit manufacturing is shrunk by silicon. The formation of shallow trenches in shallow trenches will also cause depressions. If there are 20 edges in the area, the plan view shows the problem of the field. The small size is 0.2 5 microns or less, and the isolation will be a smaller channel. Width encroachment (Isolation can be used to eliminate these encroachments in special devices. In the trench isolation area, after the trench is filled, the corner area of the shallow trench isolation area is lined up, as shown in Figure 1. Formed on the semiconductor substrate 1 〇There are corner recesses 25. It will form sharp corners which will lead to high electric fields and leakage currents. Polycrystalline silicon gates. When polycrystalline silicon gates exceed sharp corners 27. This is also a well-known _, polycrystalline silicon coating effect " The secondary valve hump will be caused in the metal oxide semiconductor transistor formed in the active area. The secondary valve hump 21 is an abnormal metal oxide semiconductor device ID — VG curve 'which is isolated by the accumulation of sharp shallow trenches Corner 2 7 is caused by a high voltage field, as illustrated in Figure 2. Figure 2 illustrates the gate electrode voltage t as a function of the saturation current ID. ^ A high electric field will cause the " VA -krak "phenomenon represented by 21. Which will result in a higher secondary valve leakage current

4 6 82 5 0 _Abandonment number 89107744 V. Description of the invention (2) and the difficulty of controlling the valve voltage. The second problem is illustrated in Figure 3. After the source / drain region 34 is metallized 32, the recessed corner 25 will allow the interface to leak 35. The third problem occurs when forming borderless contact, as shown in Figure 4. The polycrystalline sand contact 40 is formed on the shallow trench isolation area, which will cause an excessive contact leakage current 41 deep into the shallow trench isolation area. Many patents have proposed the formation of shallow trenches. U.S. Patent No. 5, 8 3 4 360 (Tesauro et al.) Teaches etching a trench in a substrate, 'forming a stone cutting barrier layer in the trench and a silicon nitride spacer on the trench wall surface, and then Silicon is oxidized to form a field oxide region in the trench. U.S. Patent No. 5,637,529 (jang et al.) Teaches the formation of silicon nitride spacers on the surface of the silicon nitride layer over time, and then etching the trenches in the substrate between the spacers. The germanium is implanted ion Below the trench, a field oxidation region is formed in the trench. U.S. Patent No. 5,78,0,325 (Ue et al.) Forms an ion-implanted region in a substrate; forms a spacer on an opening wall surface in an insulating layer on the implanted region; etches through the implanted region A trench such that the implanted area is under a spacer on the wall surface of the trench; and then filling the trench. U.S. Patent No. 5,795,81 1 (Kim et al.) Forms the opening walls in the spacer insulation and etches between the spacers-trenches in the substrate. A one-stage trench filling and etchback complete the isolation area. US Patent No. 5 '753, 562 (Kim et al.) Teaches a shallow trench isolation method in which a factory trench is filled with silicon nitride and an oxide layer. The substrate is inverted where the bottom of the trench becomes the top of the trench to avoid corner depressions. [Summary of the invention] 4 6 82 5 〇 Case No. 89107744 May 5. Description of the invention (3) Amendment Therefore, the main purpose of the present invention is to provide a process for forming shallow trench isolation in the manufacture of integrated circuits. -Another object of the present invention is to provide a process for forming a shallow trench isolation that avoids exposure of the edges of the shallow trench isolation field. Another object of the present invention is to provide a process for forming a shallow trench isolation 'in which there is a flat transition region between the active region and the isolation region. Another object of the present invention is to provide a process for forming a stepped shallow trench isolation. Another object of the present invention is to provide a process for forming a stepped shallow trench isolation having a reduced width of a nitride spacer. Another object is to provide a stepped shallow trench isolation process with a channel field implant to reduce isolation leakage. Another object is to provide a stepped shallow trench isolation process with barrier nitride implantation and channel field implantation to reduce isolation leakage. Another object is to provide a process for forming a self-aligned nitride spacer for forming an etch stop layer formed as a borderless contact to reduce contact leakage. According to the purpose of the present invention, a method for forming a stepped shallow trench isolation is achieved. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited on the pad oxide. The first nitride layer not covered by the mask is etched through to provide an opening to the pad oxide layer. A first trench is etched in the opening. 46 825 Ο _ Case No. 89107744_ Month-Year-Amendment V. Description of the Invention (4) Pass through the hafnium oxide layer and enter the semiconductor substrate. A second nitride layer is deposited on the first nitride layer and fills the first trench. At the same time, the second nitride layer is etched with anisotropic silver to form gaseous spacers on the wall of the first trench, and the semiconductor substrate not covered by the spacers is etched to form a first Second ditch. Ions are implanted into a semiconductor substrate under the second trench. The first and second trenches are filled with an oxide layer. Secondly, the first nitride and the pad oxide layer are removed, and the formation of the shallow trench isolation is completed in the manufacture of the integrated circuit device. The nitride spacer shallow trench isolation structure can avoid oxide depressions in the corners of the shallow trenches and allow the formation of borderless contacts. This unique process will reduce junction leakage current and also reduce contact leakage current. [Brief description of the drawing] 10 semiconductor substrate 25 corner depression 3 0 polycrystalline chip 34 source / drain region 4 0 polycrystalline silicon contact 4 2 pad oxide layer 46 trench 50 spacer 56 field implanted region 70 gate Electrode 74 Silicide 78 Boundaryless contact 2 Shallow trench isolation area 27 Sharp corner 32 Metal silicide 35 Contact leakage 41 Contact leakage current 44 Silicon nitride layer 4 8 Blanket-type nitride nitride 52 Ditch 6 60 Shallow trench isolation area 7 2 Source and drain regions 7 6 Intermediate dielectric layer

Page 11 d6 825 0 __Case No. 89107744__Year Month and Day ___ V. Description of the invention (5) [Description of the preferred embodiment] The process of the present invention provides a way to avoid the exposure of shallow trench isolation field edges, (the exposure will be Leading to high field edge junction leakage) stepped shallow trench isolation. A thin barrier nitride spacer is used in the process of the invention. The presence of this spacer will allow channel field implantation to reduce isolation leakage. This is particularly important in devices having a feature size of 0.18 microns or less. The manufacturing process of the present invention will be described with reference to FIGS. 5 to 12. Referring now more particularly to FIG. 5, a semiconductor substrate is shown. A pad oxide layer 42 is grown on the surface of the semiconductor substrate to a thickness between about 50 and 200 Angstroms. A silicon nitride layer 44 is deposited on the pad oxide layer 12 to a thickness between about 1000 and 2000 Angstroms.

A photoresist mask (not shown) is formed on the surface of the nitride layer having an opening ', where the opening is where the shallow trench isolation area is formed. Using conventional optical lithography and etching techniques, the nitride layer is etched, leaving an opening where the isolation region is formed. Referring now to FIG. 6 ', using the silicon nitride as a hard mask, the oxide layer and the semiconductor substrate exposed in the opening are etched to a depth of about 2000 to 3500 angstroms to form a trench 46. Referring now to Figure 7 '-blanket silicon nitride 48 deposition is made on the surface of the soil plate and in the trench. The silicon nitride layer is deposited to a thickness of about 300 to 100 Angstroms. As illustrated in FIG. 8, 'the silicon nitride layer 48 is anisotropically etched': a spacer 50 is left on the wall surface of the trench 46. This etching step also etches--deeper trenches 52 in trenches that are not covered by nitride spacers 50

Page 12 m 4 6 82 5 0 Amendment No. 89107744 V. Description of the invention (6) In the substrate under 46, the trench 52 has a depth between about 500 and 2500 Angstroms. The silicon nitride spacer has a width of about 300 to 100 Angstroms.

So far, an opposite NMOS-PMOS field implantation mask (not shown in the figure) has been formed on the substrate, and ions have been implanted into the semiconductor substrate under the deep trench 52 'to avoid leakage. The field implantation area 56 shown in Fig. 9 will be N + or P + depending on the neighboring devices. For example, an N + field implant may include boron or boron fluoride ions implanted at a dose between about 1 × 1011 to 1 × 10iatoms / cm2 at an energy of 30 to 80 keV. The -P + field implantation may include scales or god ions implanted at a dose of between about 10 and 1 × 10 μs atoms / Cffl2 at an energy of 30 to 80 keV. An oxide layer is deposited on the surface of the substrate by a chemical vapor deposition method and fills the trench. The oxide layer may have a thickness between about 4000 and 8000 angstroms. The oxide layer is polished by a chemical mechanical polishing method having a polishing stopper on the nitride layer 44. The resulting shallow trench isolation area 60 is illustrated in Figure 10 as an example. So far, the silicon nitride layer 4 and 4 have been removed by using electrical equipment. Because the electric paddle return # is directional, the nitride spacer 50 is protected by the oxide layer 60 and has not been removed. Second, the pad oxide 42 is removed. This will produce a flat nitride spacer 50 corner, as shown in Figure 11. Processing continues in the traditional manner of the art. For example, as illustrated in FIG. 12 ', a gate oxide and a polycrystalline silicon layer are deposited on the surface of the substrate' and are etched to form a gate electrode 70. The source of the gate electrode 70 and the non-electrode region 72 may be formed in an active region between the isolation regions, as is conventional in the art. The gate electrode and source / drain regions can be silicided74

Page 13 46 8250

__ Case No. 8flin77M V. Description of the invention (7), such as the traditional method. A After performing the silicidation of the process of the present invention, there is no leakage at the interface. As shown in Fig. 3, the junction leakage 35 is caused by the recess 25 in the corner of the shallow trench isolation zone, allowing current from the underlying conductive layer (not shown in the figure) to pass through, and into the source / drain in the substrate Area 34. In the manufacturing method of the present invention, as shown in FIG. 12, the recess 65 is surrounded by the silicon nitride spacer 50. FIG. 13 illustrates the formation of the non-border contact 78. The general process does not allow a borderless contact. Because the intermediate dielectric layer 76 and the shallow trench isolation 60 are both oxides, contact etching will cause excessive loss of shallow trench isolation oxides (as shown in Figure 4). However, in the process of the present invention, the nitride spacer 50 at the junction of the active region of the shallow trench is blocked as a meal to prevent the shallow trench isolation oxide from being excavated. Therefore, contact leakage is reduced. The manufacturing process of the present invention will cause the formation of stepped shallow trench isolation. The shallow trench isolation field edge exposure is avoided by the presence of the thin nitride spacer. After silicidation, it will inevitably avoid leakage at the high electric field edge junction. The stepped shallow trench isolation with silicon nitride spacers will allow channel field implantation to reduce isolation leakage ', especially in devices with a feature size of 018 microns or smaller. This borderless contact process is fully supported by the process of the present invention. Although the present invention has been specifically shown 'and explained with reference to its preferred embodiments', it should be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention. Fan Ming

Page 14 d6 8250 __Case No. 89107744_ Year Month Amendment _ Brief Description of Drawings Figures 1, 3 and 4 are cross-sectional views showing one embodiment of the conventional art. Figure 2 is a diagram of the VA-kmk phenomenon in shallow trench isolation with the conventional art of excessive corner oxide depressions. Figures 5 to 13 are cross-sectional representations of a preferred embodiment of the present invention.

Page 15

Claims (1)

46 8250 --- Case No. 8910774 + __ Leather Month__ VI. Scope of Patent Application1. A method for forming shallow trench isolation in the manufacture of integrated circuits, including: a pad oxide layer is deposited On a semiconductor substrate surface; a first nitride layer is deposited on the pad oxide layer; the first nitride layer is engraved to provide an opening σ to the pad oxide layer; a first trench Is etched through the opening through the pad oxide layer and enters the semiconductor substrate; a second nitride layer is deposited on the first nitride layer and fills the first trench; and at the same time the The second nitride layer is anisotropically etched to form a nitride spacer on the wall of the first trench, and a semiconductor substrate not covered by the spacer is pushed in to form a second trench ion implantation. Into the semiconductor substrate under the second trench; the first and second trenches are filled with an oxide layer; second, the first nitride and pad oxide layer are removed, and the integrated circuit device End of the manufacturing order The STI = the configuration. . For example, the method of claiming a patent scope item 1, wherein the liner gasification layer has a thickness between about 50 and 200 Angstroms. The nitride layer trench has a value of 3. · The method of claim 1, wherein the first It is deposited to a thickness of between about 1000 and 2000 Angstroms. 4. If the method of applying for item (1) of the patent scope, Page 16 46 8250 __Case No. 89107744_Year Month Date Amendment ___ Sixth, the scope of patent application is about 200 to 3,500 Angstroms. 5. The method of claim 1 in which the second nitride layer is deposited to a thickness between about 300 and 100 angstroms. 6. The method of claim 1 in which the second trench has a depth between about 500 and 2500 Angstroms. 7. The method of claim 1, wherein the spacer has a width between about 300 and 100 angstroms. 8. The method of claim 1 in the scope of patent application, wherein the step of simultaneously anisotropically carving the second nitride layer and the semiconductor substrate is performed using anisotropic plasma etching. 9. The method of claim 1, wherein the step of implanting ions comprises implanting at a dose between about 1 X 1 011 to 1 X 1 013 a 100 ms / cm2 with an energy of 30 to 80 keV Boron or boron fluoride ions to form an N + field implanted region under the shallow trench isolation. I 0 'As in the method of claim 1, wherein the step of implanting ions includes phosphorous implanted at a dose between about 1 X 10 " and 1 X 10] 3 atoms / cra2 at an energy of 30 to 80 keV Or arsenic ions, and a p + field implanted region is formed under the shallow trench isolation. II. The method of claim 1 in the scope of patent application, wherein the step of filling the first and second trenches comprises: depositing an oxide layer by chemical vapor deposition to between about 40Q0 and 8Q00 Angstroms Thickness; and polishing the oxide layer using a chemical mechanical polishing method having a polishing stopper on the first nitride layer. 46 8250 ------ MM 89107744__ Car Moon Day Chromium π: VI. Patent Application Park 1 2 'The method of applying for the first item of patent scope' further includes the semiconductor substrate between the shallow trench isolations Middle and upper semiconductor device structures are manufactured. i3 • A method for forming shallow trench isolation in integrated circuit manufacturing, comprising: a pad oxide layer is deposited on a surface of a semiconductor substrate; a first nitride layer is deposited on the pad oxide Layer; engraving the first nitride layer 'to provide an opening to the pad oxide layer; a first trench is etched through the lining oxide layer' in the opening and enters the semiconductor substrate t; '-a second nitride layer is deposited on the first nitride layer and fills the first trench;' at the same time 'the first II compound layer is engraved by an anisotropic meal to form a gas spacer On the wall surface of the first trench, and the semiconductor substrate that is not covered by the spacer. The covered semiconductor substrate is silvered in, and a second trench rod is ion-implanted into the semiconductor substrate under the second trench to form a channel. Field implantation; depositing an oxide layer on the first nitride layer and filling the first and second trenches; and W polishing the chemical mechanical polishing method with a polishing stopper on the first nitride layer Oxide layer; its The first nitride and the pad oxide layer are removed, in which the nitride spacer will prevent leakage 46 8250 I No. 89107744 Sixth, the patent application Fan Yuan electricity passes through the oxidation in the first and second trenches The exposed corner of the physical layer 'completes the structure of the shallow trench isolation in the fabrication of the integrated circuit device. ^ 14 The method of claim 13 in which the pad oxide layer has a thickness between about 50 and 200 angstroms. 15: The method of claim 13 in which the first nitride layer is deposited to a thickness of between about 1000 and 2000 angstroms. 16. The method according to item 13 of the patent application, wherein the first trench has a thickness between about 2000 and 3500 Angstroms. 17. The method of claim 3, wherein the second nitride layer is deposited to a thickness between about 300 and 1000 angstroms. 18 * The method of claim 13 in which the second trench has a depth between about 500 and 2500 Angstroms. 19. The method of claim 3, wherein the spacer has a width between about 300 and 100 angstroms. 2 0. The method of claim 3, wherein the step of simultaneously anisotropically etching the second nitride layer and the semiconductor substrate is performed using anisotropic plasma etching. 21 · The method according to item 13 of the patent application, wherein the step of implanting ions comprises implanting at a dose between about 1 X 1 01] and 1 X 1 〇13 at 〇ms / cm2 with an energy of 30 to 80 keV Implanted boron or boron fluoride ions to form an N + field implanted region below the shallow trench isolation. 22. The method of claim 13 in the scope of patent application, wherein the step of implanting ions comprises a dose between about 1 X 1 〇ι 1 to 1 X 1 〇i3 a 70ms / cm2, Page 19 46 8250 __Case No. 89107744__ Month of this month τ_ VI. Patent application: Phosphorus or arsenic ions implanted with energy of 30 to 80 keV to form a ρ + field implanted area to isolate the shallow trench Below. 23. The method of claim 13 further includes fabricating a semiconductor device structure in and above the semiconductor substrate between the shallow trench isolations. 24. A method for forming shallow trench isolation in integrated circuit manufacturing, comprising:-a pad oxide layer is deposited on a surface of a semiconductor substrate; a first nitride layer is deposited on the pad On the oxide layer; engraving the first nitride layer to provide an opening to the pad oxide layer; a first trench in the opening is penetrated through the lining oxide layer 'and enters the In a semiconductor substrate; a second nitride layer is deposited on the first nitride layer and fills the first trench; at the same time, the second nitride layer is anisotropically etched to form a nitride spacer on the first nitride layer A second trench is formed on the wall surface of the first trench and the semiconductor substrate not covered by the spacer, and ions are implanted into the semiconductor substrate under the second trench to form a channel field implant; Depositing an oxide layer on the first nitride layer and filling the first and second trenches; using a chemical mechanism having a polishing stopper on the first nitride layer 46 8250 Amendment ^ E 89107744 6. Polishing the oxide layer with a patent-applied polishing method; Secondly, the first nitride and pad oxide layer are removed, wherein the nitride spacer will prevent leakage. Pass through the The exposed corners of the oxide layer in the first and second trenches complete the structure of the shallow trench isolation; forming a gate electrode and an associated source / drain region between the shallow trench isolations; and The gate electrode is silicified with the source / drain region to complete the fabrication of the integrated circuit device. 25. The method of claim 24, wherein the first and second trenches have a combined depth of between about 2500 and 600 Angstroms. 26. The method of claim 24, wherein the spacer has a width between about 300 and 1000 Angstroms. Page 21