CN114256329A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN114256329A
CN114256329A CN202111562643.1A CN202111562643A CN114256329A CN 114256329 A CN114256329 A CN 114256329A CN 202111562643 A CN202111562643 A CN 202111562643A CN 114256329 A CN114256329 A CN 114256329A
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side wall
forming
layer
semiconductor device
region
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许昭昭
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

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  • General Physics & Mathematics (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and a method of forming the same, wherein the semiconductor device comprises: a substrate having a drift region therein; a plurality of gate structures located on the drift region, the gate structures including opposing first and second sidewalls; the first side wall is positioned on the surface of the first side wall; the second side wall is positioned on the surface of the second side wall, and the second side wall is also positioned on part of the surface of the drift region; source-drain doped regions respectively located on two sides of the gate structure, the first side wall and the second side wall; the blocking dielectric layer is positioned on the surface of the second side wall; the performance of the finally formed LDMOS semiconductor device can be effectively improved, so that the formed LDMOS semiconductor device has a wider application range.

Description

Semiconductor device and method of forming the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, as well as higher integration and higher performance.
LDMOS (Laterally Diffused Metal Oxide Semiconductor) is a power device with a double diffusion structure. This technique is performed by ion implanting the substrate twice, one with arsenic (As) at a higher concentration and the other with boron (B) at a lower concentration. The implant is followed by a high temperature anneal process, which, because boron diffuses faster than arsenic, diffuses further along the lateral direction under the gate boundary, forming a concentration-graded channel whose channel length is determined by the difference between the two lateral diffusions. In order to increase the breakdown voltage, there is a drift region between the source and drain regions.
The drift region in the LDMOS is the key of the design of the device, and the impurity concentration of the drift region is lower, so that when the LDMOS is connected with high voltage, the drift region can bear higher voltage due to high resistance. In addition, the LDMOS has characteristics of high gain and good reliability, and can have good process compatibility with the CMOS, and thus the LDMOS is being widely used.
However, the performance of the existing LDMOS is poor.
Disclosure of Invention
The invention aims to provide a semiconductor device and a forming method thereof, which can effectively improve the performance of the finally formed LDMOS semiconductor device and enable the formed LDMOS semiconductor device to have a wider application range.
To solve the above problems, the present invention provides a semiconductor device comprising: a substrate having a drift region therein; a plurality of gate structures located on the drift region, the gate structures including opposing first and second sidewalls; the first side wall is positioned on the surface of the first side wall; the second side wall is positioned on the surface of the second side wall, and the second side wall is also positioned on part of the surface of the drift region; source-drain doped regions respectively located on two sides of the gate structure, the first side wall and the second side wall; and the blocking dielectric layer is positioned on the surface of the second side wall.
Optionally, the blocking dielectric layer is made of silicon oxide.
Optionally, the thickness of the second sidewall is 300 angstroms to 2000 angstroms.
Optionally, the thickness of the blocking dielectric layer is 300 to 1500 angstroms.
Optionally, the second sidewall further covers a portion of the top surface of the gate structure.
Optionally, the method further includes: and the first conductive plug is positioned on the blocking medium layer.
Optionally, the semiconductor device further comprises a body region located in the drift region, the body region is located in the drift region between adjacent gate structures, and the source-drain doped region adjacent to the gate structure is located in the body region.
Optionally, the semiconductor device further comprises a heavily doped region located in the body region, and the heavily doped region is located between the adjacent source and drain doped regions.
Optionally, the semiconductor device further includes a metal silicide layer located in the top of the gate structure, in the source-drain doped region, and in the heavily doped region.
Correspondingly, the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a substrate; forming a drift region in the substrate; forming a plurality of gate structures on the drift region, wherein each gate structure comprises a first side wall and a second side wall which are opposite; forming a first side wall on the first side wall, and forming a second side wall on the second side wall and part of the surface of the drift region; forming source-drain doped regions on two sides of the gate structure, the first side wall and the second side wall; and forming a barrier dielectric layer on the surface of the second side wall.
Optionally, the blocking dielectric layer is made of silicon oxide.
Optionally, the thickness of the second sidewall is 300 angstroms to 2000 angstroms.
Optionally, the thickness of the blocking dielectric layer is 300 to 1500 angstroms.
Optionally, the step of forming the first sidewall and the second sidewall includes: forming an initial sidewall layer on the substrate, on the drift region, on a top surface of the gate structure, on the first sidewall, and on the second sidewall; and etching the initial side wall layer by taking the first patterning layer as a mask on the initial side wall layer, forming a first side wall on the first side wall, forming a second side wall on the second side wall and part of the surface of the drift region, and covering part of the top surface of the gate structure by the second side wall.
Optionally, before forming the first side wall and the second side wall, the method further includes: forming a sacrificial layer on the substrate, wherein the sacrificial layer is internally provided with a first opening, and the bottom of the first opening exposes the surface of the drift region between the adjacent gate structures; carrying out ion doping on the exposed drift region to form a body region; and removing the sacrificial layer.
Optionally, the step of forming source-drain doped regions on two sides of the gate structure, the first side wall and the second side wall includes: and doping the drift regions on two sides of the first side wall and the second side wall to form the source-drain doped region.
Optionally, the method further includes: removing the first patterning layer to form a second patterning layer, wherein a second opening is formed in the second patterning layer, and the bottom of the second opening exposes the surface of the initial side wall layer between the adjacent source drain doping regions; etching the initial side wall layer by taking the second patterning layer as a mask until the bottom of the second opening exposes the body region between the adjacent source drain doped regions; the bottom of the second opening exposes the body region between the adjacent source-drain doped regions; and carrying out ion doping on the exposed body region to form a heavily doped region.
Optionally, the method further includes: removing the second patterned layer, and forming an initial blocking dielectric layer on the substrate to cover the gate structure, the drift region, the first side wall and the second side wall; and selectively etching the initial barrier dielectric layer to form a barrier dielectric layer on the surface of the second side wall.
Optionally, the method further includes: and forming a first conductive plug on the blocking medium layer.
Optionally, the method further includes forming a metal silicide layer in the top of the gate structure, in the source-drain doped region, and in the heavily doped region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the semiconductor device, the second side wall on the surface of part of the drift region and the blocking dielectric layer on the second side wall are simultaneously used as field plate dielectric layers, and the formed first conductive plug is used as a field plate conductive electrode and is connected to a gate structure or a source region in a source-drain doped region through a metal layer to form a field plate for assisting the depletion of the drift region.
Drawings
FIG. 1 is a schematic structural diagram of a semiconductor device in one embodiment;
fig. 2 to 8 are schematic structural diagrams illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The electrical performance of the LDMOS in the prior art is still to be improved. The following detailed description will be made in conjunction with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a semiconductor device in one embodiment.
Referring to FIG. 1, an N-LDMOS is shown as an example: a P-type substrate/P-type epitaxial layer 101, a Shallow Trench Isolation (STI) 102 located in the P-type substrate/P-type epitaxial layer 101, a gate insulating medium layer 103 located on the P-type substrate/P-type epitaxial layer 101, a gate polysilicon 104 located on the gate insulating medium layer 103, a drift region and RESUR layer implantation 105 located in the P-type substrate/P-type epitaxial layer 101, a P-type body region implantation 106 located in the drift region and RESUR layer implantation 105, a sidewall medium layer 107 located on the sidewall of the gate insulating medium layer 103 and the gate polysilicon 104, a metal silicidation reaction barrier silicon oxide layer 108 located on the sidewall medium layer 107 on one side, N-type heavily doped implantations 109 located on both sides of the sidewall medium layer 107, and a P-type heavily doped implantation 110 located between the adjacent N-type heavily doped implantations 109, a metal Silicide (Silicide)111 located in the top of the gate polysilicon 104, the N-type heavily doped implant 109, and the P-type heavily doped implant 110, a stop layer (stop layer) insulating Dielectric stack 112 located on the metal Silicide (Silicide)111 and the metal Silicide reaction barrier silicon oxide layer 108 during etching, an Interlayer Dielectric (ILD) 113 located on the stop layer (stop layer) insulating Dielectric stack 112 during etching, a contact via 114 located in the Interlayer Dielectric 113, and a metal layer 115 located on the contact via 114.
The inventors have found that in the above embodiments, for a semiconductor device requiring a higher Breakdown Voltage (BV), the thicker metal silicide blocking layer silicon oxide layer 108 is required to be used as a field plate dielectric layer of the LDMOS device, and the contact via 114 is used as a field plate conductive electrode. However, the thickness of the metal silicide blocking layer silicon oxide layer 108 may not meet the optimum Breakdown Voltage (BV) or on-resistance (R) for higher Breakdown Voltage (BV) semiconductor devicesSP) The design requirement of (a), therefore, how to thicken the thickness of the field plate dielectric layer is very important relative to the design of the contact hole field plate LDMOS with higher Breakdown Voltage (BV).
The inventor finds that the second side wall on the surface of a part of the drift region and the blocking dielectric layer on the second side wall are simultaneously used as field plate dielectric layers, a first conductive plug formed subsequently is used as a field plate conductive electrode, the first conductive plug is connected to a gate structure or a source region in a source-drain doped region through a metal layer to form a field plate for assisting in depletion of the drift region, and at the moment, as the thickness of the dielectric layer below the metal at the bottom of the first conductive plug is increased, an electric field generated during breakdown is reduced, so that the critical voltage of a semiconductor device is not easily reached, a breakdown field is not easily generated, and the formed semiconductor device has higher comprehensive performance of Breakdown Voltage (BV).
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to 8 are schematic structural diagrams illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
First, referring to fig. 2, a substrate 200 is provided.
In this embodiment, the substrate 200 is made of monocrystalline silicon.
In other embodiments, the substrate 200 may also be polysilicon or amorphous silicon. The substrate 200 may also be made of germanium, silicon germanium, gallium arsenide, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or other semiconductor materials.
In this embodiment, no fins are present on the substrate 200.
In other embodiments, fins may also be drawn on the substrate 200.
In this embodiment, the substrate 200 has an isolation structure 201 thereon.
In the present embodiment, the isolation structure 201 is a Shallow Trench Isolation (STI) structure.
In this embodiment, the step of forming the isolation structure 201 includes: forming a shallow trench opening in the substrate 200, depositing silicon oxide in the shallow trench opening by using HDP CVD, removing excess silicon oxide by using CMP, planarizing until the substrate 200 is exposed, and forming the isolation structure 201 in the substrate 200.
With continued reference to fig. 2, a drift region 202 is formed within the substrate 200.
In this embodiment, when the substrate 200 is used to form an N-type LDMOS, the type of ions implanted to form the drift region 202 includes an RESURF layer formed by N-type ions and P-type ions located below the N-type ions;
in other embodiments, when the substrate 200 is used to form a P-type LDMOS, the type of ions implanted to form the drift region 202 includes a RESURF layer composed of P-type ions and N-type ions located below the P-type ions;
in this embodiment, the forming process of the drift region 202 is as follows: after the isolation structure 201 is formed, ion implantation is performed in the substrate 200 to form the drift region 202.
With continued reference to fig. 2, a number of gate structures 203 are formed over the drift region 202.
In this embodiment, the gate structure 203 includes a gate dielectric layer 204 located on the substrate 200, the isolation structure 201 and the drift region 202, and a polysilicon layer 205 separately located on the gate dielectric layer 204.
In this embodiment, the gate structure 203 is formed by first forming the gate dielectric layer 204 on the substrate 200; a polysilicon layer 205 is then formed on the gate dielectric layer 204.
The gate dielectric layer 204 provides a material layer for subsequent formation of a gate structure.
The gate dielectric layer 204 is made of silicon oxide.
In the present embodiment, the gate dielectric layer 204 is formed by an In-Situ Steam Generation (ISSG). The gate dielectric layer 204 formed by the in-situ steam generation process has good step coverage capability, so that the formed gate dielectric layer 204 can be tightly covered on the substrate 200, and the thickness of the formed gate dielectric layer 204 is uniform.
In another embodiment, the forming process of the gate dielectric layer 204 is a high temperature thermal oxidation process; and carrying out high-temperature heat treatment on the silicon surface by an oxygen introducing dry method to form the gate dielectric layer 204.
The method of forming the polysilicon layer 205 includes: forming a polysilicon film (not shown) covering the substrate 200; and etching the polysilicon film to expose the gate dielectric layer 204, and forming the polysilicon layer 205 on the gate dielectric layer 204.
In this embodiment, the number of the gate structures 203 is two.
In other embodiments, the number of gate structures 203 can also be three, four, etc. in different numbers.
In the present embodiment, the gate structure 203 includes a first sidewall 206 and a second sidewall 207 opposite to each other.
With continued reference to fig. 2, a sacrificial layer 208 is formed on the substrate 200, the sacrificial layer 208 has a first opening 209 therein, and a bottom of the first opening 209 exposes a surface of the drift region 202 between adjacent gate structures 203.
In this embodiment, the material of the sacrificial layer 208 is photoresist.
In the present embodiment, the first opening 209 exposes the first sidewall 206 of the gate structure 203.
With continued reference to fig. 2, the body region 210 is formed by ion doping the exposed drift region 202.
In the present embodiment, the doped ions in the body region 210 are of the opposite type to the doped ions above and within the drift region 202.
In the present embodiment, the ions doped in the body region 210 are P-type ions.
In the present embodiment, the doping depth of the body region 210 is less than the doping depth of the drift region 202.
Referring to fig. 3, the sacrificial layer 208 is removed, and an initial sidewall layer 211 is formed on the substrate 200, on the drift region 202, on the top surface of the gate structure 203, on the first sidewall 206, and on the second sidewall 207.
In this embodiment, the process of removing the sacrificial layer 208 is a wet process.
In this embodiment, the material of the initial sidewall layer 211 is silicon oxide.
In this embodiment, the material of the initial sidewall layer 211 is silicon oxide for the purpose of: silicon nitride is also a dielectric layer, but silicon nitride has more Trap/Trap, easily causes Trap to Trap charges under large voltage to cause BV stability, compared with silicon oxide has less Trap, is not easy to Trap charges and has good stability, therefore, the reliability of the device is better.
In this embodiment, the forming process of the initial sidewall layer 211 is a chemical vapor deposition process.
In other embodiments, the forming process of the initial sidewall layer 211 may also be one or more of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 4, a first patterned layer 212 is formed on the initial sidewall layer 211, the initial sidewall layer 211 is etched by using the first patterned layer 212 as a mask, a first sidewall 213 is formed on the first sidewall 206, a second sidewall 214 is formed on the second sidewall 207 and a portion of the surface of the drift region 202, and the second sidewall 214 also covers a portion of the top surface of the gate structure 203.
In this embodiment, the process of etching the initial sidewall layer 211 is anisotropic etching.
In this embodiment, the anisotropic etching is specifically dry anisotropic etching, and the parameters of the dry anisotropic etching are as follows: using gases containing fluorine (e.g. CH)3F、CH2F2Or CHF3) Argon and oxygen, the etching power is 200W-400W, the pressure of the etching cavity is 30 mtorr-200 mtorr, and the etching temperature is 40 ℃ to 60 ℃.
In this embodiment, after the anisotropic etching, the first sidewall 213 is formed, a portion of the initial sidewall layer 211 on the top of the gate structure 203 is etched away, and the second sidewall 214 is formed to be covered by the first patterning layer 212.
In this embodiment, during the etching process, the exposed gate dielectric layer 204 is also etched away.
In this embodiment, the second sidewall 214 is formed on the second sidewall 207, and meanwhile, the second sidewall 214 also covers a part of the surface of the drift region 202, so that the second sidewall 214 on a part of the surface of the drift region 202 can be directly used as a field plate dielectric layer, and the thickness of the field plate dielectric layer is increased by phase change, so as to prepare for forming a semiconductor device with a larger breakdown voltage in the following process.
In this embodiment, the second sidewall 214 also covers a portion of the top surface of the gate structure 203, so as to prevent the subsequent source/drain doped region 215 from entering the surface of the drift region 202 on the side surface of the gate structure 205.
In the present embodiment, the thickness of the second sidewall 214 is 300 to 2000 angstroms; when the thickness of the second sidewall 214 is less than 300 angstroms, BV-Rsp of the high voltage resistant device cannot be optimized because the thickness of the second sidewall 214 is too thin; when the thickness of the second sidewall 214 is greater than 2000 angstroms, the BV-Rsp of the low voltage device may not be optimized because the thickness of the second sidewall 214 is too thick. .
In this embodiment, the first sidewall 213, the second sidewall 214 and the first patterned layer 212 further determine the position of a source/drain doped region to be formed subsequently.
Referring to fig. 5, the drift region 202 on both sides of the first sidewall 213 and the second sidewall 214 is doped to form the source-drain doped region 215.
In this embodiment, the source/drain doped region 215 is formed by an ion implantation process.
When the semiconductor device is an N-type device, ions doped in the source and drain doped regions are N-type ions, and the N-type ions comprise phosphorus ions or arsenic ions. When the semiconductor device is a P-type device, ions doped in the source-drain doped region are P-type ions, and the P-type ions comprise boron ions, BF 2-ions or indium ions.
In this embodiment, the semiconductor device is an N-type device, the source-drain doped region is made of silicon, and the source-drain ions are phosphorus ions and arsenic ions.
In other embodiments, the semiconductor device is a P-type device, the source-drain doped region is made of silicon germanium, and the source-drain ions are boron ions.
Referring to fig. 6, the first patterned layer 212 is removed to form a second patterned layer 216, the second patterned layer 216 has a second opening 217 therein, the bottom of the second opening 217 exposes the surface of the initial sidewall layer 211 between the adjacent source/drain doped regions 215, the initial sidewall layer 211 is etched with the second patterned layer 216 as a mask until the bottom of the second opening 217 exposes the body region 210 between the adjacent source/drain doped regions 215, and a sidewall silicon oxide layer is formed on the gate sidewall of the P-type MOS device to perform ion doping on the exposed body region 210 to form a heavily doped region 218.
In the present embodiment, the ion type doped in the heavily doped region 218 is opposite to the ion type doped in the source/drain doped region 215.
In the present embodiment, the ion type doped in the heavily doped region 218 is P-type ion.
Referring to fig. 7, the second patterned layer 216 is removed, and an initial blocking dielectric layer (not marked in the figure) is formed on the substrate 200 to cover the gate structure 203, the drift region 202, the first sidewall spacers 213, and the second sidewall spacers 214; and selectively etching the initial barrier dielectric layer to form a barrier dielectric layer 219 on the surface of the second side wall.
In this embodiment, the blocking dielectric layer 219 is a metal silicidation reaction blocking dielectric layer for preventing a metal silicide from being formed on a portion of the silicon or polysilicon surface during the metal silicidation reaction.
In this embodiment, the thickness of the blocking dielectric layer 219 is 300 to 1500 angstroms; when the thickness of the blocking dielectric layer 219 is less than 300 angstroms, the BV-Rsp of the high-voltage device cannot be optimized optimally due to the fact that the thickness of the blocking dielectric layer 219 is too thin; when the thickness of the blocking dielectric layer 219 is greater than 1500 angstroms, BV-Rsp of the low withstand voltage device may not be optimized because the thickness of the blocking dielectric layer 219 is too thick.
In this embodiment, the second sidewall 214 on the surface of the drift region 202 and the blocking dielectric layer 219 on the second sidewall 214 are both used as field plate dielectric layers, and then the formed first conductive plug is used as a field plate conductive electrode, and the field plate for assisting depletion of the drift region is formed by connecting the metal layer to the gate structure or the source region in the source-drain doped region.
In this embodiment, the process of forming the blocking dielectric layer 219 includes a chemical vapor deposition process.
In other embodiments, the process for forming the blocking dielectric layer 219 may be one or more of a chemical vapor deposition process and a physical vapor deposition process.
Referring to fig. 8, a metal layer (not labeled) is formed on the substrate 200, the metal layer performs a metal silicide reaction with the top surface of the gate structure 203, the top surfaces of the source-drain doped regions 215, and the top surface of the heavily doped region 218 to form the metal silicide layer 220, and an etch stop layer 221 is formed on the substrate 200, the isolation structure 201, the surface of the blocking dielectric layer 219, and the top surface of the metal silicide layer 220; forming an interlayer dielectric layer 222 on the etching stop layer 221, forming a plurality of contact holes in the interlayer dielectric layer 222, filling a metal layer in the contact holes, forming a first conductive plug 223 on the blocking dielectric layer 219, forming a second conductive plug 224 on the source-drain doped region 215, and forming a third conductive plug 225 on the top of the gate structure 203.
In this embodiment, the materials of the first conductive plug 223, the second conductive plug 224, and the third conductive plug 225 are all metals.
In this embodiment, the step of forming the interlayer dielectric layer 222 includes: an interlayer dielectric layer material is formed on the etching stop layer 221, and the interlayer dielectric layer material is planarized to form the interlayer dielectric layer 222.
With continued reference to fig. 8, a metal layer 226 is formed on the first conductive plug 223, the second conductive plug 224 and the third conductive plug 225.
In this embodiment, the second sidewall 214 on the surface of the drift region 202 and the blocking dielectric layer 219 on the second sidewall 214 are simultaneously used as field plate dielectric layers, the formed first conductive plug 223 is used as a field plate conductive electrode, and the metal layer 226 is connected to the gate structure 203 or the source region in the source/drain doped region 215 to form a field plate for assisting depletion of the drift region, at this time, because the thickness of the dielectric layer under the metal at the bottom of the first conductive plug 223 is increased, the electric field generated during breakdown is decreased, which does not easily reach the critical voltage of the semiconductor device, so that the field of breakdown is not easily generated, and the formed semiconductor device has higher overall performance of Breakdown Voltage (BV).
Accordingly, referring to fig. 8, the present invention further provides a semiconductor device, including: a substrate 200 having a drift region 202 therein; a plurality of gate structures 203 located on the drift region 202, the gate structures 203 including opposing first and second sidewalls 206 and 207; a first sidewall 213 disposed on a surface of the first sidewall 206; a second sidewall 214 on the surface of the second sidewall 207, wherein the second sidewall 214 is also on a portion of the surface of the drift region 202; source-drain doped regions 215 respectively located at two sides of the gate structure 203, the first sidewall 213 and the second sidewall 214; and a blocking dielectric layer 219 on the surface of the second sidewall 214.
In this embodiment, the material of the blocking dielectric layer 219 is silicon oxide.
In the present embodiment, the thickness of the second sidewall 214 is 300 to 2000 angstroms; when the thickness of the second sidewall 214 is less than 300 angstroms, BV-Rsp of the high voltage resistant device cannot be optimized because the thickness of the second sidewall 214 is too thin; when the thickness of the second sidewall 214 is greater than 2000 angstroms, the BV-Rsp of the low voltage device may not be optimized because the thickness of the second sidewall 214 is too thick.
In the present embodiment, the thickness of the blocking dielectric layer 219 is 300 to 1500 angstroms.
In this embodiment, the blocking dielectric layer 219 is a metal silicidation reaction blocking dielectric layer for preventing a metal silicide from being formed on a portion of the silicon/polysilicon surface during the metal silicidation reaction.
In this embodiment, the thickness of the blocking dielectric layer 219 is 300 to 1500 angstroms; when the thickness of the blocking dielectric layer 219 is less than 300 angstroms, the BV-Rsp of the high-voltage device cannot be optimized optimally due to the fact that the thickness of the blocking dielectric layer 219 is too thin; when the thickness of the blocking dielectric layer 219 is greater than 1500 angstroms, BV-Rsp of the low withstand voltage device may not be optimized because the thickness of the blocking dielectric layer 219 is too thick.
In this embodiment, the second sidewall 214 also covers a portion of the top surface of the gate structure 203, so as to prevent the source/drain doped region 215 from entering the surface of the drift region 202 on the side surface of the gate structure 205.
In this embodiment, the method further includes: a first conductive plug 223 located on the blocking dielectric layer 219.
In this embodiment, the semiconductor device further includes a body region 210 located in the drift region 202, the body region 210 is located in the drift region 202 between adjacent gate structures 203, and the source-drain doped region 215 adjacent to the gate structure 203 is located in the body region 210.
In this embodiment, a heavily doped region 218 is further included in the body region 210, and the heavily doped region 218 is located between the adjacent source and drain doped regions 210.
In the present embodiment, the heavily doped region 218 is located between the source regions of the adjacent source and drain doped regions 210.
In this embodiment, a metal silicide layer 220 is further included in the top portion of the gate structure 203, the source-drain doped region 215, and the heavily doped region 218.
In this embodiment, the second sidewall 214 on the surface of the drift region 202 and the blocking dielectric layer 219 on the second sidewall 214 are simultaneously used as field plate dielectric layers, the formed first conductive plug 223 is used as a field plate conductive electrode, and the metal layer 226 is connected to the gate structure 203 or the source region in the source/drain doped region 215 to form a field plate for assisting depletion of the drift region, at this time, because the thickness of the dielectric layer under the bottom metal in the first conductive plug 223 is increased, the electric field generated during breakdown is decreased, which does not easily reach the critical voltage of the semiconductor device, so that the field of breakdown is not easily reached, and the formed semiconductor device has higher overall performance of Breakdown Voltage (BV).
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A semiconductor device, comprising:
a substrate having a drift region therein;
a plurality of gate structures located on the drift region, the gate structures including opposing first and second sidewalls;
the first side wall is positioned on the surface of the first side wall;
the second side wall is positioned on the surface of the second side wall, and the second side wall is also positioned on part of the surface of the drift region;
source-drain doped regions respectively located on two sides of the gate structure, the first side wall and the second side wall;
and the blocking dielectric layer is positioned on the surface of the second side wall.
2. The semiconductor device of claim 1, wherein the material of the barrier dielectric layer is silicon oxide.
3. The semiconductor device of claim 1, wherein the second sidewall spacers are 300 a to 2000 a thick.
4. The semiconductor device of claim 1, wherein the barrier dielectric layer has a thickness of 300 to 1500 angstroms.
5. The semiconductor device of claim 1, wherein the second sidewall further covers a portion of a top surface of the gate structure.
6. The semiconductor device according to claim 1, further comprising: and the first conductive plug is positioned on the blocking medium layer.
7. The semiconductor device of claim 1, further comprising a body region located within said drift region, said body region located within said drift region between adjacent said gate structures, said source drain doped region adjacent said gate structures located within said body region.
8. The semiconductor device of claim 7, further comprising a heavily doped region within the body region, the heavily doped region being located between adjacent source and drain doped regions.
9. The semiconductor device of claim 8, further comprising a metal suicide layer located within a top portion of the gate structure, within the source drain doped region, and within the heavily doped region.
10. A method of forming a semiconductor device, comprising the steps of:
providing a substrate;
forming a drift region in the substrate;
forming a plurality of gate structures on the drift region, wherein each gate structure comprises a first side wall and a second side wall which are opposite;
forming a first side wall on the first side wall, and forming a second side wall on the second side wall and part of the surface of the drift region;
forming source-drain doping on two sides of the gate structure, the first side wall and the second side wall;
and forming a barrier dielectric layer on the surface of the second side wall.
11. The method for forming a semiconductor device according to claim 10, wherein a material of the barrier dielectric layer is silicon oxide.
12. The method for forming the semiconductor device according to claim 10, wherein the second side walls have a thickness of 300 to 2000 angstroms.
13. The method for forming a semiconductor device according to claim 10, wherein the thickness of the barrier dielectric layer is 300 to 1500 angstroms.
14. The method for forming the semiconductor device according to claim 10, wherein the step of forming the first side wall and the second side wall comprises:
forming an initial sidewall layer on the substrate, on the drift region, on a top surface of the gate structure, on the first sidewall, and on the second sidewall;
and etching the initial side wall layer by taking the first patterning layer as a mask on the initial side wall layer, forming a first side wall on the first side wall, forming a second side wall on the second side wall and part of the surface of the drift region, and covering part of the top surface of the gate structure by the second side wall.
15. The method for forming the semiconductor device according to claim 14, further comprising, before forming the first side wall and the second side wall:
forming a sacrificial layer on the substrate, wherein the sacrificial layer is internally provided with a first opening, and the bottom of the first opening exposes the surface of the drift region between the adjacent gate structures;
carrying out ion doping on the exposed drift region to form a body region;
and removing the sacrificial layer.
16. The method for forming the semiconductor device according to claim 15, wherein the step of forming the source-drain doped regions on the two sides of the gate structure, the first side wall and the second side wall comprises:
and doping the drift regions on two sides of the first side wall and the second side wall to form the source-drain doped region.
17. The method for forming a semiconductor device according to claim 16, further comprising:
removing the first patterning layer to form a second patterning layer, wherein a second opening is formed in the second patterning layer, and the bottom of the second opening exposes the surface of the initial side wall layer between the adjacent source drain doping regions;
etching the initial side wall layer by taking the second patterning layer as a mask until the bottom of the second opening exposes the body region between the adjacent source drain doped regions;
and carrying out ion doping on the exposed body region to form a heavily doped region.
18. The method for forming a semiconductor device according to claim 17, further comprising:
removing the second patterned layer, and forming an initial blocking dielectric layer on the substrate to cover the gate structure, the drift region, the first side wall and the second side wall;
and selectively etching the initial barrier dielectric layer to form a barrier dielectric layer on the surface of the second side wall.
19. The method for forming a semiconductor device according to claim 18, further comprising: and forming a first conductive plug on the blocking medium layer.
20. The method of forming a semiconductor device of claim 18, further comprising a metal suicide layer within a top portion of the gate structure, within the source drain doped region, and within the heavily doped region.
CN202111562643.1A 2021-12-20 2021-12-20 Semiconductor device and method of forming the same Pending CN114256329A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115497830A (en) * 2022-11-21 2022-12-20 广州粤芯半导体技术有限公司 Method for manufacturing semiconductor device and semiconductor device
CN117316767A (en) * 2023-11-29 2023-12-29 英诺赛科(苏州)半导体有限公司 Semiconductor device and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115497830A (en) * 2022-11-21 2022-12-20 广州粤芯半导体技术有限公司 Method for manufacturing semiconductor device and semiconductor device
CN117316767A (en) * 2023-11-29 2023-12-29 英诺赛科(苏州)半导体有限公司 Semiconductor device and preparation method thereof
CN117316767B (en) * 2023-11-29 2024-02-13 英诺赛科(苏州)半导体有限公司 Semiconductor device and preparation method thereof

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