CN111916399B - Preparation method of semiconductor device and semiconductor device - Google Patents
Preparation method of semiconductor device and semiconductor device Download PDFInfo
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- CN111916399B CN111916399B CN202010807724.2A CN202010807724A CN111916399B CN 111916399 B CN111916399 B CN 111916399B CN 202010807724 A CN202010807724 A CN 202010807724A CN 111916399 B CN111916399 B CN 111916399B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
Abstract
The invention discloses a semiconductor device and a preparation method thereof.A semiconductor layer with a first thickness is formed on a substrate comprising a first circuit area and a second circuit area, ion doping of two different conductivity types is carried out on the semiconductor layer, and then the first doped area and the second doped area formed after doping are synchronously thinned, so that the semiconductor layer can reach the preset thickness for forming a first semiconductor structure positioned in the first circuit area and a second semiconductor structure positioned in the second circuit area, and the preset thickness can be the thickness capable of effectively reducing a capacitance barrier and meeting small-size setting.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
In order to meet the miniaturization of integrated circuits, the size of semiconductor devices in integrated circuits is continuously reduced in the prior art. In the semiconductor device shrinking process, taking a Dynamic Random Access Memory (DRAM) as an example, the device performance of the DRAM needs to be ensured.
For a bit line structure composed of polysilicon or metal in a DRAM, in the prior art, in order to reduce a capacitance barrier of a bit line, a means of reducing a thickness of the polysilicon layer is generally used to reduce the capacitance barrier, and the reduction of the thickness of the polysilicon layer in the bit line structure easily causes permeation of dopant ions in a process of doping the polysilicon layer, which causes leakage current to affect device performance.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: how to reduce the electric leakage of the semiconductor device and improve the performance of the semiconductor device while reducing the capacitance barrier.
In order to solve the above technical problem, an aspect of the present application provides a method for manufacturing a semiconductor device, including:
forming a semiconductor layer with a first thickness on a substrate, wherein the substrate comprises a first circuit area and a second circuit area;
performing first ion doping on a part of the semiconductor layer above the first circuit region to form a first doped region in the semiconductor layer;
performing second ion doping on the rest part of the semiconductor layer except the first doped region to form a second doped region, wherein the second doped region is different from the first doped region in conductivity type;
synchronously thinning the first doped region and the second doped region to enable the semiconductor layer to reach a preset thickness;
forming a barrier layer, a metal layer and a mask layer on the semiconductor layer in sequence;
and patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer to form a first semiconductor structure in the first circuit region and a second semiconductor structure in the second circuit region.
Optionally, forming the semiconductor layer of the first thickness on the substrate includes:
forming a first insulating dielectric layer on the substrate;
and forming a polysilicon layer on the first insulating dielectric layer.
Optionally, performing first ion doping on a portion of the semiconductor layer located above the first circuit region, and/or performing second ion doping on the remaining portion of the semiconductor layer except for the first doped region, includes:
and performing first ion doping on the part of the semiconductor layer above the first circuit region by adopting an ion implantation process or a diffusion process, and/or performing second ion doping on the rest part of the semiconductor layer except the first doped region.
Optionally, performing first ion doping on a portion of the semiconductor layer located above the first circuit region, including: carrying out P-type doping on a part of the semiconductor layer above the first circuit region by adopting boron doping agent;
and carrying out second ion doping on the rest part of the semiconductor layer except the first doped region, wherein the second ion doping comprises the following steps: and carrying out N-type doping on the rest part of the semiconductor layer except the first doping region by adopting one dopant of phosphorus, arsenic, antimony and bismuth.
Optionally, the step of thinning the first doped region and the second doped region synchronously to make the semiconductor layer reach a predetermined thickness includes:
and synchronously thinning the first doped region and the second doped region to enable the semiconductor layer of the first doped region to reach a second thickness and the semiconductor layer of the second doped region to reach a third thickness, wherein the semiconductor layer of the second thickness and the semiconductor layer of the third thickness are not equal in thickness.
Optionally, the step of thinning the first doped region and the second doped region synchronously to make the semiconductor layer reach a predetermined thickness includes: and synchronously thinning the first doped region and the second doped region by utilizing an inductively coupled plasma etching technology so as to enable the semiconductor layer to reach a preset thickness.
Optionally, the first circuit region includes a peripheral circuit region, and the second circuit region includes a cell array region;
patterning the mask layer, the metal layer, the barrier layer, and the semiconductor layer to form a first semiconductor structure in the first circuit region and a second semiconductor structure in the second circuit region, including: and patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer to form a gate structure in the peripheral circuit region and a bit line structure in the cell array region.
Optionally, patterning the mask layer, the metal layer, the barrier layer, and the semiconductor layer to form a gate structure in the peripheral circuit region, and forming a bit line structure in the cell array region, includes:
patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer in the peripheral circuit region to form a gate structure in the peripheral circuit region;
and patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer of the second doping region of the cell array region to form a bit line structure in the cell array region.
Optionally, the semiconductor device manufacturing method further includes:
and forming a bit line contact plug in the substrate, wherein the bit line contact plug is positioned below a preset position of part of the bit line structure.
Another aspect of the present application provides a semiconductor device, which is manufactured by applying the semiconductor device manufacturing method described above, including:
a substrate, wherein the substrate includes a first circuit region and a second circuit region;
a first semiconductor structure located over the first circuit region, wherein the first semiconductor structure includes a semiconductor layer, a barrier layer located on the semiconductor layer, a metal layer located on the barrier layer, and a mask layer located on the metal layer;
and the second semiconductor structure is positioned in the second circuit area and comprises a semiconductor layer, a barrier layer positioned on the semiconductor, a metal layer positioned on the barrier layer and a mask layer positioned on the metal layer.
Optionally, the first circuit region includes a peripheral circuit region, and the first semiconductor structure located above the first circuit region includes: a gate structure over the peripheral circuit region;
the second circuit region includes a cell array region, a second semiconductor structure located in the second circuit region, including: a bit line structure located in the cell array region.
Optionally, the semiconductor device further includes a bit line contact plug located in the substrate and contacting a portion of the bottom of the bit line structure.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
by applying the semiconductor device manufacturing method and the semiconductor device provided by the application, the semiconductor layer with the first thickness is formed on the substrate, the first ion doping is carried out on part of the semiconductor layer positioned in the first circuit region to form the first doping region, and the second ion doping is carried out on the rest part of the semiconductor layer except the first doping region to form the second doping region with the conductivity type different from that of the first doping region. And then synchronously thinning the first doped region and the second doped region to enable the semiconductor layer to reach the preset thickness. And finally, sequentially forming a barrier layer, a metal layer and a mask layer on the semiconductor layer, and patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer to form a first semiconductor structure in the first circuit region and a second semiconductor structure in the second circuit region. The semiconductor device comprises a semiconductor layer, a first doped region and a second doped region, wherein the semiconductor layer is formed by first forming the semiconductor layer with first thickness, doping of two different conductive types is carried out on the semiconductor layer, and then the first doped region and the second doped region formed after doping are thinned synchronously, so that the semiconductor layer can reach preset thickness, the preset thickness can effectively reduce a capacitance barrier and meet the thickness set in a small size, therefore, the process of thinning after doping can meet the setting in a small size and reduce the capacitance barrier, doped ion permeation can be avoided, and the performance of the semiconductor device is effectively improved.
Drawings
The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. Wherein the included drawings are:
fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 2(1) to fig. 2(7) are schematic cross-sectional structural diagrams illustrating a semiconductor device manufacturing process according to an embodiment of the present disclosure;
fig. 3 is a schematic flow chart illustrating a manufacturing method of a semiconductor device according to a second embodiment of the present application;
fig. 4(1) to 4(8) are schematic cross-sectional structure diagrams illustrating a semiconductor device manufacturing process according to a second embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following will describe in detail an implementation method of the present invention with reference to the accompanying drawings and embodiments, so that how to apply technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.
In order to meet the miniaturization of integrated circuits, the size of semiconductor devices in integrated circuits is continuously reduced in the prior art. In the semiconductor device shrinking process, taking a Dynamic Random Access Memory (DRAM) as an example, the device performance of the DRAM needs to be ensured.
For a bit line structure composed of polysilicon or metal in a DRAM, in the prior art, in order to reduce a capacitance barrier of a bit line, a means of reducing a thickness of the polysilicon layer is generally used to reduce the capacitance barrier, and the reduction of the thickness of the polysilicon layer in the bit line structure easily causes permeation of dopant ions in a process of doping the polysilicon layer, which causes leakage current to affect device performance.
In view of this, the present application provides a method for manufacturing a semiconductor device and a semiconductor device, in which a semiconductor layer with a first thickness is formed on a substrate, a portion of the semiconductor layer located in a first circuit region is subjected to a first ion doping process to form a first doped region, and the remaining portion of the semiconductor layer except the first doped region is subjected to a second ion doping process to form a second doped region with a conductivity type different from that of the first doped region. And then synchronously thinning the first doped region and the second doped region to enable the semiconductor layer to reach the preset thickness. And finally, sequentially forming a barrier layer, a metal layer and a mask layer on the semiconductor layer, and patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer to form a first semiconductor structure in the first circuit region and a second semiconductor structure in the second circuit region. The semiconductor device comprises a semiconductor layer, a first doped region and a second doped region, wherein the semiconductor layer is formed by first forming the semiconductor layer with first thickness, doping of two different conductive types is carried out on the semiconductor layer, and then the first doped region and the second doped region formed after doping are thinned synchronously, so that the semiconductor layer can reach preset thickness, the preset thickness can effectively reduce a capacitance barrier and meet the thickness set in a small size, therefore, the process of thinning after doping can meet the setting in a small size and reduce the capacitance barrier, doped ion permeation can be avoided, and the performance of the semiconductor device is effectively improved.
Example one
Referring to fig. 1, fig. 1 shows a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application, which includes steps S101 to S106; fig. 2(1) to fig. 2(7) are schematic cross-sectional structural diagrams illustrating a semiconductor device manufacturing process according to an embodiment of the present application:
step S101: a semiconductor layer 12 with a first thickness is formed on a substrate 11, wherein the substrate 11 includes a first circuit region and a second circuit region, as shown in fig. 2 (1).
Step S102: first ion doping is performed on a portion of the semiconductor layer 12 located above the first circuit region to form a first doped region 121 in the semiconductor layer 12, as shown in fig. 2 (2).
Step S103: the remaining portion of the semiconductor layer 12 except the first doped region 121 is doped with second ions to form a second doped region 122, wherein the second doped region 122 has a different conductivity type from the first doped region 121, as shown in fig. 2 (2).
Step S104: the first doped region 121 and the second doped region 122 are thinned synchronously to make the semiconductor layer reach a predetermined thickness, as shown in fig. 2 (3).
Step S105: a barrier layer 14, a metal layer 15 and a mask layer 16 are sequentially formed on the semiconductor layer, see fig. 2 (4).
Step S106: the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer are patterned to form a first semiconductor structure in the first circuit region and a second semiconductor structure in the second circuit region, as shown in fig. 2(5) to fig. 2 (7).
In the embodiment of the present application, the first circuit region may be a peripheral circuit region or a cell array region, and the first circuit region may be the same as or different from the second circuit region. As an example, the first circuit region may be a peripheral circuit region, the second circuit region may be a cell array region, and the patterning of the mask layer, the metal layer, the barrier layer, and the semiconductor layer to form the first semiconductor structure in the first circuit region and the second semiconductor structure in the second circuit region may include: and patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer to form a gate structure in the peripheral circuit region and form a bit line structure BL in the cell array region.
It should be noted that the gate structure formed in the peripheral circuit region may form a transistor structure with the source/drain regions in the substrate located at both sides of the gate structure, where a portion of the semiconductor layer of the gate structure is formed by the semiconductor layer of the first doped region, and the remaining semiconductor layer of the gate structure is formed by the semiconductor layer of the second doped region. The cell array region may include a word line structure in addition to the bit line structure.
In the embodiment of the present application, a method for manufacturing a semiconductor device and a semiconductor device provided by the present application will be described by taking, as an example, a first circuit region as a peripheral circuit region, where a gate structure is formed, and a second circuit region as a cell array region, where a bit line structure is formed.
In step S101, a semiconductor layer 12 of a first thickness may be formed on the substrate 11 using an atomic layer deposition process or a chemical vapor deposition process.
The base 11 may include a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the substrate 11 may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like.
The semiconductor layer 12 may be provided as amorphous silicon or a polysilicon layer, and in the embodiment of the present application, the polysilicon layer will be used as the semiconductor layer 12.
In addition, when the semiconductor layer 12 of the first thickness is formed on the substrate 11, the first thickness is set to be thicker than a predetermined thickness in order to increase the concentration of ions doped in the semiconductor layer 12 and to avoid penetration of the doped ions.
Note that, a first insulating medium layer 13 is further provided between the semiconductor layer 12 and the substrate 11, and as an example, forming the semiconductor layer 12 with a first thickness on the substrate 11 may include:
the method comprises the following steps: a first insulating dielectric layer 13 is formed on the substrate 11.
Step two: a polysilicon layer is formed on the first insulating dielectric layer 13.
The first insulating medium layer 13 may include: borophosphosilicate glass, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, carbon-containing low dielectric constant dielectrics, and the like.
In the embodiment of the present application, when a silicon substrate is used as the base 11, silicon dioxide may be formed as the first insulating medium layer 13 by thermally oxidizing the silicon substrate, or the first insulating medium layer 13 may be deposited on the base 11 by physical vapor deposition or chemical vapor deposition.
Forming the polysilicon layer on the first insulating dielectric layer 13 may form a polysilicon layer of a first thickness on the substrate 11 using an atomic layer deposition process or a chemical vapor deposition process.
In step S102, a portion of the semiconductor layer 12 located above the peripheral circuit region is subjected to first ion doping, and/or, in step S103, the remaining portion of the semiconductor layer 12 except for the first doping region 121 is subjected to second ion doping, which includes:
an ion implantation process or a diffusion process is used to perform a first ion doping on a portion of the semiconductor layer 12 located above the peripheral circuit region, and/or a second ion doping is performed on the remaining portion of the semiconductor layer 12 except for the first doped region 121.
It should be noted that, in the embodiment of the present application, the first ion doping and the second ion doping may be performed simultaneously, or the first ion doping and the second ion doping may be performed separately, and when the doping is performed separately, the order of performing the first ion doping and the second ion doping is not limited.
As an example, the first ion doping of the portion of the semiconductor layer 12 located above the peripheral circuit region may include: a portion of the semiconductor layer 12 located above the peripheral circuit region is P-doped with a boron dopant, and a first doped region 121 is formed in the P-doped semiconductor layer 12.
As an example, the second ion doping is performed on the remaining portion of the semiconductor layer 12 except for the first doped region 121, including: and doping the rest part of the semiconductor layer 12 except the first doping region 121 with one dopant of phosphorus, arsenic, antimony and bismuth in an N-type manner, and forming a second doping region 122 in the N-type doped semiconductor layer 12.
By ion doping the semiconductor layer 12 with the first thickness, the thickness of the semiconductor layer in the corresponding structure is thicker than that of the semiconductor layer in the subsequent process when a transistor structure or a bit line structure is formed, so that when the semiconductor layer 12 with the first thickness is doped, the penetration of doped ions can be effectively avoided, and meanwhile, the doping concentration can be improved, and the conductivity of the device can be improved.
In step S104, thinning the first doped region 121 and the second doped region 122 synchronously to make the semiconductor layer reach a predetermined thickness includes: the first doped region 121 and the second doped region 122 are thinned synchronously by using an inductively coupled plasma etching technique to make the semiconductor layer reach a predetermined thickness.
In the embodiment of the present application, the conductivity types of the first doped region 121 and the second doped region 122 are different, so that in the process of performing the synchronous thinning by using the etching technique, the etching rates of the first doped region 121 and the second doped region 122 are different, so that the thicknesses of the first doped region 121 and the second doped region 122 after the synchronous thinning are different. As an example, the first doping region 121 and the second doping region 122 are thinned synchronously, so that the semiconductor layer of the first doping region 121 reaches a second thickness, and the semiconductor layer of the second doping region 122 reaches a third thickness, wherein the semiconductor layer 121 'of the second thickness and the semiconductor layer 122' of the third thickness are not equal in thickness.
In step S105, the barrier layer 14, the metal layer 15, and the mask layer 16 may be sequentially deposited on the semiconductor layer using an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.
The barrier layer 14 may include a metal silicide layer, such as tungsten silicide, the metal layer 15 may include tungsten metal, and the mask layer 16 may include an insulating material such as silicon nitride or silicon oxynitride.
Step S106 may specifically be:
patterning the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer 121' in the peripheral circuit region to form a transistor structure in the peripheral circuit region;
the mask layer 16, the metal layer 15, the barrier layer 14, and the semiconductor layer 122' of the second doping region 122 of the cell array region are patterned to form a bit line structure BL in the cell array region.
It should be noted that, in the embodiment of the present application, both the first doped region 121 and the second doped region 122 are formed in the semiconductor layer of the peripheral circuit region, and the transistor structure formed in the peripheral circuit region may be that transistors are respectively formed on the basis of the semiconductor layer 121 'of the first doped region 121 and the semiconductor layer 122' of the second doped region 122 of the peripheral circuit, and as an example, the transistors formed on the basis of the semiconductor layer 121 'of the first doped region 121 and the transistors formed on the basis of the semiconductor layer 122' of the second doped region 122 are arranged at intervals.
As an example, the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer of the patterned peripheral circuit region and the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer 122' of the patterned cell array region may be formed by forming a patterned photoresist 17 on the mask layer 16, wherein the patterned photoresist 17 covers the mask layer 16 of the region corresponding to the transistor gate structure G to be formed and the mask layer 16 of the region corresponding to the bit line structure to be formed, as shown in fig. 2 (5). Using the patterned photoresist 17 as a mask, the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer exposed in the peripheral circuit region are etched to form a plurality of gate structures in the peripheral circuit region, as shown in fig. 2 (6). Further, a sidewall (not shown in the figure) may be formed on the gate structure formed in the peripheral circuit region, for example, an atomic layer deposition process or a chemical vapor deposition process may be used to deposit an insulating layer covering the gate structure in the peripheral circuit region, and then an etch-back process is used to expose the upper surface of the mask layer 16 of the gate structure and the first insulating medium layer 13, so as to form the sidewall. The insulating layer material for forming the side wall may include silicon nitride, silicon oxide, silicon oxynitride, and the like. It should be noted that a source and a drain (not shown) are formed in the substrate 11 at two sides of the gate structure, and the source and the drain can be formed by a method commonly used in the art and will not be described in this application, so that a transistor structure can be formed in the peripheral circuit region. In addition, referring to fig. 2(7), the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer 122' of the second doped region 122 exposed in the cell array region are etched until the first insulating dielectric film 13 is exposed, so as to form a bit line structure. Furthermore, an insulation layer (not shown) may be deposited over the bit line structure in the cell array region to cover the sidewalls and the upper surface of the bit line structure, and the deposition method may be the same as the deposition process used to form the sidewalls of the gate structure.
In the method for manufacturing a semiconductor device according to the embodiment of the present application, the semiconductor layer 12 with the first thickness is formed on the substrate 11, the first ion doping is performed on the portion of the semiconductor layer 12 located in the peripheral circuit region to form the first doping region 121, and the second ion doping is performed on the remaining portion of the semiconductor layer 12 except the first doping region 121 to form the second doping region 122 with a conductivity type different from that of the first doping region 121. Then, the first doped region 121 and the second doped region 122 are thinned synchronously to make the semiconductor layer 12 reach a predetermined thickness. Finally, a barrier layer 14, a metal layer 15 and a mask layer 16 are sequentially formed on the semiconductor layer, and the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer are patterned to form a transistor structure in a peripheral circuit region and a bit line structure in a cell array region. The semiconductor layer 12 with the first thickness is formed firstly, the semiconductor layer 12 is doped with two different conductivity types, and then the first doped region 121 and the second doped region 122 formed after doping are thinned synchronously, so that the semiconductor layer can reach the preset thickness, the preset thickness can be the thickness capable of effectively reducing the capacitance barrier and meeting the small-size setting, therefore, the process of thinning after doping can meet the small-size setting and reduce the capacitance barrier, the permeation of doped ions can be avoided, and the performance of a semiconductor device is effectively improved.
In the embodiment of the present invention, a bit line contact plug 18' may be further formed in the substrate 11 of the cell array region, based on which another method for manufacturing a semiconductor device is provided in the embodiment of the present invention, please refer to the second embodiment.
Example two
Referring to fig. 3, fig. 3 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present application, which includes steps S201 to S207; fig. 4(1) to 4(8) are schematic cross-sectional structure diagrams illustrating a semiconductor device manufacturing process according to a second embodiment of the present application.
Step S201: a plurality of recesses are formed in the substrate 11 of the cell array region as bit line contact plug recesses 18, as shown in fig. 4 (1).
Step S202: a semiconductor material is deposited on the substrate 11 formed with the bit line contact plug recess 18 to integrally form a bit line contact plug semiconductor layer and a semiconductor layer 12' of a first thickness, as shown in fig. 4 (2).
Step S203: first ion doping is performed on a portion of the semiconductor layer located above the peripheral circuit region to form a first doped region 121 in the semiconductor layer, as shown in fig. 4 (3).
Step S204: performing second ion doping on the remaining portion of the semiconductor layer except the first doped region 121 to form a second doped region 122; the bit line contact plug semiconductor layer is doped with second ions to form a bit line contact plug 18', and the second doped region 122 has a different conductivity type from the first doped region 121, as shown in fig. 4 (3).
Step S205: the first doping region 121 and the second doping region 122 are thinned synchronously to make the semiconductor layer reach a predetermined thickness, see fig. 4 (4).
Step S206: a barrier layer 14, a metal layer 15 and a mask layer 16 are sequentially formed on the semiconductor layer, as shown in fig. 4 (5).
Step S207: the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer are patterned to form a transistor structure in the peripheral circuit region and a bit line structure BL in the cell array region, as shown in fig. 4(6) to 4 (8).
It should be noted that step S203 and step S205 to step S207 in the second embodiment of the present application are the same as step S102 and step S104 to step S106 in the first embodiment, and for brevity, detailed description is omitted here, and specific implementation manners may be referred to in the first embodiment.
As an example, in step S201, a plurality of grooves may be etched in the substrate 11 using a wet etching process or a dry etching process to form the bit line contact plug grooves 18.
In step S202, a semiconductor material may be deposited by using an atomic layer deposition process or a chemical vapor deposition process, the bit line contact plug recess 18 is filled with the semiconductor material, and the bit line contact plug semiconductor layer and the semiconductor layer 12' having the first thickness on the upper surface of the bit line contact plug semiconductor layer are integrally formed. In the embodiment of the present application, the semiconductor material may be polysilicon.
As an example, step S204 may specifically be that the first ion doping is performed on the portion of the semiconductor layer 12 located above the peripheral circuit region, and may include: a portion of the semiconductor layer 12 located above the peripheral circuit region is P-doped with a boron dopant, and a first doped region 121 is formed in the P-doped semiconductor layer 12.
When the remaining portion of the semiconductor layer 12 'except the first doped region 121 is subsequently doped with the second ions, the bit line contact plug semiconductor layer is doped by an ion implantation process or a diffusion process to form the bit line contact plug 18'. The bit line contact plugs 18' are located under the predetermined positions of the bit line structures, and can be used to make contact between the bit lines and the active regions or word lines in the substrate 11.
The remaining portions except the first doping region 121 and the bit line contact plug semiconductor layer are doped by the same process as the bit line contact plug semiconductor layer, or by a process different from the process for doping the bit line contact plug semiconductor layer.
When the second ion doping is performed, one of phosphorus, arsenic, antimony, and bismuth may be selectively used to perform N-type doping on the remaining portion of the semiconductor layer 12' excluding the first doping region 121.
By ion doping the semiconductor layer 12 'with the first thickness, the first thickness is thicker than the thickness of the semiconductor layer in the corresponding structure when a transistor structure or a bit line structure is formed in the subsequent process, so that when the semiconductor layer 12' with the first thickness is doped, the penetration of doped ions can be effectively avoided, and meanwhile, the doping concentration can be improved and the conductivity of the device can be improved.
In the above method for manufacturing a semiconductor device according to the embodiment of the present application, a plurality of recesses are formed in the substrate 11 in the cell array region to serve as the bit line contact plug recesses 18. And a bit line contact plug semiconductor layer and a semiconductor layer 12' of a first thickness are integrally formed by depositing a semiconductor material on the substrate 11 formed with the bit line contact plug recess 18. Next, a first doped region 121 is formed by performing a first ion doping on a portion of the semiconductor layer located in the peripheral circuit region, a second doped region 122 is formed by performing a second ion doping on the remaining portion of the semiconductor layer except for the first doped region 121, and a bit line contact plug 18' is formed by performing a second ion doping on the bit line contact plug semiconductor layer. Then, the first doping region 121 and the second doping region 122 are thinned synchronously to make the semiconductor layer reach a predetermined thickness. Finally, a barrier layer 14, a metal layer 15 and a mask layer 16 are sequentially formed on the semiconductor layer, and the mask layer 16, the metal layer 15, the barrier layer 14 and the semiconductor layer are patterned to form a transistor structure in a peripheral circuit region and a bit line structure in a cell array region. In this way, the semiconductor device formed in this embodiment has the beneficial effects of the first embodiment, and the bit line contact plugs are formed to realize the conductive contact between part of the bit lines and the substrate 11.
In addition, the embodiment of the present application further provides a semiconductor device manufactured by applying the above semiconductor device manufacturing method, and specifically please refer to embodiment three.
EXAMPLE III
Referring to fig. 2(7), fig. 2(7) is a schematic cross-sectional structure diagram of a semiconductor device manufactured by applying the semiconductor device manufacturing method according to the first embodiment, which includes:
a substrate 11, wherein the substrate 11 includes a cell array region and a peripheral circuit region;
a gate structure located over the peripheral circuit region, wherein the gate structure includes a semiconductor layer, a barrier layer 14 located on the semiconductor layer, a metal layer 15 located on the barrier layer 14, and a mask layer 16 located on the metal layer 15;
and a bit line structure located at the cell array region, the bit line structure including a semiconductor layer 122 ', a barrier layer 14 located on the semiconductor layer 122', a metal layer 15 located on the barrier layer 14, and a mask layer 16 located on the metal layer 15.
The base 11 may include a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the substrate 11 may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like.
The semiconductor layer may be provided as an amorphous silicon layer or a polysilicon layer, and in the embodiment of the present application, the polysilicon layer will be used as the semiconductor layer.
As an example, the gate structure over the peripheral circuit region of the substrate 11 includes a gate structure formed of the semiconductor layer 121 'of the first doping region 121 having the second thickness and a gate structure formed of the semiconductor layer 122' of the second doping region 122 having the third thickness.
The first doped region 121 and the second doped region 122 have different conductivity types, and the semiconductor layer 121 'having the second thickness and the semiconductor layer 122' having the third thickness are not equal in thickness. The first doping region 121 may be formed by doping with a boron dopant, and the second doping region 122 may be formed by doping with one of phosphorus, arsenic, antimony, and bismuth.
The barrier layer 14 may comprise a metal silicide layer, such as tungsten silicide, the metal layer 15 may comprise tungsten metal, and the mask layer 16 may comprise an insulating material such as silicon nitride or silicon oxynitride.
In the substrate 11 on both sides of the gate structure, a source and a drain (not shown) of the transistor structure are also formed, so that the transistor structure is formed in the peripheral circuit region.
In other embodiments, a sidewall spacer (not shown) may be further formed on the gate structure, and the insulating layer material forming the sidewall spacer may include silicon nitride, silicon oxide, silicon oxynitride, and the like. In addition, a first insulating dielectric layer (not shown) may be further disposed between the semiconductor layer and the substrate 11, wherein the first insulating dielectric layer may include: borophosphosilicate glass, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, carbon-containing low dielectric constant dielectrics, and the like.
As an example, the bit line structure located in the cell array region includes a semiconductor layer (122') having a second doped region 122 with a third thickness, the barrier layer 14 in the bit line structure may include a metal silicide layer, for example, tungsten silicide, the metal layer 15 may include metal tungsten, and the mask layer 16 may include an insulating material such as silicon nitride or silicon oxynitride. In the embodiment of the present application, the barrier layer 14 in the bit line structure and the barrier layer 14 in the gate structure are made of the same material, and in addition, the metal layer 15 or the mask layer 16 may also be made of the same material as the metal layer 15 or the mask layer 16 in the gate structure. As another example, an insulating layer (not shown) may be formed on the bit line structure to cover the sidewalls and the upper surface of the bit line structure.
As another example, referring to fig. 4(8), fig. 4(8) is a schematic cross-sectional structure diagram of a semiconductor device manufactured by applying the semiconductor device manufacturing method according to the second embodiment, which is different from the semiconductor device shown in fig. 2(7) mainly in that the semiconductor device further includes a bit line contact plug 18' located in the substrate 11 and contacting with a bottom of a portion of the bit line structure.
Wherein the bit line contact plug 18' and the semiconductor layer in the bit line structure are an integral structure, the bit line contact plug may be formed by second ion doping the bit line contact plug semiconductor layer. The bit line structure may be useful for making conductive contact of portions of the bit lines to the substrate 11.
In order to manufacture the semiconductor device manufactured by applying the manufacturing method of the semiconductor device provided by the embodiment of the present application, the semiconductor device includes a substrate 11, a gate structure located above a peripheral circuit region of the substrate 11, and a bit line structure located in a cell array region of the substrate 11, where the gate structure includes a semiconductor layer, a barrier layer 14 located on the semiconductor, a metal layer 15 located on the barrier layer 14, and a mask layer 16 located on the metal layer 15; the bit line structure includes a semiconductor layer 122', a barrier layer 14 on the semiconductor, a metal layer 15 on the barrier layer 14, and a mask layer 16 on the metal layer 15. The semiconductor layer with the first thickness is formed, the semiconductor layer is doped with two different conductivity types, and the first doped region 121 and the second doped region 122 formed after doping are thinned synchronously to form the semiconductor layer with the preset thickness in the gate structure and the bit line structure respectively, so that the small-size setting of the semiconductor device, the reduction of the capacitance barrier and the improvement of the conductivity are met, the penetration of doped ions can be avoided, and the performance of the semiconductor device is effectively improved.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A method for manufacturing a semiconductor device, comprising:
forming a semiconductor layer of a first thickness on a substrate, wherein the substrate includes a peripheral circuit region and a cell array region;
performing first ion doping on a part of the semiconductor layer above the peripheral circuit region to form a first doped region in the semiconductor layer;
performing second ion doping on the rest part of the semiconductor layer except the first doped region to form a second doped region, wherein the second doped region is different from the first doped region in conductivity type;
synchronously thinning the first doped region and the second doped region to enable the semiconductor layer to reach a preset thickness;
forming a barrier layer, a metal layer and a mask layer on the semiconductor layer in sequence;
and patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer to form a gate structure in the peripheral circuit region and a bit line structure in the cell array region.
2. The method of claim 1, wherein forming the semiconductor layer of the first thickness on the substrate comprises:
forming a first insulating dielectric layer on the substrate;
and forming a polysilicon layer on the first insulating dielectric layer.
3. The method as claimed in claim 2, wherein the first ion doping is performed on a portion of the semiconductor layer located above the peripheral circuit region, and/or the second ion doping is performed on a remaining portion of the semiconductor layer except for the first doped region, and the method comprises:
and performing first ion doping on the part of the semiconductor layer above the peripheral circuit region by adopting an ion implantation process or a diffusion process, and/or performing second ion doping on the rest part of the semiconductor layer except the first doped region.
4. The method as claimed in claim 3, wherein the first ion doping of the portion of the semiconductor layer located above the peripheral circuit region comprises: carrying out P-type doping on a part of the semiconductor layer above the peripheral circuit region by adopting a boron doping agent;
and carrying out second ion doping on the rest part of the semiconductor layer except the first doped region, wherein the second ion doping comprises the following steps: and carrying out N-type doping on the rest part of the semiconductor layer except the first doping region by adopting one dopant of phosphorus, arsenic, antimony and bismuth.
5. The method of claim 1, wherein the step of simultaneously thinning the first doped region and the second doped region to achieve a predetermined thickness of the semiconductor layer comprises:
and synchronously thinning the first doped region and the second doped region to enable the semiconductor layer of the first doped region to reach a second thickness and the semiconductor layer of the second doped region to reach a third thickness, wherein the semiconductor layer of the second thickness and the semiconductor layer of the third thickness are not equal in thickness.
6. The method of claim 5, wherein the step of simultaneously thinning the first doped region and the second doped region to achieve a predetermined thickness of the semiconductor layer comprises: and synchronously thinning the first doped region and the second doped region by utilizing an inductively coupled plasma etching technology so as to enable the semiconductor layer to reach a preset thickness.
7. The method of claim 1, wherein patterning the mask layer, the metal layer, the barrier layer, and the semiconductor layer to form a gate structure in the peripheral circuit region and a bit line structure in the cell array region comprises:
patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer in the peripheral circuit region to form a gate structure in the peripheral circuit region;
and patterning the mask layer, the metal layer, the barrier layer and the semiconductor layer of the second doping region of the cell array region to form a bit line structure in the cell array region.
8. The method of manufacturing according to claim 1, further comprising:
and forming a bit line contact plug in the substrate, wherein the bit line contact plug is positioned below a preset position of part of the bit line structure.
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