JPS60113471A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60113471A JPS60113471A JP22093483A JP22093483A JPS60113471A JP S60113471 A JPS60113471 A JP S60113471A JP 22093483 A JP22093483 A JP 22093483A JP 22093483 A JP22093483 A JP 22093483A JP S60113471 A JPS60113471 A JP S60113471A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- layer
- polycrystalline
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000010408 film Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 20
- 238000005530 etching Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000009940 knitting Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（発明の技術分野）
本発明は半導体装置の製造方法に関し、特にシリコンゲ
ー）ＭＯ８型電界効果トランジスタ（以下、ＭＯＳＦＥ
Ｔと記す）の多結晶シリコンゲート電極の形成方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device (silicon gate) MO8 field effect transistor (hereinafter referred to as MOSFE).
The present invention relates to a method for forming a polycrystalline silicon gate electrode (denoted as T).
（従来技術）
従来、シリコンゲー）ＭＯＳＦＥＴに於て、ゲート多結
晶シリコン電極の形成は、第１図に示す様な方法により
行なわれて来た。即ち、同図（ａ）に示す様に、フィー
ルド酸化膜２およびゲート酸化ゲート多結晶シリコン電
極形成部にフォトレジスト膜４を形成する。しかる後、
フォトレジスト膜４をマスクとして例えば異方性ドライ
エツチング等により多結晶シリコンをエッチイング除去
し、フォトレジスト膜４を除去することにより第１図俤
）のようにゲート多結晶シリコン電極３′が形成される
。(Prior Art) Conventionally, in a silicon gate MOSFET, a gate polycrystalline silicon electrode has been formed by a method as shown in FIG. That is, as shown in FIG. 4A, a photoresist film 4 is formed on the field oxide film 2 and the gate oxide gate polycrystalline silicon electrode formation portion. After that,
Using the photoresist film 4 as a mask, the polycrystalline silicon is etched away by, for example, anisotropic dry etching, and by removing the photoresist film 4, a gate polycrystalline silicon electrode 3' is formed as shown in FIG. be done.
この方法によりゲート多結晶シリコン電極３′を形成す
ると、ゲート電極３′はマスクの精度、リソグラフィー
の精度、ニッティングの精度等の不安定要素の影響を受
けて多結晶ゲート電極の長さくＭＯＳＦＥＴのゲート長
）を均−ｊ形成することは困難である。しかも、最近の
微細化に伴（・ＭＯＳＦＥＴのゲート長が短かくなり均
一に形成することがＬＳＩにとって必須であり、上記３
つの条件は製造プロセス上増々重要な要素をなって来て
いる。When the gate polycrystalline silicon electrode 3' is formed by this method, the gate electrode 3' is affected by unstable factors such as mask accuracy, lithography accuracy, knitting accuracy, etc. It is difficult to form a gate with a uniform gate length. Moreover, with recent miniaturization (・MOSFET gate length has become shorter, uniform formation is essential for LSIs, and the above three
These conditions are becoming increasingly important factors in the manufacturing process.
（発明の目的）
本発明の目的は素子の微細化に対応出来る多結晶シリコ
ンゲート電極の形成方法を提供するものである。(Object of the Invention) An object of the present invention is to provide a method for forming a polycrystalline silicon gate electrode that is compatible with miniaturization of devices.
（発明の構成）
本発明は、異方性ドライエツチングを利用してシリコン
ゲート層を選択的に形成することを特徴とする。(Structure of the Invention) The present invention is characterized in that a silicon gate layer is selectively formed using anisotropic dry etching.
（実施例）
以下、実施例を図面で詳述すると、第２図（ａ）〜（ｄ
）は本発明の一実施例であり、まず、同図（ａ）の様に
半導体基板１に例えば選択酸化等により素子分離用のフ
ィールド酸化膜層２を形成し、素子領域に例えば熱酸化
等によりゲート酸化膜層６を形成する。しかる後、ゲー
ト酸化膜６上でその一端が終端するような形状をした例
えばＣＶＤ酸化膜層５を形成する。次に、同図（ｂ）の
様に周知の方法により多結晶シリコン層３を全面に形成
する。次に同図（Ｃ）の様に例えば異方性ドライエツチ
ング等により、多結晶シリコンをニッティングする。こ
のとき、酸化膜５の上表面上の多結晶シリコン層厚およ
び酸化膜５の終端部から所定距離はなれたところからゲ
ート酸化膜６およびフィールド酸化膜２上にある多結晶
シリコン層厚に同じであるから、伺らマスクをすること
なく異方性ドライエツチングをすれば、酸化膜５の終端
部から所定距離までのゲート酸化膜６上にのみ残る多結
晶シリコン領域３′が形成される。所定距離は多結晶３
の厚さに依存する。次に、同図（ｄ）のようにＣＶＤ酸
化膜５を除去することにより多結晶シリコンゲート電極
３′が形成される。(Example) Hereinafter, the example will be described in detail with reference to the drawings.
) is an embodiment of the present invention. First, as shown in FIG. 2(a), a field oxide film layer 2 for element isolation is formed on a semiconductor substrate 1 by, for example, selective oxidation. A gate oxide film layer 6 is formed by the following steps. Thereafter, for example, a CVD oxide film layer 5 having a shape such that one end thereof terminates on the gate oxide film 6 is formed. Next, as shown in FIG. 3B, a polycrystalline silicon layer 3 is formed on the entire surface by a well-known method. Next, as shown in FIG. 2C, the polycrystalline silicon is knitted by, for example, anisotropic dry etching. At this time, the thickness of the polycrystalline silicon layer on the upper surface of oxide film 5 is the same as the thickness of the polycrystalline silicon layer on gate oxide film 6 and field oxide film 2 from a predetermined distance away from the end of oxide film 5. Therefore, if anisotropic dry etching is performed without using a mask, a polycrystalline silicon region 3' remaining only on gate oxide film 6 up to a predetermined distance from the end of oxide film 5 is formed. The specified distance is polycrystalline 3
depends on the thickness. Next, as shown in FIG. 4(d), the CVD oxide film 5 is removed to form a polycrystalline silicon gate electrode 3'.
以上述べた様に、本発明によって形成されたゲート電極
は、マスク精度、リソグラフィー精度エツチング精度等
の影響を受けずに、多結晶シリコン層３の成長膜厚の精
度だけしか影響を受け外い。As described above, the gate electrode formed according to the present invention is not affected by mask accuracy, lithography accuracy, etching accuracy, etc., but is only affected by the accuracy of the growth thickness of polycrystalline silicon layer 3.
又、多結晶シリコン３の膜厚（・ま自由に変えられるこ
とから１つのマスクで、ゲート長を自由に制御出来、微
細化にも有効である。なお、ＣＶＤ酸化膜５に代えて、
例えばＡ−ｅ等の金属薄膜や、多結晶シリコン上を薄く
酸化したもの等、薄膜を形成出来るものであれば選択は
自由である。In addition, since the film thickness of the polycrystalline silicon 3 can be changed freely, the gate length can be controlled freely with one mask, which is effective for miniaturization.In addition, instead of the CVD oxide film 5,
For example, any material can be selected as long as a thin film can be formed, such as a metal thin film such as A-e, or a thin oxidized film on polycrystalline silicon.
第３図は本発明の他の実施例であり、第２図（ａ）乃至
（ｄ）に従って多結晶シリコンゲート層３′を形成した
後、舛酸化等によってシリコンゲート層３′の上および
側表面に酸化膜を形成し、この後、第３図に示すように
、異方性ドライエツチングによりシリコンゲート層３′
の上表面の酸化膜だけを除去し、その側表面に葭化、摸
７を残したものである。FIG. 3 shows another embodiment of the present invention, in which after a polycrystalline silicon gate layer 3' is formed according to FIGS. 2(a) to (d), the top and sides of the silicon gate layer 3' are An oxide film is formed on the surface, and then, as shown in FIG. 3, the silicon gate layer 3' is etched by anisotropic dry etching.
Only the oxide film on the top surface of the oxide film was removed, leaving the oxide film 7 on the side surface.
本構造の応用として、この後、ＭＯＳＦＥＴのソース領
域、ドレイン領域を形成し、ゲート多結晶シリコン電極
、ソース領域、ドレイン領域を高融点シリサイド化する
ことも出来る。又、薄膜層５を酸化膜層の異方性ドライ
エッチイングのエラ５−
チング速度に比べて十分に早い様な薄膜層を用いること
により、薄膜層除去の工程を力くすことも可能である。As an application of this structure, the source region and drain region of the MOSFET can be formed after this, and the gate polycrystalline silicon electrode, the source region, and the drain region can be made into high melting point silicide. Furthermore, by using a thin film layer 5 that is sufficiently faster than the etching speed of the anisotropic dry etching of the oxide film layer, it is possible to reduce the process of removing the thin film layer. .
第１図（ａ） 、 （ｂ）は従来の方法を示す工程断面
図、第２図（ａｌ乃至（ｄ）は本発明の一実施例を示す
工程断面図、第３図は本発明の他の実施例を示す断面図
である。
ｌは半導体基板、２は素子分離酸化膜、３は多結晶シリ
コン層、４はフォトレジスト膜、５は薄膜、６はゲート
酸化膜層、７は絶縁体膜をそれぞれ示す。
６−
縞２図
乙 、３′ ２FIGS. 1(a) and (b) are process sectional views showing a conventional method, FIGS. 1 is a sectional view showing an embodiment of the present invention. l is a semiconductor substrate, 2 is an element isolation oxide film, 3 is a polycrystalline silicon layer, 4 is a photoresist film, 5 is a thin film, 6 is a gate oxide film layer, and 7 is an insulator. The membranes are shown respectively. 6- Stripes 2, 3' 2
Claims (1)
端が前記ゲート絶縁膜上に終端するよう殴薄膜を形成す
る工程と、少なくとも該薄膜上および前記ゲート絶縁膜
上に多結晶半導体層を形成する工程と、異方性ドライエ
ツチングにより前記多結を形成する工程とを有すること
を特徴とする半導体装置の製造方法。forming a gate insulating film on a semiconductor substrate; forming a punched thin film such that one end thereof terminates on the gate insulating film; and forming a polycrystalline semiconductor layer at least on the thin film and on the gate insulating film. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming the multilayer structure by anisotropic dry etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22093483A JPS60113471A (en) | 1983-11-24 | 1983-11-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22093483A JPS60113471A (en) | 1983-11-24 | 1983-11-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60113471A true JPS60113471A (en) | 1985-06-19 |
Family
ID=16758842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22093483A Pending JPS60113471A (en) | 1983-11-24 | 1983-11-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60113471A (en) |
-
1983
- 1983-11-24 JP JP22093483A patent/JPS60113471A/en active Pending
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