JPH0513436A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make smaller natural oxide film to be formed on the bottom of a contact hole, thereby enabling a contact hole having smaller aperture area in lower contact resistance to be made in relation to the structure of the contact hole for making an ohmic connection. CONSTITUTION:The title semiconductor device containing a MOS field effect transistor composed of a gate region 2 provided on a substrate 1 (100), a source region 3 and a drain region 4 with an oblique surface 5 (111) formed on the surface at least in one region and a contact hole 7 made in the substrate 1 using at least a part of the oblique surface 5 as an ohmic connection surface 6 as well as formed in the substrate 1 in the surface direction obliquely intersecting with the oblique surface 5 (111) is characterized in that the oblique surface 5 (111) formed on the surface of the substrate 1 (100) is an ohmic connection surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device, and more particularly to a structure of a contact hole for making ohmic connection.

When a semiconductor element is reduced and miniaturized by using the scaling rule as a guide, it is necessary to reduce the contact resistance per opening area of the contact hole in order to miniaturize the contact hole according to the scaling rule.

Therefore, there is a demand for a contact hole which can realize ohmic connection with low contact resistance.

[0004]

2. Description of the Related Art It is known that when a contact hole is opened in the manufacture of a semiconductor device, a natural oxide film is formed on the surface of an impurity region exposed at the bottom of the contact hole to increase the contact resistance.

Therefore, a method has been devised to reduce the contact resistance by removing the oxide film by hydrofluoric acid treatment and then immersing it in hot water to prevent the oxide film from being formed on the surface of the impurity region.

However, a semiconductor device is often formed on a substrate surface different from the (111) plane from the viewpoint of element characteristics or process. In such a case, the surface of the impurity region to be contacted is usually parallel to the substrate surface,
The ohmic contact surface of the contact hole provided thereon is necessarily the same crystal plane as the substrate surface.

As a result, in the conventional contact hole structure, when a semiconductor element is formed on a crystal plane that is easily oxidized,
For example, in the case of a MOSFET formed on the (100) plane, the prevention of oxidation of the ohmic contact surface does not always have a sufficient effect.

[0008]

As described above, the conventional contact hole has a drawback that an oxide film is easily formed on the ohmic contact surface, resulting in an increase in contact resistance.

The present invention reduces the natural oxide film formed on the bottom surface of the opened contact hole,
An object is to provide a contact hole having a small opening area and a low contact resistance.

[0010]

In order to solve the above problems, the present invention provides at least a gate 2, a source region 3 and a drain region 4 provided on the surface of a semiconductor substrate 1 having a plane orientation (100). The surface orientation (11
MO having a source and a drain provided with the inclined surface 5 of 1) and a contact hole 7 provided on the substrate 1 in which at least a part of the inclined surface 5 is an ohmic connection surface 6.
In a semiconductor device formed on a semiconductor substrate 1 having an S field effect transistor and having a plane orientation oblique to the (111) plane, the plane orientation formed on the surface of the substrate 1 ( It is characterized in that the slope 5 of (111) is the ohmic connection surface 6.

[0011]

In the structure of the present invention, the surface orientation of the substrate 1 on which the semiconductor element is formed is on the surface of the ohmic connection region 12 which is formed of the source region 3 and the drain region 4 and the semiconductor region including them, which is to be ohmic-connected. Slopes composed of (111) planes (hereinafter referred to as (111) slopes) are formed irrespective of the
11) It is formed to include a slope as an ohmic contact surface.

Therefore, when the contact hole is formed, the (111) slope formed on the surface of the ohmic contact region 12 is exposed at the bottom of the contact hole. In a silicon or Group 3-5 compound semiconductor, the (111) plane is the crystal plane most resistant to oxidation. Therefore, the natural oxide film formed on the (111) plane has a plane orientation different from that of the (111) plane and is thinner than the natural oxide film formed on the surface of the substrate on which the semiconductor element is formed.

Therefore, in the contact hole having the (111) plane as the ohmic contact surface in this structure, the oxide film interposed in the contact surface is thin, so that low contact resistance can be realized.

Further, in the present invention, the surface on which the semiconductor element is formed and the ohmic contact surface are obliquely intersected. For this reason, regarding the contact hole provided perpendicularly to the surface on which the semiconductor element is formed, the ohmic contact surface is larger than the opening area of the contact hole. Therefore, even if the opening area of the contact hole is small, the contact area should be large. Can
The element can be miniaturized. It should be noted that it is not an essential element of the present invention that the contact hole is provided perpendicularly to the surface on which the semiconductor element is formed.

[0015]

EXAMPLES The present invention will be described in detail with reference to Examples. Figure 1
FIG. 1 is a structural diagram of the first embodiment of the present invention, and FIG.
FIG. 1B is a plan view of a MOSFET formed on a substrate having an OI (Silicon on Insulator) structure, and FIG.

The MOSFET of this embodiment is manufactured as follows. FIG. 2 is a process chart of the first embodiment, and shows a cross-sectional view of the manufacturing process of the MOSFET shown in FIG.

First, referring to FIG. 2A, on a substrate having an SOI structure in which a silicon wafer is used as a support substrate 10 and a plane orientation (100) silicon substrate 1 is provided on an oxide film 11 formed on the surface thereof. Then, a mask 13 made of a rectangular oxide film, which is wider than the gate width and is long in the <-1,1,0> direction, is formed.

Next, referring to FIG. 2B, the mask 1
3, the portion of the substrate 1 without the mask 13 is selectively etched and removed, and the substrate 1 has a mask 13 having an upper base and a wide lower base. Is molded into an obelisk shape.

This etching can be carried out using an anisotropic etchant which exposes the (111) plane, for example, an aqueous solution of potassium hydroxide and isopropyl alcohol.
Then, the mask 13 is removed, the gate oxide film is formed, the channels are formed and the drain and ions are implanted for forming the source regions 3 and 4, and the polysilicon gate is formed. Then, the insulating film 8 is deposited to form a contact hole. Hole 7a (111)
It is provided on the slope 5. The effect of the present invention can be obtained even if a part of the contact hole 7 extends over the (111) slope 5.

Then, a contact hole having the ohmic connection surface 6 as the (111) slope is formed by the wiring metal 9 formed by depositing and patterning a conductor.
In this embodiment, since the lower surface of the substrate 1 is not etched due to the oxide film 11, it is easy to form the obelisk-shaped silicon substrate 1 into a precise shape.

FIG. 3 is a process chart of the second embodiment of the present invention.
1 shows a cross section of a MOSFET formed on a silicon substrate 1. In this embodiment, the substrate is a silicon wafer which is normally used in the first embodiment.

First, referring to FIG. 3A, a mask 13 made of an oxide film is formed on a (100) silicon substrate 1 by the same method as in the first embodiment, and anisotropic etching is performed to form (100). Form an obelisk with a slope 5.

Next, referring to FIG. 3B, a MOSFET having contact holes on the (111) slope is manufactured in the same manner as in the first embodiment. This embodiment can be easily applied to a semiconductor integrated circuit using a silicon wafer.

FIG. 4 is a process chart of the third embodiment of the present invention.
6 shows a cross section of a MOSFET having another structure formed on a silicon substrate. First, referring to FIG. 4A, a mask 13 made of a rectangular oxide film long in the <-1,1,0> direction is formed on the surface of the (100) plane-oriented silicon substrate 1.

Next, using an anisotropic etchant,
Form a trapezoidal recess 14 having a (111) slope 5 and a narrow cross section at the bottom. Then, a MOSFET having a channel on the bottom surface of the depression 14 and a contact hole on the (111) slope is manufactured by the same method as in the first embodiment.

According to the present invention, since the drain region and the source region can be provided separately, the short channel effect can be reduced. FIG. 5 is a process chart of the fourth embodiment of the present invention, showing a cross section of a contact hole for making ohmic contact with a semiconductor.

This embodiment relates to the structure of a contact hole for making an ohmic contact having a low resistance, more generally. With reference to FIG. 5 (a), ohmic connection region 1 to be ohmic-connected to a part of the surface of semiconductor substrate 1
2 is formed.

Anisotropic etching using a mask 13 provided on the surface of the substrate 1 forms V-grooves or pyramidal depressions 14 of (111) plane in the ohmic contact region 12.

Next, referring to FIG. 5B, an insulating film 8 is deposited on the substrate 1 and contact holes 7 are formed on the depressions 14. According to this embodiment, a low resistance contact hole can be easily provided in a semiconductor device that requires ohmic contact.

[0030]

According to the present invention, since a low resistance contact hole can be formed without being restricted by the plane orientation of the substrate, it is possible to provide a semiconductor device having a small contact hole required area. It greatly contributes to the performance improvement of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a structural diagram of a first embodiment of the present invention.

FIG. 2 is a process chart of the first embodiment of the present invention.

FIG. 3 is a process chart of the second embodiment of the present invention.

FIG. 4 is a process chart of a third embodiment of the present invention.

FIG. 5 is a process chart of the fourth embodiment of the present invention.

[Explanation of symbols]

1 substrate 2 gates 3 Source area 4 drain region 5 slopes 6 Ohmic connection surface 7 contact holes 8 insulating film 9 metal wiring 10 Support substrate 11 Oxide film 12 Ohmic connection area 13 masks 14 hollow

Claims (2)

[Claims] 1. A gate (2) provided on a surface of a semiconductor substrate (1) having a plane orientation (100), and a source region (3).
The source and drain in which at least one of the drain and drain regions (4) is provided with a slope (5) having a plane orientation (111), and at least a part of the slope (5) is provided with an ohmic contact surface (6). A semiconductor device comprising a MOS field effect transistor having a contact hole (7) provided on the substrate (1). 2. A semiconductor device formed on a semiconductor substrate (1) having a plane orientation oblique to a (111) plane, the slope (5) having a plane orientation (111) formed on the surface of the substrate (1). ) Is an ohmic contact surface (6).