KR100274072B1 - Manufacturing method of single crystal soi wafer - Google Patents

Manufacturing method of single crystal soi wafer Download PDF

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KR100274072B1
KR100274072B1 KR1019970079358A KR19970079358A KR100274072B1 KR 100274072 B1 KR100274072 B1 KR 100274072B1 KR 1019970079358 A KR1019970079358 A KR 1019970079358A KR 19970079358 A KR19970079358 A KR 19970079358A KR 100274072 B1 KR100274072 B1 KR 100274072B1
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wafer
oxide film
silicon
silicon wafer
impurity region
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KR19990059161A (en
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박상훈
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

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Abstract

PURPOSE: A method for manufacturing a single crystal SOI wafer is provided to form a defectless SOI wafer by removing a dopant region of a wafer. CONSTITUTION: A dopant region is formed on the first silicon wafer by implanting dopant ions therein. Silicon ions are implanted into the dopant region. An epitaxial layer(30) is grown on the dopant region by using SiCl4 and hydrogen gas. The first and the second oxide layers are formed on the epitaxial layer(30) and the second silicon wafer(50), respectively. A single oxide layer is formed by adhering the first oxide layer of the first silicon wafer to the second oxide layer of the second silicon wafer(50). The dopant region is removed.

Description

단결정ＳＯＩ웨이퍼 제조방법Single Crystal SOI Wafer Manufacturing Method

본 발명은 웨이퍼(Wafer)의 제조방법에 관한 것으로, 특히, 제 1 웨이퍼의 상부면에 실리콘이온을 미리 주입하고, 에피텍셜층 및 제 1 산화막을 형성시킨 후에 또 다른 제 2 웨이퍼상에 제 2 산화막을 형성시켜 제 1 웨이퍼를 반대로 하여 제 1 산화막을 제 2 웨이퍼의 제 2 산화막에 어닐링을 결합하여 제 1 웨이퍼와 불순물영역을 제거하므로 결함이 없는 웨이퍼를 제조하도록 하는 단결정 SOI웨이퍼 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a wafer. In particular, a silicon ion is pre-injected into an upper surface of a first wafer, and an epitaxial layer and a first oxide film are formed. A method of fabricating a single crystal SOI wafer for forming a wafer free of defects by forming an oxide film and inverting the first wafer to combine the first oxide film with the second oxide film of the second wafer to remove the first wafer and the impurity region. will be.

일반적으로, 반도체장치의 종류에는 여러 가지가 있으며, 이 반도체장치 내에 형성되는 트랜지스터 및 커패시터등을 구성시키는 방법에는 다양한 제조기술이 사용되고 있으며, 최근에는 실리콘기판 상에 산화막을 입혀 전계효과를 내도록 하는 모스형 전계효과 트랜지스터(MOSFET; metal oxide semiconductor field effect transistor)를 점차적으로 많이 사용하고 있는 실정에 있다.In general, there are various kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors, capacitors, etc. formed in the semiconductor device, and in recent years, MOS is formed by applying an oxide film on a silicon substrate to produce an electric field effect. Background Art [0002] Metal oxide semiconductor field effect transistors (MOSFETs) are increasingly used.

상기한 트랜지스터를 만들기 위하여서는 유리천이나 종이 기재, 에폭시수지 적층판등에 동박을 입히고, 동박의 불필요한 부분을 에칭하여 전자회로를 만들기 의한 실리콘웨이퍼가 사용되고 있으며, 이 실리콘웨이퍼는 원형의 웨이퍼를 다이아몬드커터 혹은 레이저로 절단하여 사각형상의 칩의 형태로 만들어 사용하게 된다. 이와 같이, 트랜지터에는 여러 가지 종류의 웨이퍼가 사용되고 있으며, 이 중에 단결정 SOI(Silicon-on-insulation)웨이퍼는 절연된 실리콘기판 상에 에피텍셜층을 형성하여 제조되는 것으로서, 소자의 기생접합용량(Parasitic junction capacitance)을 제거하기 위여 회로의 고속동작을 구현하는 데 장점을 지니고 있어서 최근에 많이 사용되고 있는 웨이퍼이다.In order to make the above-mentioned transistors, a silicon wafer is formed by coating copper foil on a glass cloth, a paper base material, an epoxy resin laminate, etc., and etching an unnecessary part of the copper foil to make an electronic circuit. The laser is cut and used in the form of a rectangular chip. As described above, various types of wafers are used in the transistor, and a single crystal silicon-on-insulation (SOI) wafer is manufactured by forming an epitaxial layer on an insulated silicon substrate. In order to eliminate parasitic junction capacitance, the wafer has been widely used in recent years because it has the advantage of realizing high-speed operation of the circuit.

이러한 SOI반도체를 제조하는 방법에는 다음의 두가지 방법이 널리 사용되고 있는 실정에 있다.The following two methods are widely used as a method for manufacturing such an SOI semiconductor.

첫번째 방법은 원하는 표면방향과 유사한 격자 변수(Lattice parameter)를 갖는 결정질의 상부에 실리콘에피텍셜층을 증착하는 것으로서, 이 방법은 통상의 실리콘 상부면에 사파이어(Al2O3)를 형성하는 방법이다.The first method is to deposit a silicon epitaxial layer on top of a crystalline having a lattice parameter similar to the desired surface orientation, which is a method of forming sapphire (Al 2 O 3 ) on a top surface of a conventional silicon. .

그리고, 두 번째 방법은 비정질의 기판 상에 다결정실리콘을 증착하고서 연속하여 증착된 박막을 재결정화시키며, 재결정화를 위한 에너지는 레이저 또는 스트립히터(Strip heater)에 의하여 제공되는 방법이다.The second method is to deposit polycrystalline silicon on an amorphous substrate and recrystallize the subsequently deposited thin film, and energy for recrystallization is provided by a laser or a strip heater.

그런데, 상기 한바와 같이, 첫 번째 방법은 기판 상에 알루미늄을 자동으로 도핑하는 것과, 열팽창 계수의부조화 및 실리콘과 절연막의 계면으로부터 길이에 아주 민감한 함수인 막결함 밀도가 좋지 않은 중요한 문제를 지니고 있으며, 두 번째 방법 역시 제조수율을 결정하는 결함 밀도가 여전히 해결되지 못하는 문제점이 있었다.However, as mentioned above, the first method has important problems of automatically doping aluminum on a substrate, poor thermal expansion coefficient, and film defect density, which is a function that is very sensitive to the length from the interface between silicon and the insulating film. The second method also had a problem that the defect density to determine the manufacturing yield was still not solved.

본 발명은 이러한 점을 감안하여 안출한 것으로서, 제 1 웨이퍼의 상부면에 실리콘이온을 미리 주입하고, 에피텍셜층 및 제 1 산화막을 형성시킨 후에 또 다른 제 2 웨이퍼상에 제 2 산화막을 형성시켜 제 1 웨이퍼를 반대로 하여 제 1 산화막을 제 2 웨이퍼의 제 2 산화막에 어닐링을 결합하여 제 1 웨이퍼와 불순물영역을 제거하므로 결함이 없는 웨이퍼를 제조하는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and in which silicon ions are pre-injected into the upper surface of the first wafer, the epitaxial layer and the first oxide film are formed, and then a second oxide film is formed on another second wafer. It is an object to manufacture a wafer free of defects because the first oxide film is annealed to the second oxide film of the second wafer with the first wafer reversed to remove the first wafer and the impurity region.

도 1 내지 도 6은 본 발명에 따른 단결정 SOI웨이퍼 제조방법을 순차적으로 예시한 도면이다.1 to 6 are views sequentially illustrating a method for manufacturing a single crystal SOI wafer according to the present invention.

-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing

10 : 제 1 웨이퍼 20 : 불순물영역10: first wafer 20: impurity region

30 : 에피텍셜층 40 : 제 1 산화막30 epitaxial layer 40 first oxide film

50 : 제 2 웨이퍼 60 : 제 2 산화막50: second wafer 60: second oxide film

70 : 산화막70: oxide film

이러한 목적은 제 1 실리콘웨이퍼 상에 소정의 불순물을 이온 주입하여 불순물영역을 형성하고, 그 불순물영역 상부에 에피텍셜층을 성장시키는 단계와; 상기 단계 후에 에피텍셜층 상부와 제 2 실리콘웨이퍼의 상에 제 1, 제 2 산화막을 형성하는 단계와; 상기 단계 후에 제 1 실리콘웨이퍼의 제 1 산화막과 제 2 실리콘웨이퍼의 제 2 산화막을 서로 맞대고서 제 1 어닐링으로 접착하여 단일화된 산화막을 형성하는 단계; 상기 단계 후에 제 1 실리콘웨이퍼와 불순물영역을 순차적으로 제거하고, 제 2 어닐링을 수행하는 단계로 이루어진 단결정 SOI웨이퍼 제조방법을 제공함으로써 달성된다.The object is to implant an impurity on the first silicon wafer to form an impurity region, and to grow an epitaxial layer on the impurity region; Forming first and second oxide films on the epitaxial layer and on the second silicon wafer after the step; After said step, bonding the first oxide film of the first silicon wafer and the second oxide film of the second silicon wafer to each other by first annealing to form a unified oxide film; After the step, the first silicon wafer and the impurity region are sequentially removed and a second annealing is performed to provide a single crystal SOI wafer manufacturing method.

그리고, 상기 불순물영역에는 실리콘이온을 주입하여 식각시에 주입되지 않은 부분보다 더 많이 식각되도록 하고, 상기 실리콘이온이 주입되는 조건은 20 ∼50KeV의 전압을 가하여 1×1012∼ 1×1015atom/㎠의 조건으로 주입하게 된다.In addition, silicon ions are implanted into the impurity region so as to be etched more than the portions not implanted at the time of etching, and the conditions under which the silicon ions are implanted are applied at a voltage of 20 to 50 KeV, thereby applying 1 × 10 12 to 1 × 10 15 atoms. It is injected under the condition of / cm 2.

또한, 상기 에피텍셜층은 SiCl4및 수소가스를 1000∼1300℃에서 반응시켜 형성하고, 상기 SiCl4를 대신하여 SiH2Cl2, SiHCl3, SiH4가스를 사용하여도 무방하다.In addition, the epitaxial layer is formed by reacting SiCl 4 and hydrogen gas at 1000 to 1300 ° C., and SiH 2 Cl 2 , SiHCl 3 , and SiH 4 gas may be used instead of SiCl 4 .

그리고, 상기 제 1 산화막 및 제 2 산화막은 오존-TEOS막 이고, 상기 제 1 어닐링은 질소분위기에서 1100∼1300℃의 온도에서 접착시키도록 한다.The first oxide film and the second oxide film are ozone-TEOS films, and the first annealing is performed at a temperature of 1100 to 1300 ° C. in a nitrogen atmosphere.

또한, 상기 불순물영역의 제거는 HF, CH3COOH 및 H2O2를 혼합한 용액을 사용하고, 이 혼합요약의 비율은 HF : CH3COOH : H2O2= 1 : 1 : 5정도로 하여 제거하도록 한다.In addition, the impurity region is removed using a mixture of HF, CH 3 COOH, and H 2 O 2 , and the ratio of the mixture summary is about HF: CH 3 COOH: H 2 O 2 = 1: 1: 5 Remove it.

이하, 첨부도면에 의거하여 본 발명에 따른 SOI웨이퍼 형성방법에 대하여 상세하게 설명하도록 한다.Hereinafter, the SOI wafer forming method according to the present invention will be described in detail with reference to the accompanying drawings.

도 1에 도시된 바와 같이, 제 1 실리콘웨이퍼(10) 상에 소정의 불순물을 이온 주입하여 불순물영역(20)을 형성하는 상태를 도시한 도면으로서, 이 불순물영역(20)에는 실리콘이온을 주입하고, 이 실리콘이온이 주입되는 조건은 20 ∼50KeV의 전압을 가하여 1×1012∼ 1×1015atom/㎠의 조건으로 주입하도록 한다.As shown in FIG. 1, a state in which an impurity region 20 is formed by ion implanting predetermined impurities onto the first silicon wafer 10 is illustrated in which silicon ions are implanted into the impurity region 20. The silicon ions are implanted under a condition of 1 × 10 12 to 1 × 10 15 atom / cm 2 by applying a voltage of 20 to 50 KeV.

이때, 실리콘이온이 주입된 불순물영역(20)은 차후에 식각할시에 불순물이 주입되지 않은 영역에 비하여 식각이 더욱 잘 이루어지게 된다.At this time, the impurity region 20 implanted with silicon ions may be etched better than the region where impurity is not implanted at the time of subsequent etching.

그리고 도 2는 상기 불순물영역(20) 상부에 에피텍셜층(30)을 성장시키는 상태를 보이고 있으며, 상기 에피텍셜층(30)은 SiCl4및 수소가스를 1000∼1300℃에서 반응시켜 형성하도록 하고, 이 SiCl4를 대신하여 SiH2Cl2, SiHCl3, SiH4가스를 사용하여도 무방하다.2 shows a state in which the epitaxial layer 30 is grown on the impurity region 20, and the epitaxial layer 30 is formed by reacting SiCl 4 and hydrogen gas at 1000 to 1300 ° C. In place of this SiCl 4 , SiH 2 Cl 2 , SiHCl 3 , or SiH 4 gas may be used.

그리고, 도 3 및 도 4는 상기 단계 후에 에피텍셜층(30) 상부와 제 2 실리콘웨이퍼(50)의 상부에 제 1, 제 2 산화막(40)(60)을 형성하는 상태를 보이고 있으며, 이 제 1 산화막(40) 및 제 2 산화막(60)은 저부에 다른 층과의 접착력과 불순물의 오염정도를 고려하여 오존-TEOS막을 사용하는 것이 바람직하다.3 and 4 show the first and second oxide films 40 and 60 formed on the epitaxial layer 30 and the second silicon wafer 50 after the step. In the first oxide film 40 and the second oxide film 60, it is preferable to use an ozone-TEOS film in consideration of adhesion to other layers and contamination of impurities.

그리고, 도 5는 상기 단계 후에 제 1 실리콘웨이퍼(10)의 제 1 산화막(40)과 제 2 실리콘웨이퍼(50)의 제 2 산화막(60)을 서로 맞대고서 제 1 어닐링으로 접착하여 단일화된 산화막(70)을 형성하는 상태를 보이고 있으며, 제 1 어닐링은 질소분위기에서 1100∼1300℃의 온도에서 제 1 산화막(40)과 제 2 산화막(60)을 완전하게 접착시켜 산화막(70)으로 전환시키도록 한다.FIG. 5 shows that the first oxide film 40 of the first silicon wafer 10 and the second oxide film 60 of the second silicon wafer 50 are bonded together with each other by first annealing after the above step, thereby unifying an oxide film. 70 shows a state in which the first annealing is completely bonded to the first oxide film 40 and the second oxide film 60 at a temperature of 1100 to 1300 ° C. in a nitrogen atmosphere, thereby converting them into the oxide film 70. To do that.

그리고, 도 6은 상기 단계 후에 제 1 실리콘웨이퍼(10)와 불순물영역(20)을 순차적으로 제거하고, 제 2 어닐링을 수행하는 상태를 도시한 도면으로서, 상기 불순물영역(20)의 제거는 HF, CH3COOH 및 H2O2를 혼합한 용액을 사용하여 이루어지고, 이 혼합요약의 비율은 HF : CH3COOH : H2O2= 1 : 1 : 5정도가 적당하고, 이 불순물영역(20)의 제거 후에 스크러버(Scrubber)장비를 사용하여 웨이퍼의 전체표면을 추가 세정하도록 하여 파트클(Particle)의 오염을 방지하게 된다.6 is a diagram illustrating a state in which the first silicon wafer 10 and the impurity region 20 are sequentially removed and the second annealing is performed after the step, and the removal of the impurity region 20 is performed by HF. , CH 3 COOH and H 2 O 2 mixed solution, the ratio of the mixture summary is HF: CH 3 COOH: H 2 O 2 = 1: 1: 5 is suitable, this impurity region ( 20) After the removal, the scrubber equipment is used to further clean the entire surface of the wafer to prevent contamination of the particles.

따라서, 상기한 바와 같이 본 발명에 따른 단결정 SOI웨이퍼 제조방법을 이용하게 되면, 제 1 웨이퍼의 상부면에 실리콘이온을 미리 주입하고, 에피텍셜층 및 제 1 산화막을 형성시킨 후에 또 다른 제 2 웨이퍼상에 제 2 산화막을 형성시켜 제 1 웨이퍼를 반대로 하여 제 1 산화막을 제 2 웨이퍼의 제 2 산화막에 어닐링을 결합하여 제 1 웨이퍼와 불순물영역을 제거하므로 결함이 없는 웨이퍼를 제조하여 불순물의 함유를 억제하므로 수율이 뛰어난 양질의 SOI웨이퍼를 제조하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, when the single crystal SOI wafer manufacturing method according to the present invention is used as described above, another second wafer is formed by injecting silicon ions into the upper surface of the first wafer in advance, and forming an epitaxial layer and a first oxide film. A second oxide film is formed on the first wafer, the first wafer is reversed, and the first oxide film is annealed to the second oxide film of the second wafer to remove the first wafer and the impurity region. Thus, a defect free wafer is produced to contain impurities. Inhibition is a very useful and effective invention for producing high quality SOI wafers with excellent yield.

Claims (4)

제 1 실리콘웨이퍼 상에 실리콘이온을 주입하여 불순물영역을 형성하고, 그 불순물영역 상부에 SiCl4및 수소가스를 1000~1300℃에서 반응시켜 에피텍셜층을 성장시키는 단계와; 상기 단계 후에 에피텍셜층 상부와 제 2 실리콘웨이퍼의 상에 오존 TEOS막인 제 1, 제 2산화막을 형성하는 단계와; 상기 단계 후에 제 1 실리콘웨이퍼의 제 1 산화막과 제 2 실리콘웨이퍼의 제 2 산화막을 서로 맞대고서 질소분위기에서 1100 ~ 1300℃의 온도에서 제 1 어닐링으로 접착하여 단일화된 산화막을 형성하는 단계; 상기 단계 후에 제 1 실리콘웨이퍼와 HF, CH3COOH 및 H2O2를 혼합한 용액을 사용하여 불순물영역을 순차적으로 제거하고, 제 2 어닐링을 수행하는 단계로 이루어진 것을 특징으로 하는 단결정 SOI웨이퍼 제조방법.Implanting silicon ions onto the first silicon wafer to form an impurity region, and growing an epitaxial layer by reacting SiCl 4 and hydrogen gas at 1000 to 1300 ° C. over the impurity region; Forming first and second oxide films, which are ozone TEOS films, on the epitaxial layer and on the second silicon wafer after the step; After the step of adhering the first oxide film of the first silicon wafer and the second oxide film of the second silicon wafer to each other by bonding the first annealing at a temperature of 1100 ~ 1300 ℃ in a nitrogen atmosphere to form a unified oxide film; After the step, using the solution of the first silicon wafer and HF, CH 3 COOH and H 2 O 2 to remove the impurity region sequentially and to perform a second annealing manufacturing single crystal SOI wafer Way. 제1항에 있어서, 상기 실리콘이온이 주입되는 조건은 20 ~ 50KeV의 전압을 가하여 1× 1012~ 1×1015atom/cm2의 조건으로 주입하는 것을 특징으로 하는 단결정 SOI웨이퍼 제조방법.The method of claim 1, wherein the silicon ion is implanted under a condition of 1 × 10 12 to 1 × 10 15 atom / cm 2 by applying a voltage of 20 to 50 KeV. 제1항에 있어서, 상기 SiCl4를 대신하여 SiH2Cl2, SiHCl3, SiH4가스중에 어느 하나의 가스를 사용하는 것을 특징으로 하는 단결정 SOI웨이퍼 제조방법.The method of claim 1, wherein any one of SiH 2 Cl 2 , SiHCl 3 , and SiH 4 gas is used in place of the SiCl 4 . 제1항에 있어서, 상기 혼합용액의 비율은 HF : CH3COOH : H2O2= 1 : 1 : 5인 것을 특징으로 하는 단결정 SOI웨이퍼 제조방법.The method of claim 1, wherein the ratio of the mixed solution is HF: CH 3 COOH: H 2 O 2 = 1: 1: 5.
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JPH06275525A (en) * 1993-03-18 1994-09-30 Shin Etsu Handotai Co Ltd Soi substrate and manufacture thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06275525A (en) * 1993-03-18 1994-09-30 Shin Etsu Handotai Co Ltd Soi substrate and manufacture thereof

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