JPH0712038B2 - Semiconductor substrate processing method - Google Patents
Semiconductor substrate processing methodInfo
- Publication number
- JPH0712038B2 JPH0712038B2 JP59088887A JP8888784A JPH0712038B2 JP H0712038 B2 JPH0712038 B2 JP H0712038B2 JP 59088887 A JP59088887 A JP 59088887A JP 8888784 A JP8888784 A JP 8888784A JP H0712038 B2 JPH0712038 B2 JP H0712038B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- rie
- treatment
- osf
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 title claims description 31
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000003672 processing method Methods 0.000 title description 2
- 238000005530 etching Methods 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000007864 aqueous solution Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 10
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 5
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 5
- 239000002344 surface layer Substances 0.000 claims description 4
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 description 39
- 229910004298 SiO 2 Inorganic materials 0.000 description 18
- 238000011109 contamination Methods 0.000 description 18
- 239000010410 layer Substances 0.000 description 18
- 230000007547 defect Effects 0.000 description 14
- 235000012431 wafers Nutrition 0.000 description 13
- 239000013078 crystal Substances 0.000 description 10
- 239000000203 mixture Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 8
- 239000010408 film Substances 0.000 description 6
- 238000002156 mixing Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 108090000368 Fibroblast growth factor 8 Proteins 0.000 description 5
- 238000009835 boiling Methods 0.000 description 5
- 102000005162 pleiotrophin Human genes 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000004381 surface treatment Methods 0.000 description 4
- 102100024155 Cadherin-11 Human genes 0.000 description 3
- 101710196878 Cadherin-11 Proteins 0.000 description 3
- 101710199268 Periostin Proteins 0.000 description 3
- 102100025368 Runt-related transcription factor 2 Human genes 0.000 description 3
- 101710102802 Runt-related transcription factor 2 Proteins 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 108010081640 osteoblast specific factor 3 Proteins 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910002796 Si–Al Inorganic materials 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体基板の処理方法に関し、プラズマエツチ
ングのようなドライエツチングによつてシリコン基板中
に生じた汚染や結晶欠陥等を除去するための表面処理に
用いて特に好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for treating a semiconductor substrate, and a surface treatment for removing contamination, crystal defects, etc. generated in a silicon substrate by dry etching such as plasma etching. It is particularly suitable for use in.
背景技術とその問題点 反応性イオンエツチング(以下、「RIE」と記す。)や
反応性又は通常のイオンミリング等による加工時に半導
体基板中に生じる放射線損傷や有機物若しくは重金属等
による汚染は、加工の異方エツチング性、材質の選択エ
ツチ性、微細加工性及び適度のプロセス速度(エツチレ
ート)確保のためには避けがたい副産物である。しか
も、上記の汚染及び放射線損傷が原因となつて、半導体
デバイスの電気的特性上、下記のような種々の好ましく
ない結果をもたらすことが一般に知られている。Background art and its problems Reactive ion etching (hereinafter referred to as "RIE"), reactive or radiation damage that occurs in a semiconductor substrate during processing by normal ion milling, or contamination by organic substances or heavy metals, etc. It is an unavoidable by-product for anisotropic etching, selection of material, etchability, fine workability and proper process speed (etching rate). Moreover, it is generally known that the above-mentioned contamination and radiation damage bring about various unfavorable results due to the electrical characteristics of the semiconductor device.
例えば、Si基板におけるSiO2薄膜のエツチングを例にと
ると、 (1) コンタクト抵抗の増大と非オーミツク化及びコン
タクト抵抗のICチツプ内及びウエハ内分布のバラツキ増
大化。例えば、AD変換器において、ICチップ内のコンタ
クト抵抗値のバラツキがAD変換器の動作特性を大きく左
右し、歩留にも影響を与える(単体のトランジスタとし
ては動作するが、ICとしては動作しない)。Taking etching of a SiO 2 thin film on a Si substrate as an example, (1) increase in contact resistance and non-ohmicity, and increase in variations in distribution of contact resistance within IC chip and within wafer. For example, in an AD converter, variations in the contact resistance value in the IC chip greatly affect the operating characteristics of the AD converter, and also affect the yield (works as a single transistor, but does not work as an IC. ).
(2) Si中のキヤリア寿命の減少。(2) Reduction of carrier life in Si.
(3) pn接合のリーク電流増大及びSiO2−Si界面電荷密
度の増大。(3) Increase of leakage current of pn junction and increase of SiO 2 -Si interface charge density.
(4) その他、Si中の欠陥等に敏感なデバイス、例えばC
CDやレーザでも、電気的活性な領域に放射線損傷や汚染
が達するような構造にして使用した場合、RIE等のエツ
チング後に何も対策をとらないと、その動作特性に影響
が出る。(4) Other devices sensitive to defects in Si, such as C
Even if a CD or laser is used with a structure in which radiation damage or contamination reaches the electrically active region, the operating characteristics will be affected if no measures are taken after etching such as RIE.
又、RIE等のドライエツチによって汚染やSi中の結晶欠
陥が生じることは、RIE後にSiを酸化して酸化誘起積層
欠陥(以下、「OSF」と記す。)を調べると、OSFが多数
発生することからも明らかである。In addition, the fact that contamination and crystal defects in Si are caused by dry etching such as RIE is that a large number of OSFs are generated when oxidation-induced stacking faults (hereinafter referred to as “OSF”) are investigated by oxidizing Si after RIE. It is also clear from.
上記の問題点を解決する手段として次のような方法が考
えられる。The following method can be considered as a means for solving the above problems.
以下、Si(多結晶Siの場合も含む。以下同じ。)基板上
にSiO2膜を形成した構造のデバイスのRIE処理を例にと
つて説明する。Hereinafter, the RIE process of a device having a structure in which a SiO 2 film is formed on a Si (including the case of polycrystalline Si; the same applies hereinafter) will be described as an example.
(A) RIE処理条件を、損傷及び汚染の少ない条件に
設定する。しかしながら、この方法では、微細加工化に
必要なエツチングの異方性、材質選択エツチ性、エツチ
ング均一性及び適度のプロセス速度を同時に満たすRIE
条件を得ることが、RIE装置の構造依存性があるもの
の、実際上困難である。(A) Set the RIE processing condition to a condition with less damage and contamination. However, with this method, an RIE that simultaneously satisfies the anisotropy of etching, material selection etching property, etching uniformity, and appropriate process speed necessary for microfabrication.
Although it depends on the structure of the RIE device, it is practically difficult to obtain the conditions.
(B) SiO2のエツチングを行う際、数100Å程度のSiO
2を残してRIE処理を止め、他の損傷及び汚染の少ないエ
ツチング方法で残りのSiO2をエツチオフする。しかしな
がら、この方法では、いかにコントロールしてウエハ内
の均一性よくSiO2を残すかという再現性、プロセス安定
性に問題がある。(B) When etching SiO 2 , SiO of several hundred Å
The RIE process is stopped by leaving 2 , and the remaining SiO 2 is etched off by another etching method with less damage and contamination. However, this method has a problem in reproducibility of how to control and leave SiO 2 in the wafer with good uniformity and process stability.
(C) SiO2とSiとの間にエツチングバツフア層を設
け、RIEによる汚染及び欠陥をこのバツフア層で吸収す
る。この方法は特定の構造の半導体デバイスに対しては
非常に有用であるが、一般的にはバツフア層の形成及び
除去等のプロセス工程の増加を招く。(C) An etching buffer layer is provided between SiO 2 and Si, and contamination and defects due to RIE are absorbed by this buffer layer. Although this method is very useful for a semiconductor device having a specific structure, it generally causes an increase in process steps such as formation and removal of a buffer layer.
発明の目的 本発明は上記の問題点に鑑みてなされたものであつて、
RIE等のドライエツチングによつてシリコン基板中に生
じた汚染や結晶欠陥等を効果的に除去することができる
ような半導体基板の処理方法を提供しようとするもので
ある。OBJECT OF THE INVENTION The present invention has been made in view of the above problems,
It is an object of the present invention to provide a method for treating a semiconductor substrate, which can effectively remove contamination, crystal defects, etc. generated in a silicon substrate by dry etching such as RIE.
発明の概要 上記の目的は本発明により次のようにして達成される。
即ち、本発明においては、ドライエッチング工程に引き
続き、シリコン基板の表面層を、アンモニア水(NH4O
H)と過酸化水素水(H2O2)とをNH4OH/H2O2=2/1〜2.9
5/0.05の割合で含有する水溶液によってシリコン基板の
表面層をエッチングにより除去する。SUMMARY OF THE INVENTION The above object is achieved by the present invention as follows.
That is, in the present invention, following the dry etching step, the surface layer of the silicon substrate is treated with ammonia water (NH 4 O
H) and hydrogen peroxide solution (H 2 O 2 ) NH 4 OH / H 2 O 2 = 2/1 to 2.9
The surface layer of the silicon substrate is removed by etching with an aqueous solution containing 5 / 0.05.
このような構成によつてシリコン基板を損傷及び汚染す
ることなくその表面をエツチングすることができる。With this structure, the surface of the silicon substrate can be etched without damaging or contaminating the silicon substrate.
実施例 本発明は次のような知見に基いてなされたものである。Example The present invention is based on the following findings.
即ち、既述したSi基板上にSiO2膜の形成された構造のデ
バイスのRIE処理において、RIEによつてSiO2を完全にエ
ツチオフした後に、下地のSi表面又はSi中に生じた汚染
及び欠陥層(〜数100Å)を、アンモニア水と過酸化水
素水との混合水溶液を昇温又は煮沸状態で用いてエツチ
オフした。この結果、SiO2の微細加工条件を満たしたま
まで、半導体デバイスの電気特性の劣化、特にコンタク
ト抵抗に関する問題を解決することができた。That is, in the RIE treatment of the device having the structure in which the SiO 2 film is formed on the Si substrate as described above, after the SiO 2 is completely etched off by the RIE, contamination and defects generated on the underlying Si surface or Si The layer (up to several hundred liters) was etched off by using a mixed aqueous solution of ammonia water and hydrogen peroxide solution at a temperature rise or boiling. As a result, it was possible to solve the problem of the deterioration of the electrical characteristics of the semiconductor device, especially the contact resistance, while the fine processing conditions of SiO 2 were being satisfied.
アンモニア水(NH4OH)と過酸化水素水(H2O2)と水(H
2O)との混合溶液を室温、昇温又は煮沸状態で用いるSi
処理はウエハの洗浄工程の1つとして一般に知られてい
る。しかしながら、この公知のSi基板処理は、例えばSi
ウエハの通常の有機物汚染や、Si粒子、ゴミ、ダスト等
のSi表面に付着したパーテイクルを除去するのが目的で
あり、酸化、蒸着、エピタキシヤル処理等の前処理とし
てのウエハ洗浄に用いられる。従つて、この洗浄でエツ
チングされるSiの量は極力少なくすることが望ましく、
通常除去されるSi深さは、数Å〜数十Å程度であり、こ
のため溶液組成も、NH4OHを少なくし、酸化作用を持つH
2O2を多くした混合比を用いる。混合比としては通常NH4
OH:H2O2:H2O=1:2:7又は=1:1:5が多く用いられる。Ammonia water (NH 4 OH), hydrogen peroxide water (H 2 O 2 ) and water (H
2 O) mixed solution with room temperature, elevated temperature or boiling
Processing is commonly known as one of the wafer cleaning steps. However, this known Si substrate processing is
The purpose is to remove the usual organic contaminants on the wafer and particles such as Si particles, dust, and dust that adhere to the Si surface, and are used for wafer cleaning as a pretreatment such as oxidation, vapor deposition, and epitaxial treatment. Therefore, it is desirable to minimize the amount of Si etched by this cleaning.
The depth of Si that is usually removed is several Å to several tens of Å. Therefore, the solution composition also reduces the amount of NH 4 OH and reduces the H
Use a mixture ratio that is high in 2 O 2 . The mixing ratio is usually NH 4
OH: H 2 O 2 : H 2 O = 1: 2: 7 or = 1: 1: 5 is often used.
本発明による半導体基板処理は、次の点で、上述した公
知のSi基板処理と明確に区別されるべきものである。The semiconductor substrate processing according to the present invention should be clearly distinguished from the above-described known Si substrate processing in the following points.
即ち、本発明の方法は、通常の有機物汚染や重金属汚染
等だけではなく、RIE等のドライエツチングによつて生
じた基板表面近傍の結晶欠陥層を除去するために積極的
にシリコン基板の表面をエツチング除去するものであ
る。このために、例えばSi基板の好ましいエツチング量
は100〜500Å程度である。このSiエツチング量は、SiO2
のRIE処理時に生じるSi中の汚染及び欠陥の深さに対応
するものであり、汚染及び欠陥層の深さは、IMMA、AE
S、RBS等の解析手段で知り得た。That is, the method of the present invention is not limited to normal organic matter contamination, heavy metal contamination, and the like, but also positively removes the surface of the silicon substrate in order to remove the crystal defect layer near the substrate surface caused by dry etching such as RIE. Etching is removed. For this reason, for example, the preferable etching amount of the Si substrate is about 100 to 500Å. This Si etching amount is SiO 2
Corresponds to the depth of contamination and defects in Si generated during the RIE process of Al.
I was able to know it by analysis means such as S and RBS.
そして、本発明においては、半導体プロセス上適当な時
間内に充分コントロール良く所定量のシリコン基板をエ
ツチング除去するために、従来公知の溶液組成と比較し
てNH4OHの混入量がH2O2のそれに対してかなり多い。即
ち、処理水溶液中のNH4OHとH2O2との比NH4OH/H2O2は2/
1〜2.95/0.05の範囲が良く、2.5/0.05/〜2.95/0.05の範
囲であるのがより好ましい。又、この処理水溶液は、室
温で用いても良いが、昇温又は煮沸状態(約75〜100
℃)で使用するのがより好ましい。Further, in the present invention, in order to etch a predetermined amount of the silicon substrate with good control within a suitable time in the semiconductor process, the mixing amount of NH 4 OH is H 2 O 2 as compared with the conventionally known solution composition. That's quite a lot. That is, the ratio NH 4 OH / H 2 O 2 of NH 4 OH and H 2 O 2 in the treated aqueous solution is 2 /
The range of 1 to 2.95 / 0.05 is preferable, and the range of 2.5 / 0.05 / to 2.95 / 0.05 is more preferable. Further, this treated aqueous solution may be used at room temperature, but it is heated or boiled (about 75 to 100).
It is more preferable to use at (° C).
以下、本発明を具体的な実験例について説明する。Hereinafter, the present invention will be described with reference to specific experimental examples.
実験例1 本発明による処理水溶液の組成とSi基板のエツチング深
さとの関係を第1図に示す。この第1図のa〜e点にお
ける水溶液組成は、夫々、NH4OH:H2O2:H2O=1:2:7
(a)、2:1:7(b)、2.5:0.5:7(c)、2.85:0.15:7
(d)、2.95:0.05:7(e)である。尚、処理水溶液は
煮沸状態でSi基板を10分間処理した。Experimental Example 1 FIG. 1 shows the relationship between the composition of the treatment aqueous solution according to the present invention and the etching depth of the Si substrate. The aqueous solution compositions at points a to e in FIG. 1 are NH 4 OH: H 2 O 2 : H 2 O = 1: 2: 7, respectively.
(A), 2: 1: 7 (b), 2.5: 0.5: 7 (c), 2.85: 0.15: 7
(D) and 2.95: 0.05: 7 (e). The treatment aqueous solution was prepared by boiling the Si substrate for 10 minutes.
一般にNH4OHはSiのエツチヤントとして働き、H2O2は酸
化作用によりSiエツチングの抑制剤として働いている。
そして、この第1図の結果から、H2Oの割合が7の場
合、充分コントロール良く、実用上問題のない時間でエ
ツチングできる処理水溶液の混合比として、NH4OH:H2O
2:H2O=2:1:7〜2.95:0.05:7の範囲であることが分る。
但し、これはH2Oの混合比が7の場合であるが、H2Oの混
合比はこれ以外でも良い。又、H2Oの混合比が7の場合
でも、NH4OH:H2O2=2:1未満の場合についても、長時間
エツチングすれば、所望(100〜500Åの範囲)のSi除去
も可能であるが、長時間エツチングする場合の欠点とし
て、煮沸して使用した場合、エツチング途中で処理水溶
液の組成が(例えば、H2O2の熱分解や各成分の蒸発によ
つて)変化して、エツチングのコントロール性に欠ける
ことがある。In general, NH 4 OH acts as an etchant for Si, and H 2 O 2 acts as an inhibitor for Si etching due to the oxidation action.
From the results shown in FIG. 1, when the ratio of H 2 O is 7, the mixture ratio of NH 4 OH: H 2 O is well controlled and the mixing ratio of the treated aqueous solution is such that etching can be performed in a time without any practical problems.
It can be seen that it is in the range of 2 : H 2 O = 2: 1: 7 to 2.95: 0.05: 7.
However, this is the case where the mixing ratio of H 2 O is 7, but the mixing ratio of H 2 O may be other than this. Even if the mixture ratio of H 2 O is 7, even if NH 4 OH: H 2 O 2 = 2: 1 or less, desired etching (100 to 500Å) of Si can be removed by etching for a long time. It is possible, but the disadvantage of etching for a long time is that when it is boiled and used, the composition of the treatment solution changes during the etching (for example, due to thermal decomposition of H 2 O 2 or evaporation of each component). Therefore, the controllability of etching may be lacking.
以上の結果から、NH4OHとH2O2との混合比はNH4OH:H2O2
=2/1〜2.95/0.05の範囲であるのが良いことが分る。From the above results, the mixing ratio of NH 4 OH and H 2 O 2 is NH 4 OH: H 2 O 2
It turns out that the range of 2/1 to 2.95 / 0.05 is good.
第2図に、P(100)ウエハ及び、イオン注入とその後
のアニールによつて形成したP+ウエハ(N(100)基板
にP+層形成:BF2 +、50KeV、5×1015cm-2)及びN+ウエ
ハ(P(100)基板にN+層形成:As+、50KeV、5×1015c
m-2)の3種類の試料をNH4OH:H2O2:H2O=2.85:0.15:7
の処理水溶液(75℃以上)で処理した時の処理時間とエ
ツチング量との関係を示す。又、上記3種類の試料をRI
Eプラズマ(CF4とH2との混合ガス使用、300W)に10分間
さらした後、上記と同様の表面処理を施した時の処理時
間と上記処理水溶液によるエツチング量との関係も示さ
れている。Second FIG, P (100) wafer and ion implantation and by the subsequent annealing connexion forming the P + wafer (N (100) substrate in the P + layer formed: BF 2 +, 50KeV, 5 × 10 15 cm - 2 ) and N + wafer (N + layer formation on P (100) substrate: As + , 50 KeV, 5 × 10 15 c
Three samples NH 4 OH in m -2): H 2 O 2 : H 2 O = 2.85: 0.15: 7
The relation between the treatment time and the etching amount when treated with the treatment aqueous solution (75 ° C or higher) is shown. In addition, RI of the above three types of samples
The relationship between the treatment time when the same surface treatment as above was applied after exposure to E plasma (using a mixed gas of CF 4 and H 2 , 300 W) for 10 minutes, and the etching amount by the above treatment solution was also shown. There is.
この結果、上記組成の水溶液によつて、SiウエハのN
型、P型、不純物濃度、RIE処理の有無(RIEによる汚染
及び欠陥の有無)に関係なく略同じ処理時間で同程度の
Si層が除去できることが分つた。As a result, the N aqueous solution of the Si wafer was
Type, P-type, impurity concentration, RIE treatment (presence or absence of RIE)
It was found that the Si layer can be removed.
NH4OH:H2O2:H2O=2.85:0.15:7の処理水溶液(煮沸状
態)でSi及びドープ処理したSiO2を10分間処理した時に
エツチングされた量を測定した結果を表1に示す。The etching amount of Si and doped SiO 2 was treated for 10 minutes in a treatment solution (boiled state) of NH 4 OH: H 2 O 2 : H 2 O = 2.85: 0.15: 7. Shown in.
この結果、層間絶縁膜としてのドープされた酸化につい
ては、アニール処理が施されていれば、本実験例の処理
水溶液によつて、例えばVLSI等に必要な微細加工条件を
充分に満たすものであることが分る。 As a result, for the doped oxidation as the interlayer insulating film, if the annealing treatment is performed, the treatment solution of the present experimental example sufficiently satisfies the fine processing conditions necessary for VLSI and the like. I understand.
尚、本実験例においては、NH4OH、H2O2、H2Oとして夫々
次のようなものを用いた。In this experimental example, NH 4 OH, H 2 O 2 and H 2 O used were as follows.
H2O :DI水、フイルターリング済 H2O2 :H2O231%含有、電子工業用 NH4OH:NH329%、特級 実験例2 Si基板上にSiO2が形成された構造の試料にRIE処理によ
つてSi中に生じたSiの結晶欠陥、若しくは以後の熱処理
で生じた、Si中に結晶欠陥を生じる核となりうる汚染が
本発明の処理によつて除去されることを調べた。Si中の
結晶欠陥は、RIE後の酸化処理によつて発生するOSFをラ
イトエツチ(Wright Etch)によって調査した。H 2 O: DI water, filtered H 2 O 2 : H 2 O 2 31% content, electronics industry NH 4 OH: NH 3 29%, special grade Experimental example 2 Structure with SiO 2 formed on Si substrate It was confirmed that the crystal defects of Si generated in Si by the RIE treatment in the sample of No. 1 or the contamination which may be nuclei causing crystal defects in Si caused by the subsequent heat treatment are removed by the treatment of the present invention. Examined. Regarding the crystal defects in Si, the OSF generated by the oxidation treatment after RIE was investigated by Wright Etch.
先ず、試料の作成方法を説明する。出発材料として8〜
12ΩcmのP(100)基板に熱酸化によつて650ÅのSiO2を
形成したもの(試料No.OSF−1)を用いた。これをRIE
処理(CF4/H2、6pa、300W)した(試料No.OSF−2)。
但し、SiO2が完全にエツチオフされ、更にSiが5分間RI
Eされるような条件(5分間オーバーエツチ条件)で行
つた。次に、ホトレジストの剥離と汚染の軽減化のため
にO2プラズマでアツシングした後、H2SO4とHNO3の混酸
煮沸後に、ライトエツチ(Light Etch)し、Si上のSiO2
(自然酸化膜)を除去した(試料No.OSF−3)。次い
で、NH4OH:H2O2:H2O=2.85:0.15:7の処理水溶液(煮
沸状態)によつて10分間処理し、約300ÅのSiをエツチ
ング除去した。次いで、上記と同様の混酸煮沸によつて
ライトエツチした(試料No.OSF−4)。First, a method of preparing a sample will be described. 8 ~ as starting material
A P (100) substrate of 12 Ωcm on which 650 Å SiO 2 was formed by thermal oxidation (Sample No. OSF-1) was used. RIE this
It was processed (CF 4 / H 2 , 6pa, 300W) (Sample No. OSF-2).
However, SiO 2 was completely etched off, and Si was RI for 5 minutes.
The test was carried out under the conditions as indicated by E (overetch condition for 5 minutes). Next, after removing the photoresist and ashing it with O 2 plasma to reduce contamination, boiled with a mixed acid of H 2 SO 4 and HNO 3 and then light-etched (SiO 2 on Si).
The (natural oxide film) was removed (Sample No. OSF-3). Then, NH 4 OH: H 2 O 2 : H 2 O = 2.85: 0.15: 7 was used for a treatment for 10 minutes with a treatment aqueous solution (boiled state) to remove about 300 Å Si by etching. Next, light etching was performed by the same mixed acid boiling as described above (Sample No. OSF-4).
試料は、上記プロセスによつて作製したOSF−1〜4の
4枚で、このうちOSF−1はRIEの汚染及び欠陥がない試
料で、以後のOSF−2〜4との比較のための試料であ
る。又OSF−4は本発明による処理の効果を調べるため
の試料である。The samples were 4 pieces of OSF-1 to 4 prepared by the above process. Of these, OSF-1 is a sample without RIE contamination and defects, and is a sample for comparison with OSF-2 to 4 below. Is. OSF-4 is a sample for investigating the effect of the treatment according to the present invention.
各試料は、OSFを調べるために、1000℃、2時間のスチ
ーム酸化後、酸化膜を剥離してライトエツチ(Wright E
tch)を施した。その結果、次のようになつた。In order to examine the OSF, each sample was steam-oxidized at 1000 ° C for 2 hours, and then the oxide film was peeled off to remove the Wright E
tch). As a result, it became as follows.
試料No. OSF量 OSF−1 OSFなし OSF−2 2×104個/cm2 OSF−3 4×104個/cm2 OSF−4 OSFなし この結果から分るように、本発明による処理(NH4OH:H
2O2:H2O=2.85:0.15:7、10分)で、約300ÅのSiをエツ
チオフしたものは、RIEによつて生じた汚染及び結晶欠
陥層が明らかに除去され、RIEを施こす前の状態、即
ち、OSF−1と同程度の良好な結晶状態に回復した。Sample No. OSF amount OSF-1 OSF None OSF-2 2 × 10 4 pieces / cm 2 OSF-3 4 × 10 4 pieces / cm 2 OSF-4 OSF None As can be seen from these results, the treatment according to the present invention ( NH 4 OH: H
2 O 2 : H 2 O = 2.85: 0.15: 7, 10 min), and about 300 Å of Si etched off, the contamination and crystal defect layer caused by RIE are clearly removed, and RIE is applied. The former state, that is, the crystal state as good as that of OSF-1 was recovered.
実験例3 SiO2のRIEにより層間絶縁膜をエツチングして、下地のN
+拡散層、P+拡散層又はリンをドープした多結晶Siにコ
ンタクトホール(1.5μ×1.5μ、2.0μ×2.0μ又は2.5
μ×2.5μの3種)を形成し、Al(1%Si含有)によつ
てコンタクトを形成した場合のコンタクト抵抗について
調べた。Experimental Example 3 Etching the interlayer insulating film with SiO 2 RIE
+ Diffusion layer, P + Diffusion layer or contact hole (1.5 μ × 1.5 μ, 2.0 μ × 2.0 μ or 2.5 μ × 1.5 μ
μ × 2.5 μ) was formed, and the contact resistance when forming a contact with Al (containing 1% Si) was examined.
コンタクト抵抗の測定に用いたパターン例を第3図に示
す。図中、A〜Dは端子であり、Al(1%Si含有)によ
つて形成されている。又、斜線を施した部分2は下地で
あり、N+拡散層、P+拡散層又は多結晶Siである。参照符
号1はコンタクトホールである。An example of the pattern used for measuring the contact resistance is shown in FIG. In the figure, A to D are terminals, which are formed of Al (containing 1% Si). Further, the shaded portion 2 is a base and is an N + diffusion layer, a P + diffusion layer or polycrystalline Si. Reference numeral 1 is a contact hole.
コンタクト抵抗の測定は4端子法、即ち、端子A−B間
に定電流(I=1.0mA)を流し端子C−D間での電位差
を測定する方法で行なつた。The contact resistance was measured by a four-terminal method, that is, a method of flowing a constant current (I = 1.0 mA) between the terminals A and B and measuring the potential difference between the terminals C and D.
本発明による処理の有用性を調べるために、SiO2のRIE
処理後にNH4OH:H2O2:H2O=2.85:0.15:7(煮沸状態)
で10分間処理(〜300ÅのSiをエツチオフ)したもの
と、本発明による処理を施さないものとのコンタクト抵
抗を比較検討した。To investigate the usefulness of the treatment according to the invention, RIE of SiO 2
After treatment NH 4 OH: H 2 O 2 : H 2 O = 2.85: 0.15: 7 (boiling state)
The contact resistances of the sample treated for 10 minutes (etching off Si up to 300 Å) and the sample not treated according to the present invention were compared and examined.
試料は、N+拡散層とAl(1%Si含有、以下同様)との組
合せ(RIE処理のみで本発明による処理を施さなかつた
もの:f、RIE処理後に本発明の処理を施したもの:f′、
以下同様)、多結晶SiとAlとの組合せ(g、g′)、P+
拡散層とAlとの組合せ(h、h′)について夫々調べ
た。RIE及びその後の処理方法は上記実験例2の場合と
同様であつた。但し、RIEは10分間オーバーエツチ条件
で行つた。又N+層は、As+を50KeV、5×1015cm-2でイオ
ン注入した後、1000℃、20分のアニール処理で形成し
た。一方、P+層は、BF2 +を50KeV、5×1015cm-2でイオ
ン注入し、1000℃、20分のアニール処理で形成した。更
に、リンをドープした多結晶Siは、純粋多結晶Si3000Å
にPSGの熱拡散処理を施して形成したものである。The sample was a combination of N + diffusion layer and Al (containing 1% Si, the same applies below) (one that was not subjected to the treatment according to the present invention only by RIE treatment: f, one that was subjected to the treatment according to the present invention after the RIE treatment: f ′,
The same shall apply hereinafter), a combination of polycrystalline Si and Al (g, g '), P +
The combinations (h, h ') of the diffusion layer and Al were examined respectively. The RIE and the subsequent processing method were the same as in the case of Experimental Example 2 above. However, RIE was conducted for 10 minutes under overetch conditions. The N + layer was formed by ion-implanting As + at 50 KeV and 5 × 10 15 cm -2 , and then annealing at 1000 ° C. for 20 minutes. On the other hand, the P + layer was formed by ion implantation of BF 2 + at 50 KeV and 5 × 10 15 cm −2 and annealing at 1000 ° C. for 20 minutes. Furthermore, the polycrystalline Si doped with phosphorus is pure polycrystalline Si3000Å
It is formed by subjecting PSG to thermal diffusion treatment.
第4図に各試料のコンタクト抵抗値(ウエハ内50ケ所で
の測定値の平均)を、又第5図に各ウエハ内におけるコ
ンタクト抵抗のばらつき(2σ/で定義したもの。但
し、σ:標準偏差、:平均値)を夫々示す。Fig. 4 shows the contact resistance value of each sample (average of the measured values at 50 points in the wafer), and Fig. 5 shows the variation of contact resistance within each wafer (2σ /, where σ: standard) Deviation ,: average value) are shown.
これら第4図及び第5図から明らかなように、N+−Al、
P+−Al、リンをドープした多結晶Si−Alの各サイズ(1.
5μ□〜2.5μ□)において、本発明による処理を施した
試料で、 (1) コンタクト抵抗の高抵抗化の防止及びオーミック
性 (2) コンタクト抵抗のウエハ内(ウエハ間も)均一性
の向上 が実証された。又、上記の試料作製において、RIE条件
は、故意にSi面が10分間RIEプラズマにされされる条件
(10分間オーバーエツチ条件)で行つたが、それにもか
かわらず上記(1)及び(2)の効果が認められた。従つて、
RIE条件がオーバーエツチの全くないジヤストエツチ条
件であれば、これらの効果が当然得られることは明らか
である。As is clear from FIGS. 4 and 5, N + -Al,
Sizes of P + -Al and phosphorus-doped polycrystalline Si-Al (1.
5μ □ to 2.5μ □ ), the sample treated by the present invention, (1) prevention of high contact resistance and ohmic property (2) improvement of uniformity of contact resistance within wafer (between wafers) Was demonstrated. Also, in the above sample preparation, the RIE conditions were set so that the Si surface was intentionally subjected to RIE plasma for 10 minutes (10 minutes overetch condition), but nevertheless, the above (1) and (2) The effect of was confirmed. Therefore,
It is clear that these effects can be naturally obtained if the RIE condition is the just-etch condition without any overetch.
それ故、本発明による表面処理には、例えばRIE条件の
不安定性(10分間程度以内のオーバーエツチ)要素をも
補うことができるという効果もある。Therefore, the surface treatment according to the present invention also has an effect that it is possible to compensate for the instability (overetching within about 10 minutes) factor of the RIE conditions.
RIE後に本発明による表面処理を施した場合の他の電気
的特性、即ちPN接合のI−V特性及び少数キヤリアのラ
イフタイムを夫々測定したが、特に異常は認められず、
MOS FET及びリング・オシレータの特性においても、正
常に動作していることが確認された。Other electrical characteristics when the surface treatment according to the present invention was performed after RIE, that is, the IV characteristics of the PN junction and the lifetime of a few carriers were measured, but no particular abnormality was observed.
It was confirmed that the MOS FET and the ring oscillator are also operating normally.
発明の効果 以上説明したように、本発明においては、ドライエッチ
ング工程に引き続き、アンモニア水(NH4OH)と過酸化
水素水(H2O2)とをNH4OH/H2O2=2/1〜2.95/0.05の割
合で含有する水溶液によってシリコン基板の表面層をエ
ッチングにより除去する。As described above, in the present invention, following the dry etching process, ammonia water (NH 4 OH) and hydrogen peroxide water (H 2 O 2 ) are mixed with NH 4 OH / H 2 O 2 = 2. The surface layer of the silicon substrate is removed by etching with an aqueous solution containing at a ratio of /1-2.95/0.05.
従つて、再現性よく、しかも充分なコントロール性を有
して、シリコン基板の微小な深さ(例えば100Å〜500Å
程度)のエツチングが可能である。しかもRIE等のドラ
イエツチングに比べてシリコン基板の損傷及び汚染が少
ない。このため、RIE等のドライエツチングで生じた汚
染及び結晶欠陥の除去に使用することができる。Therefore, it has good reproducibility and sufficient controllability, and has a very small depth of silicon substrate (for example, 100Å ~ 500Å
Etching is possible. Moreover, the silicon substrate is less damaged and contaminated as compared with dry etching such as RIE. Therefore, it can be used for removing contamination and crystal defects caused by dry etching such as RIE.
更に、本発明による方法は、RIE等のドライエツチング
と組み合せて用いることにより、エツチングの異方性や
材質選択エツチ性等の微細加工条件を満たしたままで、
半導体デバイスの良好な電気特性(例えば、接触抵抗の
低減、バラツキの低減、接合リーク電流の低減)を得る
ことができる。Furthermore, the method according to the present invention is used in combination with dry etching such as RIE to keep fine processing conditions such as etching anisotropy and material selection etchability.
It is possible to obtain good electrical characteristics of the semiconductor device (for example, reduction in contact resistance, variation, and junction leak current).
第1図はNH4OH/H2O2の混合比とSi基板のエツチング深
さとの関係を示すグラフ、第2図は処理時間とエツチン
グ量との関係を示すグラフ、第3図はコンタクト抵抗を
測定するためのパターンを示す概略平面図、第4図はコ
ンタクト抵抗の変化を示すグラフ、第5図はコンタクト
抵抗のばらつきを示すグラフである。 尚、図面に用いた符号において、 1……コンタクトホール 2……下地(拡散層又は多結晶Si) 3……Al電極(Si1%含有) A〜D……端子Fig. 1 is a graph showing the relationship between the NH 4 OH / H 2 O 2 mixture ratio and the etching depth of the Si substrate, Fig. 2 is a graph showing the relationship between the processing time and the etching amount, and Fig. 3 is the contact resistance. FIG. 4 is a schematic plan view showing a pattern for measuring the contact resistance, FIG. 4 is a graph showing changes in contact resistance, and FIG. 5 is a graph showing variations in contact resistance. In the reference numerals used in the drawings, 1 ... Contact hole 2 ... Base (diffusion layer or polycrystalline Si) 3 ... Al electrode (containing 1% Si) A to D ... Terminal
Claims (1)
ニア水(NH4OH)と過酸化水素水(H2O2)とをNH4OH/H2
O2=2/1〜2.95/0.05の割合で含有する水溶液によってシ
リコン基板の表面層をエッチングにより除去することを
特徴とする半導体基板の処理方法。1. A dry etching process is followed by adding ammonia water (NH 4 OH) and hydrogen peroxide water (H 2 O 2 ) to NH 4 OH / H 2
A method for treating a semiconductor substrate, characterized in that the surface layer of the silicon substrate is removed by etching with an aqueous solution containing O 2 = 2/1 to 2.95 / 0.05.
Priority Applications (1)
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---|---|---|---|
JP59088887A JPH0712038B2 (en) | 1984-05-02 | 1984-05-02 | Semiconductor substrate processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59088887A JPH0712038B2 (en) | 1984-05-02 | 1984-05-02 | Semiconductor substrate processing method |
Publications (2)
Publication Number | Publication Date |
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JPS60233824A JPS60233824A (en) | 1985-11-20 |
JPH0712038B2 true JPH0712038B2 (en) | 1995-02-08 |
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JP2906416B2 (en) * | 1988-09-16 | 1999-06-21 | ソニー株式会社 | Silicon etching method |
JPH02165641A (en) * | 1988-12-20 | 1990-06-26 | Sanyo Electric Co Ltd | Manufacture of field effect transistor |
JP2890220B2 (en) * | 1991-09-25 | 1999-05-10 | 三菱マテリアル株式会社 | Etching method and etching solution |
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