JPS6258138B2 - - Google Patents

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Publication number
JPS6258138B2
JPS6258138B2 JP14418379A JP14418379A JPS6258138B2 JP S6258138 B2 JPS6258138 B2 JP S6258138B2 JP 14418379 A JP14418379 A JP 14418379A JP 14418379 A JP14418379 A JP 14418379A JP S6258138 B2 JPS6258138 B2 JP S6258138B2
Authority
JP
Japan
Prior art keywords
oxygen
heat treatment
defects
substrate
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14418379A
Other languages
Japanese (ja)
Other versions
JPS5667922A (en
Inventor
Hideki Tsuya
Yukinobu Tanno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Original Assignee
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHO ERU ESU AI GIJUTSU KENKYU KUMIAI filed Critical CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority to JP14418379A priority Critical patent/JPS5667922A/en
Publication of JPS5667922A publication Critical patent/JPS5667922A/en
Publication of JPS6258138B2 publication Critical patent/JPS6258138B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は半導体基板の製造方法に係り、とくに
気相反応法によるシリコン単結晶薄膜のエピタキ
シヤル成長においてエピタキシヤル表面層にみら
れる微小欠陥を低減させる製造方法に関するもの
である。 シリコンエピタキシヤル層はIC,LSI用基板と
して、さらには超LSI用基板として不可欠なもの
であり、バイポーラ・デバイス用として用いられ
ている。このエピタキシヤル層には、例えば積層
欠陥、転位、微小欠陥(シヤロー・ピツト)等の
結晶欠陥がみられる。これらの結晶欠陥はデバイ
スの電気的特性を悪化させることはよく知られて
いる。これらの結晶欠陥を最小限に抑制すること
が素子の歩留り向上に寄与することができる。結
晶欠陥の抑制方法としては種々の方法が提案され
ている。現状ではエピタキシヤル層の積層欠陥
は、エピタキシヤル成長前のガスエツチングによ
りその欠陥密度を10個/cm2以下とすることがで
き、転位に関しては、エピタキシヤル成長時の均
一加熱方法等の改善により同じくその欠陥密度は
10個/cm2以下となりつつある。今ここで問題とな
るものはエピタキシヤル表面層にみられる微小欠
陥である。微小欠陥はデバイス工程を経るにつれ
成長して大きな積層欠陥となり歩留低下の原因と
なる。この微小欠陥密度は、従来の無処理ウエー
ハを用いたエピタキシヤル層には、106〜107個/
cm2みられ、デバイス特性、例えば耐圧低下との相
関が解明されつつある。 この微小欠陥を発生させる原因としては、拡散
速度の大きい重金属汚染によるものであろうと推
定されている。重金属はエピタキシヤル成長前処
理によるウエーハ表面の汚染によるものか、エピ
タキシヤル成長時に周辺の装置内壁から飛来する
かは、今のところ明らかではない。 重金属のゲツタリング方法としては、基板裏面
に、(1)機械的歪屑を形成する、(2)イオン注入によ
り歪屑を形成する、(3)Si3N4膜を形成し、ミスフ
イツト転位を導入する、(4)レーザによる歪屑の形
成等が提案されている。これらの裏面処理による
ゲツタリング効果については、MOSデバイスで
は、その有効性が確認されているが、バイポーラ
デバイスではプロセスがより複雑で、高温プロセ
スを繰り返していくと有効性が徐々に失われてい
くともいわれている。 本発明はシリコン単結晶基板を乾式酸素雰囲気
中と湿式酸素雰囲気中の二工程で熱処理すること
により、内部に析出物や転位からなる微小欠陥を
発生させ、その歪場により微小欠陥又はその核を
吸収するいわゆるイントリンシツク・ゲツタリン
グ(IG)効果によりエピタキシヤル膜中の微小
欠陥を低減化しようとするものである。 本発明は例えば、気相反応性によりシリコン単
結晶基板にシリコン単結晶薄膜をエピタキシヤル
成長させる工程において、該基板をあらかじめ乾
式酸素雰囲気中で650℃〜1000℃の温度範囲で16
時間以上熱処理したのち酸化膜を除去し、次いで
湿式酸素雰囲気中で1050℃〜1200℃の温度範囲で
少なくとも2時間熱処理する2種類の熱処理工程
を連続して行い、特にこのあとでエピタキシヤル
成長させることを特徴とする半導体基板の製造方
法である。又、湿式酸素雰囲気中で熱処理する前
にエピタキシヤル成長させる点にも特徴がある。 IG効果の有効性については、例えばG.A.
Rozgonyi et ol:Appl.Phys.Lett.vol.32,747〜
749(1978)の文献にみられるように、MOSデバ
イスのライフタイムの向上が報告されている。本
発明者らはIG効果がエピタキシヤル層中の微小
欠陥の低減化に特に有効であると考えた。以下実
施例に基き詳細に説明する。 実施例1;エピタキシヤル用の基板をあらかじめ
乾式酸素雰囲気中で、600℃〜1200℃の温度範囲
で16〜64時間熱処理し、酸化膜を除去したのち、
エピタキシヤル成長させた。エピタキシヤル膜中
の微小欠陥を評価するために、湿式酸素雰囲気中
で、1140℃、2時間熱処理し、ジルトルエツチ液
で30秒間エツチングし、ノマルスキー干渉顕微鏡
で観察した。その結果、乾式酸素中で、700℃〜
1000℃の温度範囲で熱処理した基板を用いてエピ
タキシヤル成長させたエピタキシヤル膜中の微小
欠陥は、大幅に低減し、5×103個/cm2以下であ
つた。 実施例2;種々の酸素濃度を有する基板について
上記の乾式酸素雰囲気中で熱処理し、内部欠陥の
発生及び格子間酸素量をエツチング及び赤外分光
法で測定した。その結果、格子間酸素の減少は出
発ウエーハの酸素濃度及び熱処理温度、時間に著
しく依存することが分つた。この格子間酸素の減
少量は内部欠陥の析出量に比例するが、エツチン
グ観察の結果、1000℃以下ではそのような相関が
明らかにみられた。格子間酸素の減少量の測定結
果の一例を第1表に示す。
The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for reducing minute defects found in an epitaxial surface layer during epitaxial growth of a silicon single crystal thin film by a vapor phase reaction method. Silicon epitaxial layers are essential as substrates for ICs and LSIs, as well as for VLSIs, and are used for bipolar devices. Crystal defects such as stacking faults, dislocations, and micro defects (shallow pits) are found in this epitaxial layer. It is well known that these crystal defects deteriorate the electrical characteristics of devices. Minimizing these crystal defects can contribute to improving the yield of devices. Various methods have been proposed to suppress crystal defects. Currently, stacking faults in epitaxial layers can be reduced to 10/cm 2 or less by gas etching before epitaxial growth, and dislocations can be reduced by improving uniform heating methods during epitaxial growth. Similarly, the defect density is
It is becoming less than 10 pieces/ cm2 . The problem here is minute defects found in the epitaxial surface layer. Micro defects grow as the device process progresses, becoming large stacking faults and causing a decrease in yield. This microdefect density is 10 6 to 10 7 per epitaxial layer using conventional untreated wafers.
cm2 , and the correlation with device characteristics, such as a drop in breakdown voltage, is being clarified. It is presumed that the cause of these microdefects is heavy metal contamination, which has a high diffusion rate. It is currently unclear whether the heavy metals are due to contamination of the wafer surface during epitaxial growth pretreatment, or whether they come flying from the inner walls of the surrounding equipment during epitaxial growth. The methods for gettering heavy metals include (1) forming mechanically strained debris on the back surface of the substrate, (2) forming strained debris by ion implantation, and (3) forming a Si 3 N 4 film and introducing misfit dislocations. (4) Formation of strained debris using a laser has been proposed. The effectiveness of the gettering effect caused by these backside treatments has been confirmed for MOS devices, but the process for bipolar devices is more complex, and it is believed that the effectiveness will gradually be lost as high-temperature processes are repeated. It is said. The present invention heat-treats a silicon single crystal substrate in two steps, one in a dry oxygen atmosphere and one in a wet oxygen atmosphere, to generate micro-defects consisting of precipitates and dislocations inside, and then use the resulting strain field to destroy the micro-defects or their nuclei. This is an attempt to reduce micro defects in the epitaxial film by the so-called intrinsic gettering (IG) effect. For example, in the process of epitaxially growing a silicon single-crystal thin film on a silicon single-crystal substrate by vapor phase reactivity, the present invention can be applied by pre-processing the substrate in a dry oxygen atmosphere at a temperature range of 650°C to 1000°C for 16 hours.
Two types of heat treatment steps are carried out in succession: removing the oxide film after heat treatment for more than an hour, and then heat treatment in a wet oxygen atmosphere at a temperature range of 1050°C to 1200°C for at least 2 hours, especially after this, epitaxial growth is performed. This is a method for manufacturing a semiconductor substrate characterized by the following. Another feature is that epitaxial growth is performed before heat treatment in a wet oxygen atmosphere. Regarding the effectiveness of IG effect, for example, GA
Rozgonyi et ol: Appl.Phys.Lett.vol.32, 747~
749 (1978), improvements in the lifetime of MOS devices have been reported. The present inventors considered that the IG effect is particularly effective in reducing microdefects in the epitaxial layer. A detailed explanation will be given below based on examples. Example 1: A substrate for epitaxial use was heat treated in advance in a dry oxygen atmosphere at a temperature range of 600°C to 1200°C for 16 to 64 hours to remove the oxide film.
Grown epitaxially. In order to evaluate minute defects in the epitaxial film, it was heat treated at 1140°C for 2 hours in a wet oxygen atmosphere, etched for 30 seconds with dilt etch solution, and observed using a Nomarski interference microscope. As a result, in dry oxygen, 700℃~
The number of minute defects in the epitaxial film grown epitaxially using a substrate heat-treated in a temperature range of 1000° C. was significantly reduced to 5×10 3 defects/cm 2 or less. Example 2: Substrates having various oxygen concentrations were heat-treated in the above dry oxygen atmosphere, and the occurrence of internal defects and the amount of interstitial oxygen were measured by etching and infrared spectroscopy. As a result, it was found that the reduction in interstitial oxygen significantly depends on the oxygen concentration of the starting wafer and the heat treatment temperature and time. The amount of interstitial oxygen decrease is proportional to the amount of precipitated internal defects, and etching observations clearly showed such a correlation at temperatures below 1000°C. An example of the measurement results of the amount of decrease in interstitial oxygen is shown in Table 1.

【表】 このように格子間酸素の減少率は、1)熱処理
時間が長いほど大きい、2)同一熱処理条件では
出発ウエーハの酸素濃度が高いほど大きい、3)
特定の温度で減少率が最大となる、等の特徴をも
つ振舞を示すことが分つた。 実施例3;次に上記の実施例2に示すように、乾
式酸素中で熱処理を施したウエーハの酸化膜を除
去したのち、湿式酸素中で1100℃〜1200℃で2時
間熱処理し格子間酸素の減少率及び内部欠陥の析
出の様子を測定した。その結果、650℃〜1000℃
の温度範囲で、乾式酸素中で熱処理を施した基板
を続いて、湿式酸素中で熱処理すると、格子間酸
素の減少率が更に著しく、また内部欠陥の増大も
顕著であることが分つた。第1表に示した試料を
更に湿式酸素中で、1140℃、2時間の熱処理を施
した場合の結果を第2表に示す。
[Table] The rate of decrease in interstitial oxygen is as follows: 1) The longer the heat treatment time is, the greater it is. 2) Under the same heat treatment conditions, the higher the oxygen concentration of the starting wafer, the greater the rate of decrease. 3)
It was found that it exhibits characteristic behavior, such as the rate of decrease reaching its maximum at a specific temperature. Example 3: Next, as shown in Example 2 above, the oxide film of the wafer heat-treated in dry oxygen was removed, and then heat-treated in wet oxygen at 1100°C to 1200°C for 2 hours to remove interstitial oxygen. The reduction rate and the state of precipitation of internal defects were measured. As a result, 650℃~1000℃
It has been found that when a substrate that has been heat-treated in dry oxygen is subsequently heat-treated in wet oxygen, the rate of decrease in interstitial oxygen is even more remarkable, and the increase in internal defects is also remarkable. Table 2 shows the results when the samples shown in Table 1 were further heat treated in wet oxygen at 1140°C for 2 hours.

【表】 このように、適切な温度範囲であらかじめ乾式
酸素中で熱処理を施したのち湿式酸素中で熱処理
を施すと、格子間酸素濃度の減少率は、第一処理
に比べて1桁以上も増大する場合のあることが分
つた。第二処理は短時間でよいので、この二つの
熱処理工程を続けて行うことにより、全体として
熱時間の短縮をはかることが可能となつた。例え
ば40%以上の減少率を達成するのに、第一処理の
みでは、試料Eで64時間も要するのに対して試料
Aでは、第一及び第二処理を施すことにより18時
間で十分である。つまり、第二処理を付け加える
ことにより、第一処理時間を大幅に短縮すること
ができる。また13×1017/cm3程度の酸素濃度が低
いウエーハでも第二処理を付け加えることによ
り、17.1%の減少率を達成することができIG効果
が認められた。 実施例4;連続した第一、第二処理の有効性を確
認するために、第一処理を施さずに、第二処理の
湿式酸素中でのみ熱処理を施しても格子間酸素濃
度の減少がみられず、また内部欠陥も発生しなか
つた。 実施例5;そこで上記の第一、第二処理の熱処理
工程を連続して行つたウエーハを用いてエピタキ
シヤル成長を行つたところ、IG効果が顕著にみ
られ、適切な熱処理条件の組合せでは、エピタキ
シヤル層中のの微小欠陥密度は5×103/cm2以下
であつた。 以上の実施例から明らかなように、乾式及び湿
式酸素中での熱処理を連続して施すことにより、
IG効果をもたらすための熱処理時間を大幅に短
縮することができる、また低酸素濃度基板でも
IG効果をもたらすことができる等、半導体装置
を製造する場合に、著しい効果を有することが分
つた。
[Table] As shown above, when heat treatment is performed in dry oxygen in advance at an appropriate temperature range and then heat treatment is performed in wet oxygen, the rate of decrease in interstitial oxygen concentration is more than one order of magnitude higher than in the first treatment. It was found that there are cases where it increases. Since the second treatment only takes a short time, by performing these two heat treatment steps in succession, it has become possible to shorten the heat time as a whole. For example, to achieve a reduction rate of 40% or more, it takes 64 hours for sample E with the first treatment alone, whereas 18 hours is sufficient for sample A with the first and second treatments. . In other words, by adding the second process, the first process time can be significantly shortened. Furthermore, by adding the second treatment to wafers with a low oxygen concentration of about 13×10 17 /cm 3 , a reduction rate of 17.1% could be achieved, and the IG effect was recognized. Example 4: In order to confirm the effectiveness of successive first and second treatments, the interstitial oxygen concentration did not decrease even if heat treatment was performed only in wet oxygen in the second treatment without performing the first treatment. No internal defects were observed. Example 5: Therefore, when epitaxial growth was performed using a wafer that had been subjected to the heat treatment steps of the first and second treatments described above, a remarkable IG effect was observed, and with an appropriate combination of heat treatment conditions, The microdefect density in the epitaxial layer was less than 5×10 3 /cm 2 . As is clear from the above examples, by successively performing dry and wet heat treatment in oxygen,
The heat treatment time required to produce the IG effect can be significantly shortened, and even on low oxygen concentration substrates.
It has been found that this method has significant effects when manufacturing semiconductor devices, such as being able to bring about the IG effect.

Claims (1)

【特許請求の範囲】[Claims] 1 気相反応性によりシリコン単結晶基板にシリ
コン単結晶薄膜をエピタキシヤル成長させる工程
において、エピタキシヤル成長後該基板を乾式酸
素雰囲気中で700℃から1150℃の温度範囲で熱処
理したのち、湿式酸素雰囲気中で1100℃〜1200℃
の温度範囲で熱処理することを特徴とする半導体
基板の製造方法。
1 In the process of epitaxially growing a silicon single crystal thin film on a silicon single crystal substrate by vapor phase reactivity, after the epitaxial growth, the substrate is heat treated in a dry oxygen atmosphere at a temperature range of 700°C to 1150°C, and then wet oxygen 1100℃~1200℃ in atmosphere
1. A method for manufacturing a semiconductor substrate, characterized by performing heat treatment in a temperature range of .
JP14418379A 1979-11-07 1979-11-07 Preparation method of semiconductor system Granted JPS5667922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14418379A JPS5667922A (en) 1979-11-07 1979-11-07 Preparation method of semiconductor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14418379A JPS5667922A (en) 1979-11-07 1979-11-07 Preparation method of semiconductor system

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP27874488A Division JPH02177321A (en) 1988-11-04 1988-11-04 Manufacture of semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS5667922A JPS5667922A (en) 1981-06-08
JPS6258138B2 true JPS6258138B2 (en) 1987-12-04

Family

ID=15356120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14418379A Granted JPS5667922A (en) 1979-11-07 1979-11-07 Preparation method of semiconductor system

Country Status (1)

Country Link
JP (1) JPS5667922A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994809A (en) * 1982-11-22 1984-05-31 Fujitsu Ltd Production of semiconductor element
JPH01265525A (en) * 1988-04-15 1989-10-23 Fujitsu Ltd Manufacture of semiconductor substrate

Also Published As

Publication number Publication date
JPS5667922A (en) 1981-06-08

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