JPH03156932A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance accuracy, to increase speed and to easily manufacture a semiconductor device by a method wherein one pair of high-concentration diffusion layers are formed on the surface of a substrate by making use of insulator sidewalls and a gate as a mask. CONSTITUTION:A gate 25 is formed by an etching operation using a mask; one pair of low-concentration diffusion layers 3 are formed on the surface of a substrate by making use of the gate 25 as a mask; after that, a conductive thin film is deposited on the whole surface; gate-sidewall insulator sidewalls 31 which come into contact with the conductive thin film on sidewalls of the gate are formed. The conductive thin film is etched by making use of the insulator sidewalls 31 as an etching mask; one pair of high-concentration diffusion layers are formed on the surface of the substrate by making use of the insulator sidewalls 31 and the gate 25 as a mask. Consequently, a gate length can be decided by one etching operation instead of two etching operations in conventional cases. Thereby, accuracy can be enhanced, and a semiconductor device can be manufactured simply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a technique that is effective when applied to a method of manufacturing a semiconductor device, and in particular, relates to a technique that is effective when applied to a method of manufacturing a semiconductor device, and particularly relates to hot carrier breakdown voltage, source,
The present invention relates to a technique that is effective when manufacturing a semiconductor device for the purpose of improving drain-to-drain breakdown voltage.

[Prior art] GOLD (GateDrain) is a semiconductor device with improved hot carrier breakdown voltage and source-drain breakdown voltage.
2. Description of the Related Art Semiconductor devices having a 0verlapped device (overlapped device) structure are known.

For this GOLD structure semiconductor device, for example, 1
It is described in "Nikkei Micro Devices, April issue, pages 58 to 64," published by Nikkei McGraw-Hill Co., Ltd. in 1988.

The third example shows an example of a semiconductor device with this GOLD structure.
It is a diagram.

In this semiconductor device, a pair of high concentration source and drain diffusion layers 2, 2 are formed on the surface of a semiconductor substrate 1, and a pair of low concentration source and drain diffusion layers are formed inside the pair of high concentration source and drain diffusion layers 2, 2. A natural oxide film 4 is formed, which acts as an etching stopper.
A gate 5 of a 2P gate structure sandwiched between polysilicon 5a and 5b, a pair of low concentration source and drain diffusion layers 3,
5ELOC8 oxidized portions 6 formed at both ends of the polysilicon 5b to control the overlap length of the polysilicon 5b.
It is equipped with Note that numerals 7 and 8 represent StO, a film, and 9
indicate the gate oxide film, respectively.

Next, the outline of the manufacturing process of this GOLD structure semiconductor device will be explained as follows.

First, gate oxide film 9 is formed on the surface of semiconductor substrate 1, and polysilicon 15d is deposited on the entire surface. Next, a natural oxide film 14 is formed on the surface of this polysilicon 15d, and polysilicon 15a, SjO, and a film 18 are formed on this natural oxide film 14.
are sequentially deposited to form the state shown in FIG. 4(a).

Next, using a mask, a resist is patterned using the polysilicon 15d, natural oxide film 14, polysilicon I5a, and SiO* film 18 on the SIO film 8a, and the polysilicon 5d, natural oxide film 4, and polysilicon film 18 are patterned. 5c,
Etching is performed to form a SiO film 8a, as shown in FIG. 4(b).
The state shown in

Next, with a resist (not shown) placed on the SiO film 8a, etching is performed to retreat the 5iO9 film 8a inward to form an SiO film 8, as shown in FIG. 4(C). be in the state shown.

Next, the polysilicon 5c is etched by isotropic etching using the natural oxide film 4 as an etching stopper.
Polysilicon 5a is formed to obtain the state shown in FIG. 4(d).

Next, impurities are implanted at a low concentration to form a pair of low concentration source and drain diffusion layers 3, 3, and then both ends of the polysilicon 5d are oxidized with 5ELOC3 to form S E
LOCS oxide film 6 is formed and polysilicon portion 5d becomes polysilicon portion 5b). After forming the 5jO1 film 7,
Impurities are implanted at a high concentration, and a pair of high concentration source and drain diffusion layers 2 and 2 are replaced with a low concentration source and drain diffusion layer 3.
, 3, the semiconductor device shown in FIG. 3 can be obtained.

[Problems to be Solved by the Invention] However, the above-mentioned GOLD structure semiconductor device has problems in terms of accuracy, process simplification, and high speed.

That is, the gate 5 is formed using a two-layer gate 5c.

Etching is required twice: etching to form the upper layer gate 5d and etching to retreat only the upper layer gate 5c to form the upper layer gate 5a, which inevitably leads to a problem in that the dimensional accuracy of the gate 5 deteriorates. be.

In addition, the thickness control of the natural oxide film 4 (+4) is difficult;
If the thickness of the natural oxide film 4 becomes too thick, there is a risk of electrical disconnection between the upper gate 5a and the lower gate 5b, and the thickness of the natural oxide film 4 may become too thick. If this occurs, the upper layer gate 5c cannot function as an etching stopper when retreating, and the lower layer gate 5b
There is a fear that the semiconductor device may be scraped off, and in any case, there is a problem that it is difficult to obtain a high-precision semiconductor device.

Further, there are problems in terms of precision, such as difficulty in controlling the length of the 5ELOC3 oxidized portion 6, and difficulty in controlling the overlap length between the gate 5 and the low concentration diffusion layer.

In addition, in order to increase the speed, the upper layer gate 5a is made of polycide (
In the case of using polysilicon (silicide), it is difficult to form the gate 5 in the desired shape due to the difference in the receding speed of polysilicon and silicide during etching to retreat the upper layer gate 5c, making it impossible to form a gate 5 with high precision. There is a problem.

Also, gate 5 and S E L OCS
Since the oxidized portion 6 cannot be formed with high precision, when a plurality of the above semiconductor devices are used, there is a problem that variations in characteristics become large and high speed cannot be achieved.

In addition, an etching process for recessing the upper layer gate 5c and
There is also the problem that it is extremely difficult to manufacture due to difficult-to-control processes such as the ELOC3 oxidation process.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can improve accuracy and speed, and can be manufactured easily.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a gate is formed by etching using a mask, a pair of low concentration diffusion layers are formed on the substrate surface using the gate as a mask, and then a conductive thin film is deposited on the entire surface so as to be in contact with the conductive thin film on the side wall of the gate. After forming an insulator sidewall on the gate sidewall, the conductive thin film is etched using the insulator sidewall as an etching mask, and a pair of high concentration diffusion layers are formed on the substrate surface using the insulator sidewall and the gate as a mask. It was designed to do so.

[Operation] According to the above-described means, a gate is formed by etching using a mask, a pair of low concentration diffusion layers are formed on the substrate surface using the gate as a mask, and then a conductive thin film is deposited on the entire surface. After forming a gate sidewall insulating sidewall in contact with the conductive thin film on the gate sidewall, the conductive thin film is etched using the insulating sidewall as an etching mask, and a pair of high-temperature layers are etched using the insulating sidewall and the gate as a mask. Since the concentration diffusion layer is formed on the substrate surface, the gate width (gate length) can be determined in one etching process instead of the conventional two etching steps, which improves precision and simplifies manufacturing. The above objective of doing so will be achieved.

Furthermore, the above-mentioned objective of improving precision can be achieved by eliminating the natural oxide film whose thickness is difficult to control.

In addition, the overlap length of the low concentration diffusion layer is 5ELC)
In place of the C3 oxidation part, the effect can be controlled by the insulating sidewall and the conductive thin film, which are determined by the film thickness of the gate formed with high accuracy as described above.
The above objective of improving accuracy will be achieved.

In addition, the gate shape is a rectangular parallelepiped structure that can be formed by normal etching without using isotropic etching, and even if this gate has a polycide structure, it can be formed with high accuracy by normal etching, which improves accuracy and speeds up etching. The above objective of aiming for this will be achieved.

In addition, as mentioned above, since the gate length and overlap length can be made highly accurate, even when multiple semiconductor devices are used, the variation in characteristics is extremely reduced, resulting in faster speed. will be achieved.

In addition, the etching process for recessing the upper layer gate and the 5EL
Due to the elimination of difficult-to-control processes such as the OC8 oxidation process, the above-mentioned objective of simple manufacturing can be achieved.

Embodiment Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a semiconductor device according to the present invention.

The semiconductor device of this embodiment is a so-called LDD (Light
y Doded Drain) structure)
In the semiconductor device of this embodiment, which is a transistor, a conductive bud film overlap gate 16 is formed on the side wall of the gate 25 and overlaps above the low concentration source and drain diffusion layers 3, 3. It functions in the same way as the GOLD structure semiconductor device.

Next, an example of the method for manufacturing the semiconductor device of the second embodiment will be described below based on FIGS. 2(a) to 2(d).

First, a gate oxide film 9 is formed on the surface of the semiconductor substrate 1, and polysilicon, for example, is deposited on the entire surface. Next, this polysilicon is etched using a mask to form a gate 25, and by ion implantation using this gate 25 as a mask, the low concentration source and drain diffusion layers 3a, 3a are formed on the substrate 1.
It is formed on the surface to obtain the state shown in FIG. 2(a).

Next, a conductive thin film 26 of polysilicon or the like is deposited over the entire surface to form the state shown in FIG. 2(b). Here, the thickness of the conductive thin film 26 is such that it does not inhibit the formation of the gate sidewall insulator sidewall 31 in the next step.

Next, a Sin film 31a indicated by a dotted line is deposited on the entire surface, and this 810. The film 31a is etched using a well-known RIE (ion reactive etching) technique to form the gate 25.
A gate sidewall insulator sidewall 31 is left on the sidewall to form the state shown in FIG. 2(C).

Next, the conductive thin film 26 is etched using the gate side wall insulating side wall 31 as an etching mask and the gate oxide film 9 as an etching stopper, so that the conductive thin film 26 remains only under and beside the gate side wall insulating side wall 31. The remaining conductive thin film has a conductive thin film overlap length of -1 to -16. Thereafter, high concentration source and drain diffusion layers 2, 2 are formed on the substrate surface by ion implantation using the insulating sidewall 31 and gate 25 as masks, resulting in the state shown in FIG. 2(d). Here, the low concentration source and drain diffusion layer 3.3 remains inside the high concentration source and drain diffusion layer 2.2.

Next, an interlayer insulating film 40 is deposited on the entire surface, and contact holes are formed in this interlayer insulating film 40 to form a source electrode, a drain electrode 4], a gate electrode 41, and a gate electrode 42, respectively, thereby completing the semiconductor device shown in FIG. You will get it.

Here, the conductive thin film overlap gate 16, which is a feature of this embodiment, has the function 1 of relaxing the drain electric field and suppressing the generation of hot carriers, similar to the lower gate 5b of the GOLD type semiconductor device. It also functions to suppress the injection of hot carriers into the gate side insulator sidewall 31 and improve the hot carrier breakdown voltage.

As a result, according to the method of manufacturing a semiconductor device according to the first embodiment, the following effects can be obtained.

That is, the gate 25 is etched using a mask.
After forming a pair of low concentration source and drain diffusion layers 3a, 3a on the surface of the substrate 1 using the gate 25 as a mask, a conductive thin film 26 is deposited on the entire surface, and the gate 2
After forming a gate sidewall insulator sidewall 31 in contact with the conductive thin film 26 on the sidewall 5, the conductive thin film 26 is etched using the insulator sidewall 31 as an etching mask, and the insulator sidewall 31 and the gate 25 are etched. Since a pair of high-concentration source and drain diffusion layers 2, 2 are formed on the surface of the substrate 1 using etching as a mask, the width (gate length) of the gate 25 can be determined in one etching process instead of the conventional two etching steps. Due to the effect of becoming
It becomes possible to improve accuracy and also to simplify manufacturing.

Furthermore, since the natural oxide film 4 whose thickness is difficult to control is eliminated, manufacturing can be simplified.

In addition, the overlap length of the low concentration diffusion layers 3, 3 is set to S
In place of the E L OCS oxide film 6, the effect can be controlled by the insulating sidewall 31 and the conductive thin film 16, which are determined by the film thickness of the gate 25, which is formed with high precision like two series. This makes it possible to improve the accuracy of the overlap length.

Furthermore, the shape of the gate 25 is a rectangular parallelepiped structure that can be formed by normal etching without using isotropic etching, and even if the gate 25 has a polycide structure, it can be formed with high precision by normal etching. It becomes possible to improve the precision of the width (gate length) of 25 and increase the speed.

Furthermore, since the gate length and overlap length can be made highly accurate as described above, even when a plurality of semiconductor devices are used, variations in characteristics are extremely reduced, making it possible to increase the speed.

In addition, it is possible to easily manufacture the semiconductor device by eliminating the need to control the etching process for recessing the double-layer gate 5c, SEL, OCS oxidation process, etc.

In addition, since the breakdown voltage can be improved by improving the dimensional accuracy as in the case of "double series", the length of the gate 25 (gate length) can be further shortened, and the speed of the semiconductor device can be further increased.
High integration is possible.

Further, the difference between the semiconductor device of the above embodiment and the MOS transistor of LDD structure is that the conductive thin film overlap gate 1
6, it is possible to coexist with a MOS transistor of the LI)D structure, and since most of the processes can be shared, manufacturing in the case of coexistence is extremely easy.

Hereinafter, the invention made by the inventor Niki has been specifically explained based on examples, but the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

For example, in the embodiment described above, the gate 25 is made of polysilicon or polycide, but it is of course possible to make it of other materials.

Note that if the present invention is applied to the Bi-0M03 circuit, it is possible to obtain a new effect of increasing the speed of the circuit without lowering the power supply voltage because of the high withstand voltage.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, a gate is formed by etching using a mask, a pair of low concentration diffusion layers are formed on the substrate surface using the gate as a mask, and then a conductive thin film is deposited on the entire surface so as to be in contact with the conductive thin film on the side wall of the gate. After forming an insulator sidewall on the gate sidewall, the conductive thin film is etched using the insulator sidewall as an etching mask, and a pair of high concentration diffusion layers are etched on the substrate surface using the insulator sidewall and the gate as a mask. Since the gate length is formed by etching, the gate length can be determined by one etching process instead of the conventional two etching steps. As a result, it becomes possible to improve the accuracy and also to simplify manufacturing.

Furthermore, since there is no natural oxide film whose thickness is difficult to control, it is possible to improve accuracy.

In addition, the overlap length of the low concentration diffusion layer is determined by SE L
In place of the OCS oxidized portion, control can be achieved using insulating sidewalls and conductive thin films determined by the film thickness of the gate, which are formed with high precision as described above. As a result, it becomes possible to improve accuracy.

Further, the gate shape is a rectangular parallelepiped structure that can be formed by ordinary etching without using isotropic etching, and even if this gate is a polycide structure, it can be obtained with high precision by ordinary etching. As a result, it becomes possible to improve accuracy and speed up the process.

Furthermore, since the gate length and overlap length can be made highly accurate as described above, variations in characteristics are extremely reduced even when a plurality of semiconductor devices are used. As a result, it becomes possible to increase the speed.

In addition, an etching process for recessing the upper layer gate and an S E
As a result of eliminating difficult-to-control processes such as the LOCS oxidation process, it becomes possible to manufacture easily.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of a semiconductor device obtained by applying an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2(a) to 2(cl) are semiconductor devices according to the present invention. Each process diagram of an embodiment of the device manufacturing method, FIG. 3 is a vertical cross-sectional view of a semiconductor device according to the prior art, and FIGS.
) are process diagrams of a method for manufacturing a semiconductor device according to the prior art. ■... Semiconductor substrate, 2... High concentration diffusion layer, 3...
...Low concentration diffusion layer, 16...Conductive thin film overlap gate, 25...Gate, 26...Conductive thin film, 31...Gate side wall insulator sidewall. 9-

Claims (1)

[Scope of Claims] 1. A pair of high concentration diffusion layers are formed on the surface of the semiconductor substrate, a pair of low concentration diffusion layers are formed inside the pair of high concentration diffusion layers, and an overlying layer is formed above the low concentration diffusion layers. A method for manufacturing a semiconductor device having a wrapping conductive layer on a gate side wall, the method comprising: forming the gate by etching using a mask; and forming a pair of low concentration diffusion layers on the surface of the substrate using the gate as a mask; After depositing a conductive thin film on the entire surface and forming a gate sidewall insulating sidewall in contact with the conductive thin film on the gate sidewall, the conductive thin film is etched using the insulating sidewall as an etching mask. A method of manufacturing a semiconductor device, characterized in that the pair of high concentration diffusion layers are formed on the surface of the substrate using the sidewalls and the gate as masks. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the gate is made of polycide. 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the semiconductor device is used for a Bi-CMOS transistor.