JPH05183160A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device wherein contact resistance is not increased even though the device is made finer. CONSTITUTION:There are provided on a silicon substrate 1 a gate electrode 4 formed through a gate oxide film 3, a source-drain diffusion layer 6 formed on the surface of the silicon substrate 1 oppositely to the gate electrode 4, a source-drain electrode 9 formed on the source-drain diffusion layer 6, and a Si-Ge mixed crystal layer 8 displaced between the source-drain electrode 9 and the source-drain diffusion layer 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of reducing contact resistance and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, large-scale integrated circuits (LSIs) formed by integrating a large number of transistors, resistors, etc. so as to achieve an electric circuit on a single chip are formed in important parts of computers and communication devices. It is used a lot. Therefore, the performance of the entire device is largely linked to the performance of the LSI alone.

The performance of the LSI itself can be improved by increasing the degree of integration, that is, by miniaturizing the elements. As the element becomes finer, the diameter of the contact hole connecting the wiring member and each element becomes smaller, and the contact area between the wiring member and the element becomes smaller. As a result, the resistance in the contact hole, so-called contact resistance, increases with the miniaturization of the element. Therefore, the contact resistance acts as a parasitic resistance, the current supplied to the element is reduced, and an operation delay occurs.

Therefore, in an electric field transistor (FET), as shown in FIG. 14, a method of forming a silicide 93 on the surface of the source / drain diffusion layer 92 has been studied. In this method, after forming the source / drain diffusion layer 92, an insulating film 93 is formed on the side wall of the polysilicon gate electrode 91, and then, on the entire surface of the silicon substrate 90.
A metal film made of titanium or the like is deposited, the heat treatment is applied to the metal film to silicide the polysilicon gate electrode 91 and the drain / source diffusion layer 92, and then the unreacted metal film is removed by etching. ..

By using such a method, even if the diameter of the contact hole is reduced, the effective contact area between the source / drain diffusion layer 92 and the source / drain electrode 95 can be reduced. The area can be made the same, and the increase in contact resistance can be prevented.

However, with further miniaturization in the future, the area of the source / drain diffusion layer 92 becomes 1.0 μm.
m ² It is expected that the contact resistance will be small, and as a result, even if the contact area is the same as the area of the source / drain 92, the value of the contact resistance becomes high, and problems such as operation delay occur. In particular, p ⁺ The contact resistance between the diffusion layer and the silicide is n ⁺ Since it is higher than that between the diffusion layer and the silicide, it is necessary to reduce the resistance of this portion.

[0007]

As described above, when the element is further miniaturized in the future, the area of the source / drain diffusion layer becomes very small even in the FET using silicide, so the source / drain There is a problem that the contact area between the electrode and the source / drain diffusion layer becomes small, which increases the contact resistance and causes a problem such as operation delay.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same which will not increase the contact resistance even if the element is further miniaturized in the future. To do.

[0009]

In order to achieve the above object, the semiconductor device of the present invention is configured such that silicon and a predetermined amount are provided between a source / drain diffusion layer and a source / drain electrode formed on a silicon substrate. A mixed crystal layer made of an element is provided, and the difference between the energy level at the valence band edge of the mixed crystal layer and the Fermi level of the source / drain electrode is the predetermined element. It is characterized in that an element smaller than the difference between the energy level at the valence band edge of the layer and the Fermi level of the source / drain electrodes is selected.

The semiconductor device manufacturing method of the present invention is
After forming the source / drain diffusion layer on the silicon substrate,
There is a step of forming a mixed crystal layer of silicon and a predetermined element on the source / drain diffusion layer by using a CVD method, and the energy level of the valence band edge of the mixed crystal layer is used as the predetermined element. An element whose difference between the Fermi level of the source / drain electrode and the Fermi level of the source / drain diffusion layer is smaller than the difference between the energy level of the valence band edge of the source / drain diffusion layer and the Fermi level of the source / drain electrode. It is characterized by Further, instead of using the CVD method, the mixed crystal layer may be formed by implanting ions of a predetermined element satisfying the above-described conditions into the source / drain diffusion layer.

[0011]

The contact resistance between the source / drain electrode and the source / drain diffusion layer becomes smaller as the difference between the Fermi level of the source / drain electrode and the energy level of the valence band of the source / drain diffusion layer becomes smaller.

In the semiconductor device of the present invention, the source / drain electrodes are connected to the source / drain diffusion layer through a mixed crystal layer of silicon and a predetermined element, and the predetermined element is
The difference between the energy level at the valence band edge of the mixed crystal layer and the Fermi level of the source / drain electrodes is
An element smaller than the difference between the energy level at the valence band edge of the drain diffusion layer and the Fermi level of the source / drain electrode is used.

That is, by connecting the source / drain diffusion layer and the source / drain electrode through the mixed crystal layer, the Fermi level of the source / drain electrode and the energy level of the valence band of the source / drain diffusion layer are connected. The difference between and is effectively reduced.

Therefore, even if the contact area between the source / drain electrode and the source / drain diffusion layer is reduced due to the miniaturization of the element, the increase in contact resistance due to this is prevented by the decrease in contact resistance due to the mixed crystal layer. it can.

In the method of manufacturing a semiconductor device, CVD is used.
A mixed crystal layer is formed on the source / drain diffusion layer by using the method. Therefore, the mixed crystal layer can be formed without damaging the silicon substrate.

[0016]

Embodiments will be described below with reference to the drawings. 1 and 2 show an MO according to the first embodiment of the present invention.
It is a manufacturing-process sectional drawing of an S transistor.

First, as shown in FIG. 1A, n-type Si
An element isolation oxide film 2 is formed on a substrate 1. Then, a gate oxide film 3 having a thickness of 8 nm is formed in the element formation region surrounded by the oxide film 2 by using a thermal oxidation method, and subsequently, a polycrystalline silicon film to be a gate electrode 4 having a thickness of 300 nm is formed on the entire surface. Deposit. Then, the polycrystalline silicon film is patterned by using the photolithography technique to form the gate electrode 4.

Next, as shown in FIG. 1B, after depositing a SiO ₂ film which will be the side wall gate insulating film 5 on the entire surface, this Si film is formed.
The entire surface of the O ₂ film is etched back to form a sidewall gate insulating film 5 on the sidewall of the gate electrode 4. Then acceleration voltage 40
BF ₂ is implanted under the conditions of keV and a dose of 5 × 10 ¹⁵ cm ⁻² , followed by heat treatment at 850 ° C. for 30 minutes in a nitrogen atmosphere to obtain p ^+. The source / drain diffusion layer 6 of the mold is formed.

Next, as shown in FIG. 2A, a CVD method is used to deposit an SiO ₂ film 7 having a thickness of 800 nm on the entire surface, and then a source / drain diffusion layer 6 and a source / drain formed in a later step are formed. A contact hole for making contact with the electrode 9 is formed. Next, accelerating voltage 20 keV, dose 3 × 10 ¹⁶ cm ² Ge ⁺ Ion implantation is performed. After that, heat treatment is performed at 600 ° C. for 1 hour in an Ar atmosphere to bond Ge and Si injected into the Si substrate 1 at the lower part of the contact hole. By such an ion implantation step and a heat treatment step, Si-G becomes Si _0.8 Ge _{0.2 on} the surface of the Si substrate 1 in the lower portion of the contact hole.
The mixed crystal layer 8 can be formed.

Next, as shown in FIG. 2 (b), in order to sufficiently increase the impurity activation rate of the Si-Ge mixed crystal layer 8 and the source / drain diffusion layer 6 thereunder, 10 in an Ar atmosphere.
Heat treatment is performed at 00 ° C. for 10 seconds. Next, an 800 nm thick Al alloy film is deposited on the entire surface as an electrode material. Finally, the Al alloy film is patterned to form the source / drain electrodes 9, and the MOS transistor is completed.

FIG. 3 shows the source / drain diffusion layer 6, the Si—Ge mixed crystal layer 8, and the source / drain electrode 9 in the contact hole of the MOS transistor obtained by the above method.
FIG. 4 is an energy band diagram of a MOS transistor obtained by a conventional method, that is, a MOS transistor in which a Si—Ge mixed crystal layer is not provided between a source / drain diffusion layer and a source / drain electrode. That is it. In the figure, φ _B is the energy level between the Fermi level of the source / drain electrode and the energy level of the valence band edge of the mixed crystal layer or the source / drain diffusion layer in contact with the source / drain electrode. It is the difference.

From these figures, it is understood that the energy level difference φ _B of the MOS transistor of this embodiment is smaller than that of the conventional one. This is because, in the MOS transistor of this example, the energy level of the minimum level of the valence band was shifted to the high level side due to the influence of the Si—Ge mixed crystal layer 8. As described above, Si- at the interface between the Si-Ge mixed crystal layer 8 and the source / drain electrode 9
The ratio of Si to Ge in the Ge mixed crystal layer 8 is 4: 1. On the other hand, the contact resistance R _c between the semiconductor having a high impurity concentration and the metal is expressed by the following equation using the energy level difference φ _B. R _c = α exp (Aφ _B / ^1/2 N _d ) where α is a proportional coefficient, N _d is the interface concentration of holes, and A is a constant. From the above equation, it can be seen that the contact resistance R _c decreases as the energy level difference φ _B decreases.

Therefore, the contact resistance of the MOS transistor of this embodiment can be made smaller than that of the conventional MOS transistor. Therefore, even if the area of the source / drain diffusion layer becomes smaller due to miniaturization, the operation due to the increase of the contact resistance will occur. There is no delay.

Further, in this embodiment, since the Si-Ge mixed crystal layer 8 is formed by using the ion implantation method, the Ge concentration becomes higher as it gets closer to the surface of the substrate. As a result, the Si-Ge mixed crystal layer 8 and The energy level of the conduction band of the source / drain electrodes changes smoothly as shown in FIG.

In this way, according to this embodiment, the energy level difference φ _B can be made small, so that it is possible to prevent an increase in contact resistance, and thus it is possible to obtain a MOS transistor in which operation delay does not occur even if miniaturization is performed. .. Although the contact hole is not completely closed in this embodiment, it may be completely closed with a metal such as W.

FIG. 6 shows an M according to the second embodiment of the present invention.
It is sectional drawing of an OS transistor. The MOS transistor of this embodiment is different from that of the previous embodiment in that the Si—Ge mixed crystal layer is formed by using the CVD method.

That is, the gate oxide film 13, the gate electrode 14, and the sidewall gate insulating film 15 are formed in the element formation region of the silicon substrate 11 surrounded by the element isolation oxide film 12 by the same method as in the previous embodiment. After that, BF ₂ ions are implanted under conditions of an acceleration voltage of 40 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² to form a p-type source / drain diffusion layer 16.
Then after depositing a SiO ₂ film 17 on the entire surface, the SiO ₂
A contact hole is opened in the film 17.

Next, the Si—Ge mixed crystal layer 18 is filled up to a predetermined height in the contact hole by a selective CVD method using a mixed gas of SiH ₄ , GeH _4, and H ₂ . Specifically, first, the total pressure of the mixed gas is set to 27 Pa (SiH ₄
Partial pressure: 6.5 Pa), substrate temperature is set to 550 ° C. and S
The i-Ge mixed crystal layer 18 is formed. And gradually GeH
_The partial pressure is increased to finally 1.3 Pa. During this period, the SiH ₄ partial pressure and total pressure are 6.5 Pa and 2 Pa, respectively.
The H ₂ partial pressure is reduced so that it becomes constant at 7 Pa. After forming the Si—Ge mixed crystal layer 18 by the CVD method under such conditions, for example, 200 keV of B, 1 × 10 ¹⁵ c
m ⁻² and 30 keV, 3 × 10 ¹⁵ cm ⁻² ion implantation was performed, and then Ar was used as the impurity at 1000 ° C.
Perform activation anneal for about 10 seconds. Finally, the source / drain electrodes 19 made of Al alloy are formed to complete the MOS transistor.

If the GeH ₄ partial pressure relative to the SiH ₄ partial pressure is kept constant, a Si—Ge mixed crystal layer having a constant ratio of Si and Ge of 4: 1 can be formed. In this case, as shown in FIG. The band structure as shown, that is, the Si-Ge mixed crystal layer 18 and S
A band structure in which the conduction band is discontinuous at the boundary with the i substrate 1 is obtained.

Also in the MOS transistor obtained by the above-mentioned method, since the source / drain electrode 19 is connected to the source / drain diffusion layer 16 through the Si-Ge mixed crystal layer 18, the conduction band edge, the valence electron The energy level difference φ _B becomes small and the contact resistance becomes small regardless of whether the band edge is discontinuous or continuous. Therefore, even if the element is miniaturized, the operation speed can be kept high. Also, CVD
Since the Si—Ge mixed crystal layer 18 is formed by using the method,
There is no possibility of damaging the Si substrate 11 as in the case of ion implantation.

In this embodiment, the contact hole was not completely filled with the Si-Ge mixed crystal layer 18, but the contact hole was filled with the Si-Ge mixed crystal layer 18 as shown in FIG.
Even if it is completely filled with, the same effect can be obtained.

Further, instead of depositing the Si-Ge mixed crystal layer 18 to a predetermined height in the contact hole by the selective CVD method, after depositing Si-Ge on the entire surface, the entire surface is etched back to perform the contact hole. Si-G in
The e mixed crystal layer 18 may be formed. FIG. 8 shows a third embodiment of the present invention.
FIG. 6 is a cross-sectional view of the manufacturing process of the MOS transistor according to the example.

First, using the same method as in the first embodiment, as shown in FIG. 8A, the gate oxide film 23 is formed in the element formation region of the silicon substrate 21 surrounded by the element isolation oxide film 22. , A gate electrode 24, a sidewall gate insulating film 25, and a p-type source / drain diffusion layer 26 are formed.

Next, as shown in FIG. 8B, Ge ⁺ Ions are implanted under the conditions of an acceleration voltage of 20 keV and a dose amount of 3 × 10 ¹⁶ cm ⁻² , and Ge is introduced into the surfaces of the gate electrode 24 and the source / drain diffusion layer 26. Then in Ar atmosphere,
Ge and Si are combined by heat treatment at 600 ° C. for 1 hour to form a Si—Ge mixed crystal layer 28. After this, Si
In order to increase the activation rate of impurities in the —Ge mixed crystal layer 28, the source / drain diffusion layer 26 thereunder, and the gate electrode 24, heat treatment is performed at 1000 ° C. for 10 seconds in an Ar atmosphere.

Next, as shown in FIG. 8C, a SiO ₂ film 27 having a thickness of 800 nm is deposited on the entire surface by the CVD method, and then a contact hole is opened in this SiO ₂ film 27. Finally, after depositing an Al alloy film with a thickness of 800 nm on the entire surface, this is patterned to form the source / drain electrodes 29, and the MOS transistor is completed.

Even with the method described above, the Si--Ge mixed crystal layer 2
Since the source / drain electrode 29 and the source / drain diffusion layer 26 are connected via 8 the energy level difference φ _B becomes small, and as a result, the parasitic resistance due to the contact resistance is reduced even if miniaturization is performed. Since it can be kept low, there is no operational delay. Although the contact hole is not completely closed in this embodiment, a structure in which the contact hole is completely closed by filling with a metal such as W may be used.

FIG. 9 shows an M according to the fourth embodiment of the present invention.
It is sectional drawing of an OS transistor. The difference between the MOS transistor of this embodiment and that of the third embodiment is that the CVD
The Si-Ge mixed crystal layer was formed by using the method.

That is, in the device formation region of the silicon substrate 31 surrounded by the device isolation oxide film 32, the gate oxide film 33,
After forming the gate electrode 34, the sidewall gate insulating film 35, and the p-type source / drain diffusion layer 36, a Si—Ge mixed crystal layer 38 having a thickness of, for example, 50 nm is formed on the source / drain diffusion layer 36 by the selective CVD method. Selectively formed. After that, the same step of depositing the SiO ₂ film 37, the step of opening a contact hole, the source / drain electrode 39 as in the previous embodiment.
The MOS transistor is completed through the formation process of. The introduction of impurities into the Si—Ge mixed crystal layer 38 on the source / drain diffusion layer 36 is performed by accelerating voltage of 40 keV,
After the ion implantation of B is performed under the condition that the dose amount is about 1 × 10 ¹⁶ cm ⁻² , activation annealing may be performed at 1000 ° C. for 10 seconds.

With the MOS transistor obtained by such a method, the same effect as in the previous embodiment can be obtained. Also in the case of this embodiment, the contact hole may be closed with a metal such as W. FIG. 10 shows an M according to the fifth embodiment of the present invention.
It is sectional drawing of an OS transistor.

This will be explained according to the manufacturing process.
A gate oxide film 43, a gate electrode 44, and a gate electrode 44 are formed in an element formation region of the silicon substrate 41 divided by the element isolation oxide film 42.
The sidewall gate insulating film 45 is formed.

Next, B ions are implanted to form a p-type source / drain diffusion layer 46, and then Ge ions are implanted to form a Si—Ge mixed crystal layer 48.
After that, in order to activate B of the source / drain diffusion layer 46, heat treatment is performed at 1000 ° C. for 10 seconds in an Ar atmosphere, as in the third embodiment.

Next, titanium silicide (TiSi ₂ ) 40 is selectively formed on the source / drain diffusion layer 46 by a selective CVD method using a mixed gas of SiH ₄ and TiCl ₄ and setting the substrate temperature at 750 ° C. Form.

Next, after depositing the SiO ₂ film 47 on the entire surface by the CVD method, a contact hole is opened in the SiO ₂ film 47. Finally, deposit an Al alloy film on the entire surface,
By patterning this, source / drain electrodes 49 are formed to complete a MOS transistor.

According to the method described above, TiSi ₂ is formed between the Si--Ge mixed crystal layer 48 and the source / drain electrode 49.
Since the film 40 is provided, the contact resistance can be further reduced.

Although the Si-Ge mixed crystal layer 48 is formed by using the Ge ion implantation method in this embodiment, as shown in FIG. 11, the Si-Ge mixed crystal layer 4 is formed by using the selective CVD method.
8a may be formed. Further, the contact hole may be completely closed with a metal such as W. FIG. 12 is a sectional view of a manufacturing process of a MOS transistor according to the sixth embodiment of the present invention.

First, as shown in FIG. 12A, n-type S
An element isolation SiO ₂ film 52 is formed on the i substrate 51.
Next, Ge ions were accelerated at an acceleration voltage of 100 keV and a dose of 3
Implanting is performed on the Si substrate 51 under the condition of × 10 ¹⁶ cm ^-2 , and then annealing is performed at 600 ° C. for 1 hour in an Ar atmosphere. As a result, the Si—Ge mixed crystal layer 58 is formed near the surface of the substrate, and the Si layer 50 is formed thereon. Next, this Si layer 50 is thermally oxidized to form a gate oxide film 5 with a thickness of 8 nm.
3 is formed, a polycrystalline silicon film to be the gate electrode 56 is deposited on the entire surface, and subsequently, this is patterned by using photolithography to form the gate electrode 56.
After that, a SiO ₂ film is deposited on the entire surface and is etched back to form a sidewall gate insulating film 55.

Next, as shown in FIG. 12B, BF ₂ ions are implanted under the conditions of an acceleration voltage of 40 keV and a dose of 5 × 10 ¹⁵ cm ^-2 , and then annealed at 850 ° C. for 30 minutes in a nitrogen atmosphere. P-type source / drain diffusion layer 5
6 is formed.

Next, as shown in FIG. 12C, a SiO ₂ film 57 having a thickness of 800 nm is deposited on the entire surface by the CVD method, and then the SiO ₂ film 57 and the Si layer 50 thereunder are sequentially etched. Then, a contact hole is formed so that the Si—Ge mixed crystal layer 58 is exposed. Finally, an Al alloy film is deposited on the entire surface and patterned to form source / drain electrodes 59, thus completing the MOS transistor.

Even with the method described above, the MOS described above
Similar to the transistor, the Si—Ge mixed crystal layer 58 reduces the energy level difference φ _B, so that the contact resistance can be reduced.

The Si-Ge mixed crystal layer 58 can be formed by using a selective CVD method instead of the ion implantation. That is,
After the element isolation SiO ₂ film 52 is formed, Si is formed on the surface of the Si substrate 51 in the element formation region by the selective CVD method.
The —Ge mixed crystal layer 58 is deposited, and thereafter, the Si layer 50 may be deposited on the Si—Ge mixed crystal layer 58 by using the selective CVD method again. Further, the contact hole may be filled with a metal such as W.

FIG. 13 is a sectional view of a MOS transistor according to the seventh embodiment of the present invention. Note that M in FIG.
The parts corresponding to the OS transistors are designated by the same reference numerals as those in FIG. 12, and detailed description thereof will be omitted. MO of this embodiment
The S-transistor differs from that of the sixth embodiment in that
This is because silicide was formed on the i-Ge mixed crystal layer 58.

That is, after forming the source / drain diffusion layer 56, a Ti film is deposited on the entire surface, and subsequently, annealing is performed at 700 ° C. for 30 seconds in a nitrogen atmosphere. As a result,
The Si layer 50 that was in contact with the Ti film was entirely the TiSi ₂ film 6
Change to 0. After that, the unreacted Ti film and TiN film are removed. The subsequent steps are the same as in the previous embodiment. Through the above steps, a MOS transistor having a structure in which the TiSi ₂ film 60 remains on the gate electrode 54 and the source / drain diffusion layer 56 can be obtained.

In the MOS transistor thus obtained, since the TiSi ₂ film 50 is formed between the Si-Ge mixed crystal layer 58 and the source / drain electrode 59,
The contact resistance is further reduced. The contact hole may be completely filled with a metal such as W.

The present invention is not limited to the above embodiment. For example, in the MOS transistor shown in FIG. 7, the Si-Ge is entirely deposited and etched back.
Although the contact hole is completely filled with the Si-Ge mixed crystal layer, the contact hole may be filled with the selective CVD method. Although TiSi ₂ is used as the silicide in the fifth and seventh embodiments, other silicide may be used.

In the above embodiment, the p channel MO is used.
Although the case of the S transistor has been described, the present invention is
n-channel MOS transistor, MIS transistor using silicon other than MOS transistor, and
The same applies to CMOS transistors.

In the above embodiment, the mixed crystal layer of Si--Ge is used, but a mixed crystal layer of Si and another element, for example, S.
A mixed crystal layer of a group IV element other than i and Ge may be used.
The point is that the energy level difference φ _B should be small. In addition, various modifications can be made without departing from the scope of the present invention.

[0057]

As described in detail above, according to the present invention, even if the element is miniaturized and the contact area between the source / drain electrode and the source / drain diffusion layer is reduced, the contact resistance is prevented from increasing. It is possible to obtain a possible semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of the MOS transistor according to the first embodiment of the present invention.

3 is an energy band diagram of a contact hole portion of the MOS transistor of FIG.

FIG. 4 is an energy band diagram of a contact hole portion of a conventional MOS transistor.

5 is an energy band diagram of a contact hole portion of the MOS transistor of FIG.

FIG. 6 is a sectional view of a MOS transistor according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a MOS transistor in which a contact hole is filled with a Si—Ge mixed crystal layer.

FIG. 8 is a sectional view showing the steps of manufacturing a MOS transistor according to the third embodiment of the present invention.

FIG. 9 is a sectional view of a MOS transistor according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view of a MOS transistor according to a fifth embodiment of the present invention.

FIG. 11 is a cross-sectional view of a MOS transistor when a Si—Ge mixed crystal layer is formed by using the selective CVD method.

FIG. 12 is a sectional view showing the steps of manufacturing a MOS transistor according to the sixth embodiment of the present invention.

FIG. 13 is a sectional view of a MOS transistor according to a seventh embodiment of the present invention.

FIG. 14 is a sectional view of a conventional MOS transistor.

[Explanation of symbols]

1, 11, 21, 31, 41, 51 ... Si substrate 2, 12, 22, 32, 42, 52 ... Element isolation oxide film 3, 13, 23, 33, 43, 53 ... Gate oxide film 4, 14, 24, 34, 44, 54 ... Gate electrode 5, 15, 25, 35, 45, 55 ... Side wall gate insulating film 6, 16, 26, 36, 46, 56 ... Source / drain diffusion layer 7, 17, 27, 37 , 47, 57 ... SiO ₂ film 8, 18, 28, 38, 48, 58 ... Si-Ge mixed crystal layer 9, 19, 29, 39, 49, 59 ... Source / drain electrode 40, 60 ... Titanium silicide (TiSi ₂ ) 50 ... Si layer

Claims (2)

[Claims] 1. A source formed on the surface of a silicon substrate.
A drain diffusion layer, a source / drain electrode formed on the source / drain diffusion layer, and a mixture of silicon and a predetermined element provided between the source / drain electrode and the source / drain diffusion layer. The difference between the energy level at the valence band edge of the mixed crystal layer and the Fermi level of the source / drain electrode as the predetermined element is equal to that of the source / drain diffusion layer. A semiconductor device characterized in that an element smaller than a difference between an energy level at a valence band edge and a Fermi level of the source / drain electrodes is selected. 2. A step of forming a source / drain diffusion layer on the surface of a silicon substrate, and a step of forming a mixed crystal layer of silicon and a predetermined element on the source / drain diffusion layer by a CVD method. A step of forming a source / drain electrode on the mixed crystal layer, the energy level at a valence band edge of the mixed crystal layer and a Fermi level of the source / drain electrode as the predetermined element. Of an element whose difference from the Fermi level of the source / drain electrode is smaller than the difference between the energy level at the valence band edge of the source / drain diffusion layer and the Fermi level of the source / drain electrode. Method.