WO2019093206A1 - Semiconductor device, and method for manufacturing same - Google Patents
Semiconductor device, and method for manufacturing same Download PDFInfo
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- WO2019093206A1 WO2019093206A1 PCT/JP2018/040555 JP2018040555W WO2019093206A1 WO 2019093206 A1 WO2019093206 A1 WO 2019093206A1 JP 2018040555 W JP2018040555 W JP 2018040555W WO 2019093206 A1 WO2019093206 A1 WO 2019093206A1
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- Prior art keywords
- silicon
- tungsten
- silicide film
- layer
- tungsten silicide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 171
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 170
- 239000010703 silicon Substances 0.000 claims abstract description 168
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 114
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 114
- 229910052751 metal Inorganic materials 0.000 claims abstract description 80
- 239000002184 metal Substances 0.000 claims abstract description 80
- 239000010937 tungsten Substances 0.000 claims abstract description 77
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 77
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 56
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 56
- 150000001875 compounds Chemical class 0.000 claims abstract description 43
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 30
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 71
- 239000002243 precursor Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- -1 tungsten nitride Chemical class 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000002360 preparation method Methods 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 67
- 230000009467 reduction Effects 0.000 abstract description 9
- UDKYUQZDRMRDOR-UHFFFAOYSA-N tungsten Chemical compound [W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W] UDKYUQZDRMRDOR-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 127
- 239000007789 gas Substances 0.000 description 61
- 238000010438 heat treatment Methods 0.000 description 29
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 23
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 23
- 239000000463 material Substances 0.000 description 15
- 230000001603 reducing effect Effects 0.000 description 15
- 239000000758 substrate Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 150000003624 transition metals Chemical class 0.000 description 11
- 239000002994 raw material Substances 0.000 description 10
- 229910052723 transition metal Inorganic materials 0.000 description 10
- 229910021350 transition metal silicide Inorganic materials 0.000 description 9
- 239000012071 phase Substances 0.000 description 8
- 229910052731 fluorine Inorganic materials 0.000 description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 239000012528 membrane Substances 0.000 description 6
- 229910000077 silane Inorganic materials 0.000 description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 5
- 239000012298 atmosphere Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000011737 fluorine Substances 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- XRXPBLNWIMLYNO-UHFFFAOYSA-J tetrafluorotungsten Chemical compound F[W](F)(F)F XRXPBLNWIMLYNO-UHFFFAOYSA-J 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000001069 Raman spectroscopy Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 125000001153 fluoro group Chemical group F* 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- YOUIDGQAIILFBW-UHFFFAOYSA-J tetrachlorotungsten Chemical compound Cl[W](Cl)(Cl)Cl YOUIDGQAIILFBW-UHFFFAOYSA-J 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/42—Silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to a semiconductor device in which the contact resistance reduction of an electrode portion is realized using a tungsten silicide film and a method of manufacturing the same.
- CMOS complementary metal oxide semiconductor
- the oxide used in the MOS is a metal oxide such as hafnium oxide or a semiconductor oxide such as silicon oxide
- the metal electrode is tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, nickel, At least one of cobalt, molybdenum, and silicon having a high carrier concentration.
- the CMOS is composed of a negative (n) type MOS and a positive (p) type MOS. In the n-type MOS, the metal electrode and the n-type semiconductor layer are normally joined at the source / drain, and in the p-type MOS, the metal electrode and the p-type semiconductor layer are normally joined at the source / drain.
- transition metal silicide films made of metal and silicon are also called transition metal silicon compounds or transition metal silicides, and research and development have been advanced in recent years.
- Transition metal silicide films that make use of metal characteristics are called metallic silicides or metallic silicides, and are excellent in heat resistance, oxidation resistance, corrosion resistance, electrical conductivity, etc., and they are electrodes, high temperature structures, environmental coatings, etc. It is expected as a material for A transition metal silicide film utilizing the characteristics as a semiconductor is called a silicide semiconductor or a silicide semiconductor or a semiconducting silicide, and is expected as a material for a light emitting element, a solar cell, a thermoelectric conversion element or the like.
- transition metal silicide films are known as materials having a good matching with processes such as LSI using silicon.
- a transition metal-containing silicon cluster surrounded by 16 or less Si atoms is used as a unit structure, and Si is disposed in the first and second adjacent atoms of the transition metal atoms, and has the following features.
- the first is suppression of deterioration due to hydrogen desorption
- the second is electric conductivity controllability by the field effect and high carrier mobility.
- the present inventors have also proposed that a film having a transition metal-containing silicon cluster as a unit structure can be substituted for amorphous silicon and used in the channel region of a thin film transistor (see Patent Document 2).
- the present inventors have also proposed a semiconductor contact structure produced by heteroepitaxial growth of a metal silicon compound thin film having a composition ratio n of transition metal M to silicon in the range of 7-16 on a semiconductor substrate surface (patent document 3).
- Patent Document 4 proposes a Si NMOS transistor having a source / drain structure in which a WSi n film is inserted at the contact interface between a metal electrode film and a semiconductor substrate (N-type Si substrate).
- CMOS complementary metal-oxide-semiconductor
- miniaturization there arises a problem that the contact resistance between the semiconductor layer (silicon, germanium, silicon germanium) at the source / drain and the metal electrode contact becomes apparent.
- the contact resistance at the metal electrode contact of both the n-type MOS and the p-type MOS it is necessary to reduce the contact resistance at the metal electrode contact of both the n-type MOS and the p-type MOS.
- the energy barrier height (hole barrier height) for holes formed between the metal electrode and the p-type semiconductor layer.
- the hole barrier height is increased, and when the hole barrier height is reduced, the electron barrier height is increased. That is, as long as the same junction material and the same laminated structure are used for the n-type MOS and the p-type MOS, the reduction of both the electron barrier height and the hole barrier height can not be compatible. Therefore, it is necessary to use two types of junction materials in CMOS, such as junction materials for reducing the electron barrier height for n-type MOS, another junction material for reducing the hole barrier height for p-type MOS, and so on.
- the two types of bonding materials cause the complexity of the CMOS manufacturing process, and there is a problem that the manufacturing cost becomes high.
- a joint material titanium nitride or titanium
- titanium titanium
- the present invention is intended to solve these problems, and the present invention can be miniaturized and the contact resistance at the metal electrode contact of the source / drain of both n-type MOS and p-type MOS. It is an object of the present invention to provide a semiconductor device having a structure capable of reducing the An object of the present invention is to provide a semiconductor device in which the performance of a CMOS is improved by reducing the contact resistance by using a common junction material for an n-type MOS and a p-type MOS. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying a CMOS manufacturing process and suppressing the manufacturing cost.
- the present invention has the following features to achieve the above object.
- a semiconductor device comprising: a second stacked structure stacked in order; and a composition ratio of silicon / tungsten of the tungsten silicide film being greater than 4 and 12 or less.
- the metal electrode is at least one or more of tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, nickel, cobalt, and molybdenum. apparatus.
- the composition ratio of (carbon) / (silicon + carbon) is more than 0 and 0.5 or less, any one of the above (1) to (3)
- the silicon layer or the compound layer of silicon and carbon in the first laminated structure is an n-type carrier type, and the compound layer of silicon and germanium in the second laminated structure is a p-type
- a structure in which at least one of the first and second laminated structures is arranged in parallel two or more, and the order of the metal, the oxide film, and the semiconductor layer in the middle position of the paralleled structure The semiconductor device according to any one of the above (1) to (5), which comprises a MOS structure stacked in the above. (7) The device according to any one of (1) to (6), further comprising: a CMOS structure in which the plurality of first laminated structures and the plurality of second laminated structures are connected by metal wiring. Semiconductor devices.
- the chemical reaction of the tungsten source gas and the silicon source gas in the gas phase produces a precursor having a silicon / tungsten composition ratio of greater than 4 and 12 or less in the gas phase, Depositing a metal layer on a silicon layer or a compound layer of silicon and carbon and a compound layer of silicon and germanium to form a tungsten silicide film, and an electrode manufacturing step of forming a metal electrode on the tungsten silicide film;
- the method of manufacturing a semiconductor device according to the above (1) comprising: (9)
- the electrode manufacturing step is a step of manufacturing a tungsten electrode on the tungsten silicide film using a source gas containing at least one source gas of the source gas of tungsten and a source gas of silicon.
- a tungsten silicide film having a specific composition ratio is both an n-type silicon layer or a compound layer of n-type silicon and carbon in an n-type MOS and a p-type silicon germanium layer or a p-type germanium layer in a p-type MOS.
- the electron barrier height of the n-type MOS and the hole barrier height of the p-type MOS and both the n-type MOS and the p-type MOS source / drain metal electrode contact
- the driving force of the CMOS can be improved by reducing the contact resistance of Therefore, further miniaturization and performance improvement of the integrated circuit can be achieved.
- the hole barrier height can be reduced.
- the tungsten silicide film When a compound layer of n-type silicon and carbon is used in the first laminated structure, the tungsten silicide film performs pinning relaxation of Fermi level as in the case of the n-type silicon layer, and electron barrier height to the compound layer of silicon and carbon Reduce the When the composition ratio of (carbon) / (silicon + carbon) is greater than 0 and 0.5 or less, the driving power of the CMOS can be further improved.
- a common tungsten silicide film is formed at the metal electrode contact portion of both the n-type MOS and the p-type MOS source / drain so that both the n-type MOS and the p-type MOS source / Since the contact resistance at the metal electrode contact portion of the drain can be reduced, the manufacturing process can be made common, and the number of processes can be reduced and simplified.
- the tungsten electrode can be formed on the upper portion of the tungsten silicide film by using the same source gas as the tungsten silicide film, so that the increase in manufacturing cost can be suppressed.
- FIG. 5 is a schematic cross-sectional view of a semiconductor device provided with a silicon layer 4 in contact with the silicon layer 3 and the silicon germanium layer 13 in addition to the first laminated structure, the second laminated structure, and the silicon layer 3. It is a cross-sectional schematic diagram of n-type MOS. It is a cross-sectional schematic diagram of p-type MOS.
- CMOS structure It is a cross-sectional schematic diagram of CMOS structure. It is a figure which shows the electric current (I) -voltage (V) characteristic of the Schottky diode laminated
- the inventors of the present invention have a first laminated structure in which a metal electrode, a tungsten silicide film, and a silicon layer are sequentially laminated, and the metal electrode, the tungsten silicide film, and a compound layer of silicon and germanium in this order.
- a metal electrode, a tungsten silicide film, and a silicon layer are sequentially laminated, and the metal electrode, the tungsten silicide film, and a compound layer of silicon and germanium in this order.
- the silicon / tungsten composition ratio of the tungsten silicide film is greater than 4 and 12 or less.
- FIG. 1 is a schematic cross-sectional view for explaining the basic structure of a semiconductor device according to an embodiment of the present invention.
- the basic structure of the semiconductor device includes at least a first laminated structure in which a metal electrode 1, a tungsten silicide film 2 and a silicon layer 3 are laminated in this order, and a metal electrode 11, a tungsten silicide film 12 and a silicon germanium layer 13 in this order.
- a second laminated structure is provided.
- FIG. 2 is a schematic cross-sectional view of one specific shape of the semiconductor device similar to FIG.
- a first laminated structure in which a metal electrode 1, a tungsten silicide film 2 and a silicon layer 3 are laminated in this order, and a metal electrode 11, a tungsten silicide film 12 and a silicon germanium layer 13 in this order.
- FIG. 3 is a schematic cross-sectional view of a plane orthogonal to FIG. 2 of the electrode (1, 11) portion having the structure surrounded by the tungsten silicide film (2, 12) in FIG.
- the metal electrode is preferably at least one or more of tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, nickel, cobalt, and molybdenum.
- the compound layer of silicon and germanium preferably has a composition ratio of (germanium) / (silicon + germanium) of more than 0 and 1 or less. That is, the compound layer of silicon and germanium is a germanium layer or a compound layer composed of silicon and germanium. Furthermore, when the hole barrier height of the p-type MOS is further reduced and the drivability of the CMOS is improved, it is more preferable that the composition ratio be a value close to one.
- the compound layer of silicon and carbon preferably has a composition ratio of (carbon) / (silicon + carbon) of more than 0 and 0.5 or less. Furthermore, in order to improve the driving power of CMOS, it is more preferable that the composition ratio be a value close to 0.5.
- the silicon layer or the compound layer of silicon and carbon in the first laminated structure is an n-type carrier type, and the compound layer of silicon and germanium in the second laminated structure is a p-type carrier type It is preferable to construct a CMOS structure using these stacked structures.
- FIG. 6 is a schematic cross-sectional view of a semiconductor device further including a silicon layer 4 in contact with the silicon layer 3 and the silicon germanium layer 13.
- a representative example of the semiconductor device according to the embodiment of the present invention is a CMOS.
- a first laminated structure in which a metal electrode, a tungsten silicide film, and an n-type silicon layer are laminated in order of source / drain of n-type MOS in CMOS is used.
- a compound layer of silicon and carbon may be used instead of the n-type silicon layer.
- An n-type silicon layer may be further provided in contact with the silicon-carbon compound layer of the first laminated structure.
- the metal electrode, the tungsten silicide film, the compound layer of silicon and carbon, and the n-type silicon layer are in this order.
- a second stacked structure in which a metal electrode, a tungsten silicide film, and a germanium layer are stacked in this order is used as the source / drain of p-type MOS in CMOS.
- the germanium layer may be a compound layer of silicon and germanium.
- a p-type silicon layer is further provided in contact with the germanium layer of the second stacked structure.
- the metal electrode, the tungsten silicide film, the germanium layer, and the p-type silicon layer are in this order.
- the metal electrode contact portion of the source / drain of n-type MOS and p-type MOS Both contact resistances can be reduced, and the driving power of the CMOS can be improved.
- the silicon / tungsten composition ratio of the common tungsten silicide film is greater than four and less than or equal to twelve.
- FIG. 5 is a schematic cross-sectional view of an n-type MOS.
- the n-type MOS is formed of a metal electrode (gate) 5 (M), an oxide 6 between two first laminated structures laminated in the order of the metal electrode 1, the tungsten silicide film 2, and the n-type silicon layer 3. (O), has a MOS structure in which a p-type silicon layer 4 (S) is stacked in this order.
- FIG. 6 is a schematic cross-sectional view of a p-type MOS.
- a metal electrode (gate) 15 (M) an oxide between two second laminated structures laminated in the order of the metal electrode 11, the tungsten silicide film 12, the silicon germanium layer or the germanium layer 13; It has a MOS structure laminated in the order of 16 (O) and silicon layer 14 (S).
- the silicon layer 14 has n-type carriers, and the silicon germanium layer or germanium layer 13 has p-type carriers.
- FIG. 7 is a schematic cross-sectional view of a complementary MOS (CMOS) structure in which an n-type MOS and a p-type MOS are adjacent to each other.
- CMOS complementary MOS
- the n-type MOS portion is similar to FIG. 5, and the p-type MOS portion is similar to FIG.
- a precursor gas of silicon / tungsten having a composition ratio of more than 4 and 12 or less is produced by chemically reacting a tungsten source gas and a silicon source gas in a gas phase. Depositing the precursor on a silicon layer or a compound layer of silicon and carbon or a compound layer of silicon and germanium to form a tungsten silicide film; And at least an electrode producing step for producing on a membrane.
- a heat treatment step for reducing both the desired electron barrier height and the hole barrier height after the step of forming the tungsten silicide film.
- the heat treatment conditions are preferably in the range of 400 ° C. to 700 ° C.
- the tungsten silicide film is formed using the raw material gas containing at least one or more raw material gases of the raw material gas of tungsten and the raw material gas of silicon used in the step of manufacturing the tungsten silicide film. It can also be made on top.
- the semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings.
- the case of a CMOS in which the first stacked structure includes a silicon layer will be described as a representative example.
- the metal electrode contact portion of the source / drain of the n-type MOS in the CMOS of the present embodiment has a laminated structure of a metal electrode, a tungsten silicide film, and an n-type silicon layer.
- the metal electrode contact portion of the source / drain of the p-type MOS in the CMOS of the present embodiment has a laminated structure of a metal electrode, a tungsten silicide film, and a compound layer (or germanium layer) of silicon and germanium.
- the height of the energy barrier at the metal electrode contact portion of both the n-type MOS and the p-type MOS source / drain can be reduced.
- the mechanism for reducing the energy barrier height of the present invention is based on the adjustment function of the Fermi level by the tungsten silicide film. Details will be described below.
- the electron barrier height is high because the Fermi level of the metal electrode is pinned to the charge neutral level which is slightly closer to the valence band edge than the silicon mid gap. Tends to be high and the hole barrier height tends to be low.
- the electron barrier height is about 0.68 eV when the tungsten electrode and n-type silicon are directly bonded, and the hole barrier height is about 0 when the tungsten electrode and p-type silicon are directly bonded. It shows .43 eV.
- the tungsten silicide film can perform pinning relaxation at the Fermi level, and the height of the electron barrier to n-type Si can be reduced.
- the electron barrier height is reduced to 0.32 eV. The reduced electron barrier height is maintained even after heat treatment at 600 ° C. for 30 minutes in a nitrogen atmosphere described later.
- the electron barrier height can be reduced without heat treatment, in order to realize both the low hole barrier height of the p-type MOS and the low electron barrier height of the n-type MOS described later. And a heat treatment process at about 600.degree. C. to the CMOS.
- the silicon layer has a crystal structure having a compressive strain or a tensile strain than ordinary single crystal silicon. Further, since the silicon layer is a semiconductor having n-type carriers, phosphorus (P), arsenic (As), antimony (Sb), and the like are contained as impurity elements.
- the hole barrier height can be reduced by performing heat treatment after fabricating a stacked structure of a tungsten silicide film and a silicon germanium layer or a germanium layer.
- the same effect can be obtained by further providing a p-type silicon layer in contact with the silicon germanium layer or the germanium layer.
- the tungsten silicide film reduces the Fermi level pinning of the metal electrode, and the hole barrier height relative to the silicon germanium layer or germanium layer shows a high value.
- the Fermi level is pinned near the valence band edge of the silicon germanium layer or the germanium layer to reduce the hole barrier height. For example, heat treatment is performed at 600 ° C.
- the hole barrier height can be reduced to 0.51 eV.
- the reduction effect of the hole barrier height after the heat treatment is caused by the interdiffusion occurring at the interface between the silicon germanium layer or the germanium layer and the tungsten silicide film by the heat treatment to change the atomic structure.
- the (germanium) / (silicon + germanium) composition ratio of the silicon germanium layer is closer to 1 interdiffusion is likely to occur, but the (germanium) / (silicon + germanium) composition ratio of the silicon germanium layer is closer to 0
- the reduction effect of the hole barrier height can be sufficiently obtained. Therefore, if the composition ratio is greater than 0 and 1 or less, the hole barrier height can be reduced.
- a silicon germanium layer or a germanium layer is widely used to apply compressive strain to an adjacent silicon layer. At this time, the silicon germanium layer or the germanium layer is also in a distorted state from the normal crystalline state, but also in this case, the same reduction effect of the hole barrier height is exerted.
- a silicon germanium layer or a germanium layer is a semiconductor having a p-type carrier, when boron (B), aluminum (Al), gallium (Ga), or the like is contained as an impurity element, a crystal defect or There are cases where atomic vacancies are used as acceptors.
- the relationship between the energy barrier and the silicon / tungsten composition ratio was investigated when a tungsten electrode was used as the metal electrode.
- FIG. 8 is a diagram showing current (I) -voltage (V) characteristics of a Schottky diode stacked in the order of a tungsten (W) electrode, a tungsten silicide WSi n film, and a silicon (Si) layer.
- the carrier type of the silicon layer is n-type on the left and p-type on the right.
- a stacked structure of a normal metal electrode and a semiconductor layer with a low carrier density is called a Schottky diode, and an energy barrier is formed at the stacked interface to exhibit rectification characteristics.
- line A is W electrode / n-type Si
- line D is W electrode / p-type Si
- FIG. 9 shows a Schottky diode laminated in the order of a tungsten electrode and a silicon layer, a Schottky diode laminated in the order of a tungsten electrode, a tungsten silicide film and an n-type silicon layer, a tungsten electrode, a tungsten silicide film and germanium It is the figure which showed the relationship between the energy barrier height and the composition ratio of a tungsten silicide film
- the multilayer structure of W electrodes / WSi n film (n 12) / n-type Si, the 0.32 eV.
- the hole barrier height with respect to p-type silicon can be adjusted.
- the above barrier height can be determined from current-voltage measurement and capacitance-voltage measurement.
- the height of the electron barrier to n-type silicon is reduced by increasing the silicon / tungsten composition ratio of the tungsten silicide film.
- the hole barrier height for p-type silicon can be increased.
- the sum of the barrier heights of electrons and holes for the same composition ratio shows a value close to 1.1 eV of the band gap of silicon.
- the hole barrier height can be reduced to 0.51 eV by inserting a germanium layer between the p-type silicon layer and the tungsten silicide film.
- FIG. 10 shows a stacked structure of n-type MOS stacked in the order of tungsten electrode / tungsten silicide film / silicon layer, and a stacked structure of p-type MOS stacked in the order of tungsten electrode / tungsten silicide film / germanium layer / silicon layer
- FIG. 10 shows a stacked structure of n-type MOS stacked in the order of tungsten electrode / tungsten silicide film / silicon layer
- Step 1 A step of forming an n-type silicon layer for an n-type MOS structure and a silicon-germanium layer for a p-type MOS structure as a preliminary step of formation of a structure of metal electrode contact portions of source / drain.
- Step 2 A step of forming a tungsten silicide layer on an n-type silicon layer for the n-type MOS structure and a silicon germanium layer for the p-type MOS structure.
- Step 3 A step of forming a metal electrode on a tungsten silicide layer for an n-type MOS structure and a tungsten silicide layer for a p-type MOS structure.
- Step 4 A heat treatment step for adjusting the electron barrier height.
- the formation of the tungsten silicide layer in (Step 2) can be produced by chemically reacting a tungsten source gas and a silicon source gas in a gas phase. It is the same manufacturing method as that described in Patent Document 4. More specifically, the composition ratio of silicon / tungsten exceeds 4 by chemically reacting the raw material gas with the raw material gas of tungsten and the raw material gas of silicon, instead of chemically reacting the raw material gas of silicon on the substrate surface.
- a tungsten silicide film having a silicon / tungsten composition ratio of more than 4 can be produced. For example, by filling the silicon source gas in advance in a reactor maintained at 400 ° C.
- tungsten silicide film is produced.
- Tungsten fluoride gas, tungsten chloride gas, organic tungsten gas etc. are mentioned as source gas of tungsten.
- source gases for silicon silane gas, disilane gas, dichlorosilane, silicon tetrachloride and the like can be mentioned.
- FIG. 11 is a view showing the fluorine atom concentration in a tungsten silicide film having a silicon / tungsten composition ratio of 12 obtained by secondary ion mass spectrometry (SIMS).
- SIMS secondary ion mass spectrometry
- the impurity fluorine is known to adversely affect the semiconductor device, and the residual fluorine concentration in the film is at least 1 atomic% or more in the conventional tungsten film or tungsten silicide film manufactured using tungsten tetrafluoride gas. there were.
- the reason why the concentration of fluorine in the tungsten silicide film of this embodiment is small is that the precursor of the tungsten silicide film synthesized in the vapor phase completely reduces the fluorine in the tungsten tetrafluoride gas with a reducing gas such as silane.
- an electrode forming method in a normal CMOS can be appropriately used. Any electrode material can be used as long as it is used in CMOS as a metal electrode, and is not particularly limited. The electrode material mentioned above is more preferable. In the present embodiment, tungsten metal or a compound of tungsten is more preferable. Tungsten nitride etc. are mentioned as a compound of tungsten. When tungsten metal or a compound of tungsten is used as the electrode, the source gas used in step 2 can be used also in the subsequent electrode forming step, so that simplification of the manufacturing process can be achieved.
- tungsten silicide film and a tungsten electrode by a combination of a tungsten source gas and a silicon source gas.
- a tungsten silicide film can be produced by a combination of a tungsten fluoride gas and a disilane gas
- a tungsten electrode can be produced by a combination of a tungsten fluoride gas and a silane gas.
- a tungsten silicide film can be made of a combination of tungsten fluoride gas and silane gas
- a tungsten electrode can be made of a combination of tungsten chloride gas and silane gas.
- the tungsten silicide film is formed using the source gas containing at least one source gas of the source gas of tungsten and the source gas of silicon used in the step of forming the tungsten silicide film. It can be made on top.
- the heat treatment step in (Step 4) will be described in detail.
- a common tungsten silicide film and metal electrode are formed at the metal electrode contact portion of both the n-type MOS and the p-type MOS, and then heat treatment is performed in a nitrogen atmosphere at 600 ° C.
- the hole barrier height of the p-type MOS can be reduced to 0.51 eV while maintaining the electron barrier height at 0.32 eV.
- the electron barrier height reducing effect of the n-type MOS and the hole barrier height reducing effect of the p-type MOS are effective even in a vacuum atmosphere or a hydrogen atmosphere. Heat treatment under an oxygen atmosphere is not desirable to promote the oxidation of the metal electrode.
- the range of the heat treatment temperature is not limited to 600 ° C., and the range of 400 ° C. or more and 700 ° C. or less is desirable.
- the timing of the heat treatment may be any time after forming the tungsten silicide film.
- the silicon / tungsten composition ratio of the tungsten silicide film is high and close to 12. The reason is that the energy gap of the tungsten silicide film increases as the silicon / tungsten composition ratio of the tungsten silicide film increases, and the density of states at the contact interface between the tungsten silicide film and the semiconductor layer can be reduced.
- the silicon / tungsten composition ratio of the tungsten silicide film is larger than four. If it is smaller than 4, the energy gap of the tungsten silicide film is so small that the density of states at the contact interface between the tungsten silicide film and the semiconductor layer can not be reduced, so the electron barrier height can not be sufficiently reduced. This is because it is effective only for reducing the hole barrier height. Therefore, it is important that the silicon / tungsten composition ratio be greater than 4 and 12 or less.
- FIG. 12 is a Raman scattering spectrum showing the bonding state of silicon atoms in a tungsten silicide film having a silicon / tungsten composition ratio of 12. Two broad peaks of the same 475cm around -1 and 165cm -1 with coupling network of the amorphous silicon could be observed. This indicates that silicon atoms have an amorphous bonding state in the tungsten silicide film. In addition, this amorphous bonding state is maintained even by heat treatment up to 1000 ° C. or more, and has a strong bonding network.
- FIG. 13 shows shots formed in the order of a tungsten electrode, a tungsten silicide film, a germanium layer, and a p-type silicon layer after deposition before heat treatment and when the heat treatment conditions are heat treatment temperatures of 400 ° C., 500 ° C. and 600 ° C. It is a figure which shows the electric current (I) -voltage (V) characteristic of a key diode. Although not shown for 700 ° C., the same excellent properties were exhibited. From this figure, it is understood that the range of the heat treatment temperature is desirably in the range of 400 ° C. to 700 ° C.
- CMOS complementary metal oxide semiconductor
- the following effects can also be obtained.
- application of a new material to CMOS entails an increase in manufacturing cost due to the introduction of a new manufacturing process and an increase in the number of manufacturing processes.
- a common tungsten silicide film can be applied to the metal electrode contact portion of the source / drain of n-type MOS and p-type MOS, so reduction or maintenance of the number of processes in CMOS manufacturing can be achieved. It is possible to suppress an increase in manufacturing cost.
- the tungsten electrode can be formed on the upper portion of the tungsten silicide film using the same source gas as the tungsten silicide film, so that the increase in the manufacturing cost can be suppressed.
- the tungsten silicide film manufactured according to the present embodiment is characterized in that the step coverage is excellent. For example, it is possible to completely cover the tungsten silicide film (sidewall / uppermost surface) at a film thickness ratio of about 1/2 on a fine step with a high aspect ratio of about 50 and a width of 40 nm. The reason why the excellent step coverage can be exhibited is based on the characteristic formation process of the tungsten silicide film.
- the tungsten silicide film precursor synthesized in the vapor phase has a low adhesion probability to the deposition substrate, and after deposition, has a high diffusivity on the deposition substrate surface.
- the excellent coverage of the tungsten silicide film makes it possible to bury the open source contact holes with a diameter of less than 100 nm of the source / drain of the CMOS, and obtain the effect of suppressing the variation of the operating characteristics of the CMOS and the contact resistance reduction effect. it can.
- the semiconductor device of the second embodiment relates to the case where a compound layer of silicon and carbon is used in place of the silicon layer of the first laminated structure in the first embodiment.
- the tungsten silicide film can relieve the pinning at the Fermi level and reduce the height of the electron barrier to the compound layer of silicon and carbon. Therefore, the same effect as the first embodiment Is obtained. Since the compound layer of silicon and carbon has a melting point higher than that of silicon, mutual diffusion at the interface between the tungsten silicide film and the compound layer of silicon and carbon is difficult to occur even if heat treatment is performed, and the Fermi level depinning effect is It is maintained also after the heat treatment process. Even if phosphorus (P), hydrogen (As), antimony (Sb) or the like is contained as an impurity element, the same effect as that of the first embodiment can be obtained.
- the semiconductor device of the present invention has a structure capable of reducing the contact resistance of the metal contact portion of both the n-type MOS and the p-type MOS, the miniaturization of the CMOS and the improvement of the driving force are required. It can be widely used for products. Further, according to the manufacturing method of the present invention, miniaturization and integration of CMOS and further efficiency of the manufacturing process can be further expected, which is industrially useful.
Abstract
Provided are: a semiconductor device that realizes a reduction in contact resistance of a metal contact part of a source/drain of a CMOS, etc.; and a method for manufacturing said semiconductor device. There is realized a semiconductor device comprising: a first laminated structure in which a metal electrode, a tungsten silicide film, and a silicon layer or a compound layer of silicon and carbon are laminated in the stated order; and a second laminated structure in which the metal electrode, the tungsten silicide film, and a compound layer of silicon and germanium are laminated in the stated order. Using a component in which the composition ratio of the silicon/tungsten of the tungsten silicide film is greater than 4 and no more than 12 reduces the energy barrier height at a source/drain metal contact part of both an n-type MOS and a p-type MOS.
Description
本発明は、タングステンシリサイド膜を用いて電極部の接触抵抗低減を実現した半導体装置及びその製造方法に関する。
The present invention relates to a semiconductor device in which the contact resistance reduction of an electrode portion is realized using a tungsten silicide film and a method of manufacturing the same.
近年、ＬＳＩを構成するトランジスタとして、相補型金属酸化物半導体（Ｃｏｍｐｌｅｍｅｎｔａｌｙ Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ（ＣＭＯＳ））の電界効果トランジスタが用いられている。ＭＯＳで用いられる酸化物は、ハフニウム酸化物などの金属酸化物、あるいはシリコン酸化物などの半導体酸化物であり、金属電極は、タングステン、窒化タングステン、チタン、窒化チタン、タンタル、窒化タンタル、ニッケル、コバルト、モリブデン、高キャリア濃度を有するシリコン、のうちの少なくとも一つ以上である。ＣＭＯＳは、Ｎｅｇａｔｉｖｅ（ｎ）型ＭＯＳとＰｏｓｉｔｉｖｅ（ｐ）型ＭＯＳから構成されている。ｎ型ＭＯＳでは、通常、ソース／ドレインにおいて、金属電極とｎ型半導体層が接合しており、ｐ型ＭＯＳでは、通常、ソース／ドレインにおいて、金属電極とｐ型半導体層が接合している。
In recent years, a field effect transistor of a complementary metal oxide semiconductor (CMOS) has been used as a transistor constituting an LSI. The oxide used in the MOS is a metal oxide such as hafnium oxide or a semiconductor oxide such as silicon oxide, and the metal electrode is tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, nickel, At least one of cobalt, molybdenum, and silicon having a high carrier concentration. The CMOS is composed of a negative (n) type MOS and a positive (p) type MOS. In the n-type MOS, the metal electrode and the n-type semiconductor layer are normally joined at the source / drain, and in the p-type MOS, the metal electrode and the p-type semiconductor layer are normally joined at the source / drain.
ところで、金属とシリコンからなる遷移金属シリサイド膜は、遷移金属珪素化合物又は遷移金属珪化物とも呼ばれ、近年に研究開発が進められている。金属としての特性を利用した遷移金属シリサイド膜は、金属性シリサイド又はメタリックシリサイドと呼ばれ、耐熱性、耐酸化性、耐食性、電気伝導特性等に優れ、電極、高温構造物、耐環境用コーティングなどの材料として期待される。半導体としての特性を利用した遷移金属シリサイド膜は、シリサイド半導体又はシリサイド系半導体又はセミコンダクティングシリサイドと呼ばれ、発光素子、太陽電池、熱電変換素子等の材料として期待される。また、半導体装置の技術分野では、遷移金属シリサイド膜は、シリコンを用いるＬＳＩ等のプロセスにマッチングのよい材料として知られている。
Incidentally, transition metal silicide films made of metal and silicon are also called transition metal silicon compounds or transition metal silicides, and research and development have been advanced in recent years. Transition metal silicide films that make use of metal characteristics are called metallic silicides or metallic silicides, and are excellent in heat resistance, oxidation resistance, corrosion resistance, electrical conductivity, etc., and they are electrodes, high temperature structures, environmental coatings, etc. It is expected as a material for A transition metal silicide film utilizing the characteristics as a semiconductor is called a silicide semiconductor or a silicide semiconductor or a semiconducting silicide, and is expected as a material for a light emitting element, a solar cell, a thermoelectric conversion element or the like. In addition, in the technical field of semiconductor devices, transition metal silicide films are known as materials having a good matching with processes such as LSI using silicon.
本発明者らは、先に、ＭＳｉｎ（但し、Ｍ：遷移金属、Ｓｉ：シリコン、ｎ＝７－１６）に係る遷移金属シリサイド膜を提案し、該遷移金属シリサイド膜を用いた半導体装置を提案した（特許文献１、特許文献２参照）。特許文献１に係る前記遷移金属シリサイド膜ＭＳｉｎ（但し、Ｍ：遷移金属、Ｓｉ：シリコン、ｎ＝７－１６）は、遷移金属とシリコンの化合物であり、遷移金属原子の周りを７個以上１６個以下のＳｉ原子が取り囲む遷移金属内包シリコンクラスターを単位構造とし、遷移金属原子の第１及び第２近接原子にＳｉが配置されており、次のような特徴を備えている。第１は、水素脱離による劣化の抑制であり、第２は、電界効果による電気伝導制御性と高いキャリア移動度である。また、本発明者らは、遷移金属内包シリコンクラスターを単位構造とした膜は、アモルファスシリコンに代替し薄膜トランジスタのチャネル領域に用いることができることを提案した（特許文献２参照）。
The present inventors have previously, MSi n (where, M: a transition metal, Si: silicon, n = 7-16) proposes a transition metal silicide film according to the semiconductor device using the transition metal silicide film It proposed (refer patent document 1 and patent document 2). The transition metal silicide film MSi n according to Patent Document 1 (where, M: a transition metal, Si: silicon, n = 7-16) is a compound of a transition metal and silicon, 7 or more around the transition metal atom A transition metal-containing silicon cluster surrounded by 16 or less Si atoms is used as a unit structure, and Si is disposed in the first and second adjacent atoms of the transition metal atoms, and has the following features. The first is suppression of deterioration due to hydrogen desorption, and the second is electric conductivity controllability by the field effect and high carrier mobility. The present inventors have also proposed that a film having a transition metal-containing silicon cluster as a unit structure can be substituted for amorphous silicon and used in the channel region of a thin film transistor (see Patent Document 2).
また、本発明者らは、遷移金属Ｍとシリコンの組成比ｎが７－１６の範囲の金属珪素化合物薄膜を、半導体基板表面上にヘテロエピタキシャル成長させて作製した半導体コンタクト構造を提案した（特許文献３参照）。
The present inventors have also proposed a semiconductor contact structure produced by heteroepitaxial growth of a metal silicon compound thin film having a composition ratio n of transition metal M to silicon in the range of 7-16 on a semiconductor substrate surface (patent document 3).
また、本発明者らは、遷移金属の原料ガスとシリコンの原料ガスを気相中で化学反応させることにより、シリコン／遷移金属の組成比が３より大で１６以下の前駆体を気相中で作製した後に、該前駆体を基板上に堆積して、シリコン／遷移金属の組成比が３より大で１６以下の遷移金属シリサイド膜を該基板上に作製することを実現した（特許文献４参照）。特許文献４では、金属電極膜と半導体基板（Ｎ型Ｓｉ基板）の接触界面にＷＳｉｎ膜を挿入したソース／ドレイン構造を持つＳｉのＮＭＯＳトランジスタを提案した。Ｓｉ組成比ｎの高いＷＳｉｎ膜（例えば、ｎ＝８－１２）を用いることにより、Ｓｉ基板とＷＳｉｎ膜の接触界面に生じる欠陥準位を低減することができ、金属とＳｉ基板の間で生じるエネルギー障壁の高さを制御して金属／Ｓｉ基板の接触抵抗を低減することが可能となることを開示した。ＷＳｉｎ膜を備える電極構造は、Ｎ－ＭＯＳトランジスタのみならず、Ｐ－ＭＯＳトランジスタにも有効であり、また、Ｓｉトランジスタのみならず、Ｇｅトランジスタにも有効であることを開示した。
Also, the present inventors chemically react a raw material gas of transition metal and a raw material gas of silicon in a gas phase to form a silicon / transition metal composition ratio of greater than 3 and less than or equal to 16 in the gas phase. It was realized that the precursor was deposited on a substrate to produce a transition metal silicide film having a silicon / transition metal composition ratio of more than 3 and 16 or less on the substrate (Patent Document 4). reference). Patent Document 4 proposes a Si NMOS transistor having a source / drain structure in which a WSi n film is inserted at the contact interface between a metal electrode film and a semiconductor substrate (N-type Si substrate). By using a WSi n film having a high Si composition ratio n (for example, n = 8-12), it is possible to reduce the level of defects generated at the contact interface between the Si substrate and the WSi n film, and between metal and Si substrate It has been disclosed that it is possible to control the height of the energy barrier that is generated by reducing the contact resistance of the metal / Si substrate. It has been disclosed that the electrode structure provided with the WSi n film is effective not only for N-MOS transistors but also for P-MOS transistors, and also effective for not only Si transistors but also Ge transistors.
従来、ＣＭＯＳは、微細化により性能を向上させている。しかしながら、微細化に伴い、ソース／ドレインにおける半導体層（シリコン、ゲルマニウム、シリコンゲルマニウム）と金属電極接触部の接触抵抗が顕在化する問題が生じる。ＣＭＯＳの性能向上のためには、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属電極接触部での接触抵抗低減が必要である。
Conventionally, the performance of CMOS has been improved by miniaturization. However, with the miniaturization, there arises a problem that the contact resistance between the semiconductor layer (silicon, germanium, silicon germanium) at the source / drain and the metal electrode contact becomes apparent. In order to improve the performance of the CMOS, it is necessary to reduce the contact resistance at the metal electrode contact of both the n-type MOS and the p-type MOS.
接触抵抗低減のために、これまでに、様々な接合材料や積層構造が提案されてきた。例えば、接合材料として、窒化チタン、チタン、窒化タンタル、タンタル、窒化シリコンなどが挙げられる。これまでの接合材料や積層構造では、ｎ型ＭＯＳかｐ型ＭＯＳのどちらか一方のみの接触抵抗を低減できたが、ｎ型ＭＯＳとｐ型ＭＯＳの両方の接触抵抗低減はできなかった。例えば、ｎ型ＭＯＳの接触抵抗低減のためには、金属電極とｎ型半導体層との間に形成される電子に対するエネルギー障壁高さ（電子障壁高さ）の低減が有効であり、ｐ型ＭＯＳの接触抵抗低減のためには、金属電極とｐ型半導体層との間に形成される正孔に対するエネルギー障壁高さ（正孔障壁高さ）の低減が有効である。しかし、通常、電子障壁高さが低減すると、正孔障壁高さが増大してしまい、正孔障壁高さを低減させると電子障壁高さが増大してしまう。つまり、ｎ型ＭＯＳとｐ型ＭＯＳに同じ接合材料や同じ積層構造を利用する限り、電子障壁高さと正孔障壁高さの両方の低減は両立し得なかった。そのため、ｎ型ＭＯＳには電子障壁高さ低減用の接合材料、ｐ型ＭＯＳには正孔障壁高さ低減用の別の接合材料、というようにＣＭＯＳに２種類の接合材料を使う必要があった。しかし、２種類の接合材料は、ＣＭＯＳ製造プロセスの繁雑さを招き、製造コストが高くなる課題があった。これを避けるために、従来は、ｎ型ＭＯＳとｐ型ＭＯＳに共通の接合材料（窒化チタンやチタン）が使われている。しかし、これらの接合材料では、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレイン接合部でのエネルギー障壁高さ低減は困難であり、接触抵抗低減に限界があった。
Various bonding materials and laminated structures have been proposed so far to reduce contact resistance. For example, titanium nitride, titanium, tantalum nitride, tantalum, silicon nitride and the like can be mentioned as the bonding material. Although the contact resistance of either n-type MOS or p-type MOS could be reduced with the conventional junction materials or the laminated structure, the contact resistance of both n-type MOS and p-type MOS could not be reduced. For example, in order to reduce the contact resistance of n-type MOS, it is effective to reduce the energy barrier height (electron barrier height) for electrons formed between the metal electrode and the n-type semiconductor layer. In order to reduce the contact resistance, it is effective to reduce the energy barrier height (hole barrier height) for holes formed between the metal electrode and the p-type semiconductor layer. However, in general, when the electron barrier height is reduced, the hole barrier height is increased, and when the hole barrier height is reduced, the electron barrier height is increased. That is, as long as the same junction material and the same laminated structure are used for the n-type MOS and the p-type MOS, the reduction of both the electron barrier height and the hole barrier height can not be compatible. Therefore, it is necessary to use two types of junction materials in CMOS, such as junction materials for reducing the electron barrier height for n-type MOS, another junction material for reducing the hole barrier height for p-type MOS, and so on. The However, the two types of bonding materials cause the complexity of the CMOS manufacturing process, and there is a problem that the manufacturing cost becomes high. In order to avoid this, conventionally, a joint material (titanium nitride or titanium) common to the n-type MOS and the p-type MOS is used. However, with these junction materials, it is difficult to reduce the height of the energy barrier at the source / drain junctions of both n-type MOS and p-type MOS, and there is a limit to the reduction of contact resistance.
本発明は、これらの問題を解決しようとするものであり、本発明は、微細化が可能で、かつ、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属電極接触部での接触抵抗の低減が可能な構造の半導体装置を提供することを目的とする。本発明は、ｎ型ＭＯＳとｐ型ＭＯＳに、共通の接合材料を用いて接触抵抗の低減することにより、ＣＭＯＳの性能を向上させた半導体装置を提供することを目的とする。本発明は、ＣＭＯＳ製造プロセスを簡素化して、製造コストを抑えることが可能な、半導体装置の製造方法を提供することを目的とする。
The present invention is intended to solve these problems, and the present invention can be miniaturized and the contact resistance at the metal electrode contact of the source / drain of both n-type MOS and p-type MOS. It is an object of the present invention to provide a semiconductor device having a structure capable of reducing the An object of the present invention is to provide a semiconductor device in which the performance of a CMOS is improved by reducing the contact resistance by using a common junction material for an n-type MOS and a p-type MOS. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of simplifying a CMOS manufacturing process and suppressing the manufacturing cost.
本発明は、前記目的を達成するために、以下の特徴を有するものである。
The present invention has the following features to achieve the above object.
（１） 金属電極、タングステンシリサイド膜、並びにシリコン層若しくはシリコンとカーボンの化合物層の順で積層された第１の積層構造と、前記金属電極、前記タングステンシリサイド膜、及びシリコンとゲルマニウムの化合物層の順で積層された第２の積層構造とを備え、前記タングステンシリサイド膜のシリコン／タングステンの組成比が４より大で１２以下であることを特徴とする半導体装置。
（２） 前記金属電極が、タングステン、窒化タングステン、チタン、窒化チタン、タンタル、窒化タンタル、ニッケル、コバルト、モリブデンのうちの少なくとも１つ以上であることを特徴とする前記（１）に記載の半導体装置。
（３） 前記シリコンとゲルマニウムの化合物層は、（ゲルマニウム）／（シリコン＋ゲルマニウム）の組成比が０より大で１以下であることを特徴とする前記（１）又は（２）に記載の半導体装置。
（４） 前記シリコンとカーボンの化合物層は、（カーボン）／（シリコン＋カーボン）の組成比が０より大で０．５以下であることを特徴とする前記（１）乃至（３）のいずれか１項に記載の半導体装置。
（５） 前記第１の積層構造における前記シリコン層又はシリコンとカーボンの前記化合物層が、ｎ型のキャリアタイプであり、前記第２の積層構造におけるシリコンとゲルマニウムの前記化合物層が、ｐ型のキャリアタイプであることを特徴とする前記（１）乃至（４）のいずれか１項に記載の半導体装置。
（６） 前記第１及び第２の積層構造の少なくともいずれか一方の積層構造が、２つ以上並列する構造であって、該並列する構造の、中間位置に金属と酸化膜と半導体層の順で積層されたＭＯＳ構造を備えていることを特徴とする前記（１）乃至（５）のいずれか１項に記載の半導体装置。
（７） 複数の前記第１の積層構造及び複数の第２の積層構造が金属配線によって接続された、ＣＭＯＳ構造を備えることを特徴とする前記（１）乃至（６）のいずれか１項記載の半導体装置。
（８） タングステンの原料ガスとシリコンの原料ガスを気相中で化学反応させることにより、シリコン／タングステンの組成比が４より大で１２以下の前駆体を気相中で作製した後に、前記前駆体を、シリコン層若しくはシリコンとカーボンの化合物層並びにシリコンとゲルマニウムの化合物層の上に堆積して、タングステンシリサイド膜を作製する工程と、金属電極を前記タングステンシリサイド膜上に作製する電極作製工程と、を備えることを特徴とする、前記（１）記載の半導体装置の製造方法。
（９） 前記電極作製工程は、前記タングステンの原料ガスと前記シリコンの原料ガスのうち少なくとも１つ以上の原料ガスを含む原料ガスを用いて、タングテン電極を前記タングステンシリサイド膜上に作製する工程であることを特徴とする、前記（８）記載の製造方法。 (1) A first laminated structure in which a metal electrode, a tungsten silicide film, and a silicon layer or a compound layer of silicon and carbon are laminated in order, a metal electrode, the tungsten silicide film, and a compound layer of silicon and germanium A semiconductor device comprising: a second stacked structure stacked in order; and a composition ratio of silicon / tungsten of the tungsten silicide film being greater than 4 and 12 or less.
(2) The semiconductor according to (1), wherein the metal electrode is at least one or more of tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, nickel, cobalt, and molybdenum. apparatus.
(3) The semiconductor according to (1) or (2), wherein the compound layer of silicon and germanium has a composition ratio of (germanium) / (silicon + germanium) of more than 0 and 1 or less. apparatus.
(4) In the compound layer of silicon and carbon, the composition ratio of (carbon) / (silicon + carbon) is more than 0 and 0.5 or less, any one of the above (1) to (3) The semiconductor device according toclaim 1.
(5) The silicon layer or the compound layer of silicon and carbon in the first laminated structure is an n-type carrier type, and the compound layer of silicon and germanium in the second laminated structure is a p-type The semiconductor device according to any one of (1) to (4), which is a carrier type.
(6) A structure in which at least one of the first and second laminated structures is arranged in parallel two or more, and the order of the metal, the oxide film, and the semiconductor layer in the middle position of the paralleled structure The semiconductor device according to any one of the above (1) to (5), which comprises a MOS structure stacked in the above.
(7) The device according to any one of (1) to (6), further comprising: a CMOS structure in which the plurality of first laminated structures and the plurality of second laminated structures are connected by metal wiring. Semiconductor devices.
(8) The chemical reaction of the tungsten source gas and the silicon source gas in the gas phase produces a precursor having a silicon / tungsten composition ratio of greater than 4 and 12 or less in the gas phase, Depositing a metal layer on a silicon layer or a compound layer of silicon and carbon and a compound layer of silicon and germanium to form a tungsten silicide film, and an electrode manufacturing step of forming a metal electrode on the tungsten silicide film; The method of manufacturing a semiconductor device according to the above (1), comprising:
(9) The electrode manufacturing step is a step of manufacturing a tungsten electrode on the tungsten silicide film using a source gas containing at least one source gas of the source gas of tungsten and a source gas of silicon. The manufacturing method according to (8), characterized in that
（２） 前記金属電極が、タングステン、窒化タングステン、チタン、窒化チタン、タンタル、窒化タンタル、ニッケル、コバルト、モリブデンのうちの少なくとも１つ以上であることを特徴とする前記（１）に記載の半導体装置。
（３） 前記シリコンとゲルマニウムの化合物層は、（ゲルマニウム）／（シリコン＋ゲルマニウム）の組成比が０より大で１以下であることを特徴とする前記（１）又は（２）に記載の半導体装置。
（４） 前記シリコンとカーボンの化合物層は、（カーボン）／（シリコン＋カーボン）の組成比が０より大で０．５以下であることを特徴とする前記（１）乃至（３）のいずれか１項に記載の半導体装置。
（５） 前記第１の積層構造における前記シリコン層又はシリコンとカーボンの前記化合物層が、ｎ型のキャリアタイプであり、前記第２の積層構造におけるシリコンとゲルマニウムの前記化合物層が、ｐ型のキャリアタイプであることを特徴とする前記（１）乃至（４）のいずれか１項に記載の半導体装置。
（６） 前記第１及び第２の積層構造の少なくともいずれか一方の積層構造が、２つ以上並列する構造であって、該並列する構造の、中間位置に金属と酸化膜と半導体層の順で積層されたＭＯＳ構造を備えていることを特徴とする前記（１）乃至（５）のいずれか１項に記載の半導体装置。
（７） 複数の前記第１の積層構造及び複数の第２の積層構造が金属配線によって接続された、ＣＭＯＳ構造を備えることを特徴とする前記（１）乃至（６）のいずれか１項記載の半導体装置。
（８） タングステンの原料ガスとシリコンの原料ガスを気相中で化学反応させることにより、シリコン／タングステンの組成比が４より大で１２以下の前駆体を気相中で作製した後に、前記前駆体を、シリコン層若しくはシリコンとカーボンの化合物層並びにシリコンとゲルマニウムの化合物層の上に堆積して、タングステンシリサイド膜を作製する工程と、金属電極を前記タングステンシリサイド膜上に作製する電極作製工程と、を備えることを特徴とする、前記（１）記載の半導体装置の製造方法。
（９） 前記電極作製工程は、前記タングステンの原料ガスと前記シリコンの原料ガスのうち少なくとも１つ以上の原料ガスを含む原料ガスを用いて、タングテン電極を前記タングステンシリサイド膜上に作製する工程であることを特徴とする、前記（８）記載の製造方法。 (1) A first laminated structure in which a metal electrode, a tungsten silicide film, and a silicon layer or a compound layer of silicon and carbon are laminated in order, a metal electrode, the tungsten silicide film, and a compound layer of silicon and germanium A semiconductor device comprising: a second stacked structure stacked in order; and a composition ratio of silicon / tungsten of the tungsten silicide film being greater than 4 and 12 or less.
(2) The semiconductor according to (1), wherein the metal electrode is at least one or more of tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, nickel, cobalt, and molybdenum. apparatus.
(3) The semiconductor according to (1) or (2), wherein the compound layer of silicon and germanium has a composition ratio of (germanium) / (silicon + germanium) of more than 0 and 1 or less. apparatus.
(4) In the compound layer of silicon and carbon, the composition ratio of (carbon) / (silicon + carbon) is more than 0 and 0.5 or less, any one of the above (1) to (3) The semiconductor device according to
(5) The silicon layer or the compound layer of silicon and carbon in the first laminated structure is an n-type carrier type, and the compound layer of silicon and germanium in the second laminated structure is a p-type The semiconductor device according to any one of (1) to (4), which is a carrier type.
(6) A structure in which at least one of the first and second laminated structures is arranged in parallel two or more, and the order of the metal, the oxide film, and the semiconductor layer in the middle position of the paralleled structure The semiconductor device according to any one of the above (1) to (5), which comprises a MOS structure stacked in the above.
(7) The device according to any one of (1) to (6), further comprising: a CMOS structure in which the plurality of first laminated structures and the plurality of second laminated structures are connected by metal wiring. Semiconductor devices.
(8) The chemical reaction of the tungsten source gas and the silicon source gas in the gas phase produces a precursor having a silicon / tungsten composition ratio of greater than 4 and 12 or less in the gas phase, Depositing a metal layer on a silicon layer or a compound layer of silicon and carbon and a compound layer of silicon and germanium to form a tungsten silicide film, and an electrode manufacturing step of forming a metal electrode on the tungsten silicide film; The method of manufacturing a semiconductor device according to the above (1), comprising:
(9) The electrode manufacturing step is a step of manufacturing a tungsten electrode on the tungsten silicide film using a source gas containing at least one source gas of the source gas of tungsten and a source gas of silicon. The manufacturing method according to (8), characterized in that
本発明では、特定の組成比のタングステンシリサイド膜が、ｎ型ＭＯＳにおけるｎ型シリコン層若しくはｎ型シリコンとカーボンの化合物層と、ｐ型ＭＯＳにおけるｐ型シリコンゲルマニウム層若しくはｐ型ゲルマニウム層、の両方のフェルミレベルの調整機能を担い、ｎ型ＭＯＳの電子障壁高さとｐ型ＭＯＳの正孔障壁高さの両方を低減し、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属電極接触部の接触抵抗を低減することにより、ＣＭＯＳの駆動力を向上させることができる。よって、集積回路のさらなる微細化及び性能の向上を図れる。
In the present invention, a tungsten silicide film having a specific composition ratio is both an n-type silicon layer or a compound layer of n-type silicon and carbon in an n-type MOS and a p-type silicon germanium layer or a p-type germanium layer in a p-type MOS. Of the electron barrier height of the n-type MOS and the hole barrier height of the p-type MOS, and both the n-type MOS and the p-type MOS source / drain metal electrode contact The driving force of the CMOS can be improved by reducing the contact resistance of Therefore, further miniaturization and performance improvement of the integrated circuit can be achieved.
ゲルマニウム層は勿論、シリコンゲルマニウム層の（ゲルマニウム）／（シリコン＋ゲルマニウム）の組成比が０より大で１以下であれば、正孔障壁高さの低減効果がある。
Of course, if the composition ratio of (germanium) / (silicon + germanium) in the silicon germanium layer is greater than 0 and not more than 1 in the germanium layer, the hole barrier height can be reduced.
第１の積層構造において、ｎ型シリコンとカーボンの化合物層を用いる場合、ｎ型シリコン層の場合と同様、タングステンシリサイド膜がフェルミレベルのピンニング緩和を行い、シリコンとカーボンの化合物層に対する電子障壁高さを低減する。（カーボン）／（シリコン＋カーボン）の組成比が０より大で０．５以下である場合は、ＣＭＯＳの駆動力をより向上させることができる。
When a compound layer of n-type silicon and carbon is used in the first laminated structure, the tungsten silicide film performs pinning relaxation of Fermi level as in the case of the n-type silicon layer, and electron barrier height to the compound layer of silicon and carbon Reduce the When the composition ratio of (carbon) / (silicon + carbon) is greater than 0 and 0.5 or less, the driving power of the CMOS can be further improved.
本発明の製造方法では、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属電極接触部に、共通のタングステンシリサイド膜を形成することにより、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属電極接触部での接触抵抗を低減できるので、製造工程の共通化、工程数の削減や簡素化が図れる。タングステンシリサイド膜の作製後に、タングステンシリサイド膜と同じ原料ガスを利用してタングステンシリサイド膜上部にタングステン電極を作製することが可能であるため、製造コストの上昇を抑えことができる。
In the manufacturing method of the present invention, a common tungsten silicide film is formed at the metal electrode contact portion of both the n-type MOS and the p-type MOS source / drain so that both the n-type MOS and the p-type MOS source / Since the contact resistance at the metal electrode contact portion of the drain can be reduced, the manufacturing process can be made common, and the number of processes can be reduced and simplified. After the formation of the tungsten silicide film, the tungsten electrode can be formed on the upper portion of the tungsten silicide film by using the same source gas as the tungsten silicide film, so that the increase in manufacturing cost can be suppressed.
本発明の実施形態について以下説明する。
Embodiments of the present invention will be described below.
本発明者らは、金属電極、タングステンシリサイド膜、シリコン層順で積層された第１の積層構造と、前記金属電極、前記タングステンシリサイド膜、及びシリコンとゲルマニウムの化合物層の順で積層された第２の積層構造とを備える構造を実現することにより、微細化が可能で、かつ、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属電極接触部での接触抵抗の低減が可能な構造を提供するものである。また、第１の積層構造におけるシリコン層に替えて、シリコンとカーボンの化合物層を用いた第１の積層構造でも同様である。前記タングステンシリサイド膜のシリコン／タングステンの組成比が４より大で１２以下である。
The inventors of the present invention have a first laminated structure in which a metal electrode, a tungsten silicide film, and a silicon layer are sequentially laminated, and the metal electrode, the tungsten silicide film, and a compound layer of silicon and germanium in this order. By realizing the structure including the two stacked structures, it is possible to miniaturize and reduce the contact resistance at the metal electrode contact portion of both the n-type MOS and the p-type MOS source / drain. To provide The same applies to a first stacked structure using a compound layer of silicon and carbon instead of the silicon layer in the first stacked structure. The silicon / tungsten composition ratio of the tungsten silicide film is greater than 4 and 12 or less.
図１は、本発明の実施形態の半導体装置の基本構造を説明する断面模式図である。半導体装置の基本構造は、少なくとも、金属電極１、タングステンシリサイド膜２、シリコン層３の順で積層された第１の積層構造、及び金属電極１１、タングステンシリサイド膜１２、シリコンゲルマニウム層１３の順で積層された第２の積層構造を備える。
FIG. 1 is a schematic cross-sectional view for explaining the basic structure of a semiconductor device according to an embodiment of the present invention. The basic structure of the semiconductor device includes at least a first laminated structure in which a metal electrode 1, a tungsten silicide film 2 and a silicon layer 3 are laminated in this order, and a metal electrode 11, a tungsten silicide film 12 and a silicon germanium layer 13 in this order. A second laminated structure is provided.
図２は、図１と同様の半導体装置の１つの具体形状の断面模式図である。本図の半導体装置は、金属電極１、タングステンシリサイド膜２、シリコン層３の順で積層された第１の積層構造と、金属電極１１、タングステンシリサイド膜１２、シリコンゲルマニウム層１３の順で積層された第２の積層構造とを備え、タングステンシリサイド膜２及び１２が金属電極１及び１１を囲った構造を備える。
FIG. 2 is a schematic cross-sectional view of one specific shape of the semiconductor device similar to FIG. In the semiconductor device of this figure, a first laminated structure in which a metal electrode 1, a tungsten silicide film 2 and a silicon layer 3 are laminated in this order, and a metal electrode 11, a tungsten silicide film 12 and a silicon germanium layer 13 in this order. And a structure in which the tungsten silicide films 2 and 12 surround the metal electrodes 1 and 11, respectively.
図３は、図２の、タングステンシリサイド膜（２、１２）で囲った構造を備える電極（１、１１）部分の、図２と直交する面の断面模式図である。
FIG. 3 is a schematic cross-sectional view of a plane orthogonal to FIG. 2 of the electrode (1, 11) portion having the structure surrounded by the tungsten silicide film (2, 12) in FIG.
前記金属電極は、タングステン、窒化タングステン、チタン、窒化チタン、タンタル、窒化タンタル、ニッケル、コバルト、モリブデンのうちの少なくとも１つ以上であることが好ましい。
The metal electrode is preferably at least one or more of tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, nickel, cobalt, and molybdenum.
前記シリコンとゲルマニウムの化合物層は、（ゲルマニウム）／（シリコン＋ゲルマニウム）の組成比が０より大で１以下であることが好ましい。即ち、前記シリコンとゲルマニウムの化合物層は、ゲルマニウム層、又はシリコン及びゲルマニウムからなる化合物層である。さらに、ｐ型ＭＯＳの正孔障壁高さをより低減し、ＣＭＯＳの駆動力を向上させる場合は、前記組成比が、１に近い値であることがより好ましい。
The compound layer of silicon and germanium preferably has a composition ratio of (germanium) / (silicon + germanium) of more than 0 and 1 or less. That is, the compound layer of silicon and germanium is a germanium layer or a compound layer composed of silicon and germanium. Furthermore, when the hole barrier height of the p-type MOS is further reduced and the drivability of the CMOS is improved, it is more preferable that the composition ratio be a value close to one.
前記シリコンとカーボンの化合物層は、（カーボン）／（シリコン＋カーボン）の組成比が０より大で０．５以下であることが好ましい。さらに、ＣＭＯＳの駆動力を向上させる場合は、前記組成比が、０．５に近い値であることがより好ましい。
The compound layer of silicon and carbon preferably has a composition ratio of (carbon) / (silicon + carbon) of more than 0 and 0.5 or less. Furthermore, in order to improve the driving power of CMOS, it is more preferable that the composition ratio be a value close to 0.5.
前記第１の積層構造における前記シリコン層又はシリコンとカーボンの前記化合物層が、ｎ型のキャリアタイプであり、前記第２の積層構造におけるシリコンとゲルマニウムの前記化合物層が、ｐ型のキャリアタイプであり、これらの積層構造を用いて、ＣＭＯＳ構造を構成することが好ましい。
The silicon layer or the compound layer of silicon and carbon in the first laminated structure is an n-type carrier type, and the compound layer of silicon and germanium in the second laminated structure is a p-type carrier type It is preferable to construct a CMOS structure using these stacked structures.
図４は．金属電極１、タングステンシリサイド膜２、シリコン層３の順で積層された第１の積層構造と、金属電極１１、タングステンシリサイド膜１２、シリコンゲルマニウム層１３の順で積層された第２の積層構造と、さらに、シリコン層３とシリコンゲルマニウム層１３とに接する、シリコン層４を備えた半導体装置の断面模式図である。
Figure 4. A first laminated structure in which metal electrode 1, tungsten silicide film 2 and silicon layer 3 are laminated in order, and a second laminated structure in which metal electrode 11, tungsten silicide film 12 and silicon germanium layer 13 are laminated in order FIG. 6 is a schematic cross-sectional view of a semiconductor device further including a silicon layer 4 in contact with the silicon layer 3 and the silicon germanium layer 13.
本発明の実施形態の半導体装置の代表例がＣＭＯＳである。ＣＭＯＳにおけるｎ型ＭＯＳのソース／ドレインに、金属電極、タングステンシリサイド膜、ｎ型シリコン層の順で積層された第１の積層構造を用いる。ここで、ｎ型シリコン層に替えて、シリコンとカーボンの化合物層を用いてもよい。第１の積層構造のシリコンとカーボンの化合物層に接してｎ型シリコン層をさらに備えてもよい。この場合、金属電極、タングステンシリサイド膜、シリコンとカーボンの化合物層、ｎ型シリコン層の順となる。ＣＭＯＳにおけるｐ型ＭＯＳのソース／ドレインに、金属電極、タングステンシリサイド膜、ゲルマニウム層の順で積層された第２の積層構造を用いる。ここで、ゲルマニウム層は、シリコンとゲルマニウムの化合物層でもよい。第２の積層構造のゲルマニウム層に接してｐ型シリコン層をさらに備えることが好ましい。この場合、金属電極、タングステンシリサイド膜、ゲルマニウム層、ｐ型シリコン層の順となる。
A representative example of the semiconductor device according to the embodiment of the present invention is a CMOS. A first laminated structure in which a metal electrode, a tungsten silicide film, and an n-type silicon layer are laminated in order of source / drain of n-type MOS in CMOS is used. Here, instead of the n-type silicon layer, a compound layer of silicon and carbon may be used. An n-type silicon layer may be further provided in contact with the silicon-carbon compound layer of the first laminated structure. In this case, the metal electrode, the tungsten silicide film, the compound layer of silicon and carbon, and the n-type silicon layer are in this order. A second stacked structure in which a metal electrode, a tungsten silicide film, and a germanium layer are stacked in this order is used as the source / drain of p-type MOS in CMOS. Here, the germanium layer may be a compound layer of silicon and germanium. Preferably, a p-type silicon layer is further provided in contact with the germanium layer of the second stacked structure. In this case, the metal electrode, the tungsten silicide film, the germanium layer, and the p-type silicon layer are in this order.
よって、チャネル部にシリコンを有するＣＭＯＳの、ｎ型ＭＯＳとｐ型ＭＯＳのソース／ドレインに共通のタングステンシリサイド膜を用いることにより、ｎ型ＭＯＳとｐ型ＭＯＳのソース／ドレインの金属電極接触部の両方の接触抵抗を低減でき、ＣＭＯＳの駆動力を向上させることができる。共通のタングステンシリサイド膜のシリコン／タングステン組成比は、４より大で１２以下である。
Therefore, by using a common tungsten silicide film for the source / drain of n-type MOS and p-type MOS of CMOS having silicon in the channel portion, the metal electrode contact portion of the source / drain of n-type MOS and p-type MOS Both contact resistances can be reduced, and the driving power of the CMOS can be improved. The silicon / tungsten composition ratio of the common tungsten silicide film is greater than four and less than or equal to twelve.
図５は、ｎ型ＭＯＳの断面模式図である。ｎ型ＭＯＳは、金属電極１、タングステンシリサイド膜２、ｎ型のシリコン層３の順で積層された２つの第１の積層構造の間に、金属電極（ゲート）５（Ｍ）、酸化物６（Ｏ）、ｐ型のシリコン層４（Ｓ）の順で積層されたＭＯＳ構造を有する。
FIG. 5 is a schematic cross-sectional view of an n-type MOS. The n-type MOS is formed of a metal electrode (gate) 5 (M), an oxide 6 between two first laminated structures laminated in the order of the metal electrode 1, the tungsten silicide film 2, and the n-type silicon layer 3. (O), has a MOS structure in which a p-type silicon layer 4 (S) is stacked in this order.
図６は、ｐ型ＭＯＳの断面模式図である。ｐ型ＭＯＳは、金属電極１１、タングステンシリサイド膜１２、シリコンゲルマニウム層又はゲルマニウム層１３の順で積層された２つの第２の積層構造の間に、金属電極（ゲート）１５（Ｍ）、酸化物１６（Ｏ）、シリコン層１４（Ｓ）の順で積層されたＭＯＳ構造を有する。シリコン層１４はｎ型のキャリアを有しており、シリコンゲルマニウム層又はゲルマニウム層１３はｐ型のキャリアを有している。
FIG. 6 is a schematic cross-sectional view of a p-type MOS. In the p-type MOS, a metal electrode (gate) 15 (M), an oxide between two second laminated structures laminated in the order of the metal electrode 11, the tungsten silicide film 12, the silicon germanium layer or the germanium layer 13; It has a MOS structure laminated in the order of 16 (O) and silicon layer 14 (S). The silicon layer 14 has n-type carriers, and the silicon germanium layer or germanium layer 13 has p-type carriers.
図７は、ｎ型ＭＯＳとｐ型ＭＯＳを隣接させた相補型ＭＯＳ（ＣＭＯＳ）構造の断面模式図である。ｎ型ＭＯＳ部分は、図５と同様であり、ｐ型ＭＯＳ部分は、図６と同様である。
FIG. 7 is a schematic cross-sectional view of a complementary MOS (CMOS) structure in which an n-type MOS and a p-type MOS are adjacent to each other. The n-type MOS portion is similar to FIG. 5, and the p-type MOS portion is similar to FIG.
本発明の実施形態の半導体装置の製造は、タングステンの原料ガスとシリコンの原料ガスを気相中で化学反応させることにより、シリコン／タングステンの組成比が４より大で１２以下の前駆体を気相中で作製した後に、前記前駆体を、シリコン層若しくはシリコンとカーボンの化合物層又はシリコンとゲルマニウムの化合物層の上に堆積して、タングステンシリサイド膜を作製する工程と、金属電極を前記タングステンシリサイド膜上に作製する電極作製工程とを、少なくとも備える。ここで、タングステンシリサイド膜を作製する工程後に、所望の電子障壁高さと正孔障壁高さの両方を低減するための熱処理工程を設けることが、好ましい。熱処理条件は、真空、窒素等の不活性、水素等の還元雰囲気下で、４００℃以上７００℃以下の範囲が望ましい。また、電極作製工程は、タングステンシリサイド膜を作製する工程で用いたタングステンの原料ガスとシリコンの原料ガスのうち少なくとも１つ以上の原料ガスを含む原料ガスを用いて、タングテン電極を前記タングステンシリサイド膜上に作製することもできる。
In the manufacture of the semiconductor device according to the embodiment of the present invention, a precursor gas of silicon / tungsten having a composition ratio of more than 4 and 12 or less is produced by chemically reacting a tungsten source gas and a silicon source gas in a gas phase. Depositing the precursor on a silicon layer or a compound layer of silicon and carbon or a compound layer of silicon and germanium to form a tungsten silicide film; And at least an electrode producing step for producing on a membrane. Here, it is preferable to provide a heat treatment step for reducing both the desired electron barrier height and the hole barrier height after the step of forming the tungsten silicide film. The heat treatment conditions are preferably in the range of 400 ° C. to 700 ° C. in vacuum, inert atmosphere such as nitrogen, or reducing atmosphere such as hydrogen. Further, in the electrode manufacturing step, the tungsten silicide film is formed using the raw material gas containing at least one or more raw material gases of the raw material gas of tungsten and the raw material gas of silicon used in the step of manufacturing the tungsten silicide film. It can also be made on top.
（第１の実施形態）
本発明の第１の実施形態の半導体装置について、図を参照して以下説明する。第１の積層構造がシリコン層を備えるＣＭＯＳの場合を、代表例として説明する。本実施形態のＣＭＯＳにおけるｎ型ＭＯＳのソース／ドレインの金属電極接触部は、金属電極、タングステンシリサイド膜、ｎ型シリコン層の積層構造を備える。本実施形態のＣＭＯＳにおけるｐ型ＭＯＳのソース／ドレインの金属電極接触部は、金属電極、タングステンシリサイド膜、シリコンとゲルマニウムの化合物層（又はゲルマニウム層）の積層構造を備える。 First Embodiment
The semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings. The case of a CMOS in which the first stacked structure includes a silicon layer will be described as a representative example. The metal electrode contact portion of the source / drain of the n-type MOS in the CMOS of the present embodiment has a laminated structure of a metal electrode, a tungsten silicide film, and an n-type silicon layer. The metal electrode contact portion of the source / drain of the p-type MOS in the CMOS of the present embodiment has a laminated structure of a metal electrode, a tungsten silicide film, and a compound layer (or germanium layer) of silicon and germanium.
本発明の第１の実施形態の半導体装置について、図を参照して以下説明する。第１の積層構造がシリコン層を備えるＣＭＯＳの場合を、代表例として説明する。本実施形態のＣＭＯＳにおけるｎ型ＭＯＳのソース／ドレインの金属電極接触部は、金属電極、タングステンシリサイド膜、ｎ型シリコン層の積層構造を備える。本実施形態のＣＭＯＳにおけるｐ型ＭＯＳのソース／ドレインの金属電極接触部は、金属電極、タングステンシリサイド膜、シリコンとゲルマニウムの化合物層（又はゲルマニウム層）の積層構造を備える。 First Embodiment
The semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings. The case of a CMOS in which the first stacked structure includes a silicon layer will be described as a representative example. The metal electrode contact portion of the source / drain of the n-type MOS in the CMOS of the present embodiment has a laminated structure of a metal electrode, a tungsten silicide film, and an n-type silicon layer. The metal electrode contact portion of the source / drain of the p-type MOS in the CMOS of the present embodiment has a laminated structure of a metal electrode, a tungsten silicide film, and a compound layer (or germanium layer) of silicon and germanium.
本実施形態は、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属電極接触部でのエネルギー障壁高さを低減することができたものである。本発明のエネルギー障壁高さの低減の機構は、タングステンシリサイド膜によるフェルミレベルの調整機能に基づいている。以下、詳しく説明する。
In the present embodiment, the height of the energy barrier at the metal electrode contact portion of both the n-type MOS and the p-type MOS source / drain can be reduced. The mechanism for reducing the energy barrier height of the present invention is based on the adjustment function of the Fermi level by the tungsten silicide film. Details will be described below.
通常の、金属電極とシリコン層の積層構造では、シリコンのミッドギャップよりもやや価電子帯端寄りに存在する電荷中性準位に、金属電極のフェルミレベルがピンニングされるために、電子障壁高さが高くなる傾向があり、正孔障壁高さが低くなる傾向がある。例えば、タングステン電極とｎ型シリコンが直接接合した場合には、電子障壁高さは約０．６８ｅＶを示し、タングテン電極とｐ型シリコンが直接接合した場合には、正孔障壁高さは約０．４３ｅＶを示す。
In the conventional laminated structure of the metal electrode and the silicon layer, the electron barrier height is high because the Fermi level of the metal electrode is pinned to the charge neutral level which is slightly closer to the valence band edge than the silicon mid gap. Tends to be high and the hole barrier height tends to be low. For example, the electron barrier height is about 0.68 eV when the tungsten electrode and n-type silicon are directly bonded, and the hole barrier height is about 0 when the tungsten electrode and p-type silicon are directly bonded. It shows .43 eV.
本実施形態のｎ型ＭＯＳにおいては、タングステンシリサイド膜がフェルミレベルのピンニング緩和を行い、ｎ型Ｓｉに対する電子障壁高さを低減することができる。例えば、タングステン電極、タングステンシリサイド膜（シリコン／タングステン組成比＝１２）、ｎ型シリコン層の順で積層された積層構造では、電子障壁高さが０．３２ｅＶまで低減する。この低減した電子障壁高さは、後述する、窒素雰囲気下で３０分間、６００℃の熱処理を行った後でも維持される。また、熱処理を行わなくても、電子障壁高さを低減することができるが、後述するｐ型ＭＯＳの低い正孔障壁高さとｎ型ＭＯＳの低い電子障壁高さの両方を実現するためには、ＣＭＯＳへの６００℃程度の熱処理工程が必要となる。
In the n-type MOS of this embodiment, the tungsten silicide film can perform pinning relaxation at the Fermi level, and the height of the electron barrier to n-type Si can be reduced. For example, in a stacked structure in which a tungsten electrode, a tungsten silicide film (silicon / tungsten composition ratio = 12), and an n-type silicon layer are stacked in this order, the electron barrier height is reduced to 0.32 eV. The reduced electron barrier height is maintained even after heat treatment at 600 ° C. for 30 minutes in a nitrogen atmosphere described later. Although the electron barrier height can be reduced without heat treatment, in order to realize both the low hole barrier height of the p-type MOS and the low electron barrier height of the n-type MOS described later. And a heat treatment process at about 600.degree. C. to the CMOS.
また、シリコン層は、通常の単結晶シリコンよりも圧縮歪あるいは引っ張りひずみを持った結晶構造を有していても、同様の効果を奏する。さらに、シリコン層は、ｎタイプのキャリアを有する半導体であるため、不純物元素として、リン（Ｐ）、ヒソ（Ａｓ）、アンチモン（Ｓｂ）などが入っている。
The same effect can be obtained even if the silicon layer has a crystal structure having a compressive strain or a tensile strain than ordinary single crystal silicon. Further, since the silicon layer is a semiconductor having n-type carriers, phosphorus (P), arsenic (As), antimony (Sb), and the like are contained as impurity elements.
本実施形態のｐ型ＭＯＳにおいては、タングステンシリサイド膜とシリコンゲルマニウム層又はゲルマニウム層の積層構造を作製後に熱処理を行うことで、正孔障壁高さを低減することができる。また、シリコンゲルマニウム層又はゲルマニウム層に接してｐ型シリコン層をさらに備えても、同様の効果を得ることができる。熱処理前においては、タングステンシリサイド膜が、金属電極のフェルミレベルのピンニング緩和を行い、シリコンゲルマニウム層又はゲルマニウム層に対する正孔障壁高さは高い値を示す。例えば、タングステン電極、タングステンシリサイド膜（シリコン／タングステン組成比＝１２）、ゲルマニウム層、ｐ型シリコン層の順で積層された積層構造の熱処理前の正孔障壁高さは、０．６８ｅＶを示す。一方、熱処理後においては、フェルミレベルが、シリコンゲルマニウム層又はゲルマニウム層の価電子帯端近傍にピンニングされて、正孔障壁高さが低減する。例えば、タングステン電極、タングステンシリサイド膜（シリコン／タングステン組成比＝１２）、ゲルマニウム層、ｐ型シリコン層の順で積層された積層構造に、窒素雰囲気下で３０分間６００℃の熱処理を行うことにより、正孔障壁高さを０．５１ｅＶまで低減することができる。この熱処理後の正孔障壁高さの低減効果は、熱処理により、シリコンゲルマニウム層又はゲルマニウム層と、タングステンシリサイド膜の界面で、相互拡散が起きて、原子構造が変化していることに起因する。シリコンゲルマニウム層の（ゲルマニウム）／（シリコン＋ゲルマニウム）の組成比が１に近い方が、相互拡散が起きやすいが、シリコンゲルマニウム層の（ゲルマニウム）／（シリコン＋ゲルマニウム）の組成比が０に近くても、相互拡散が起きるため、正孔障壁高さの低減効果を十分に得ることができる。よって、前記組成比が０より大で１以下であれば、正孔障壁高さの低減効果がある。
In the p-type MOS of the present embodiment, the hole barrier height can be reduced by performing heat treatment after fabricating a stacked structure of a tungsten silicide film and a silicon germanium layer or a germanium layer. The same effect can be obtained by further providing a p-type silicon layer in contact with the silicon germanium layer or the germanium layer. Before heat treatment, the tungsten silicide film reduces the Fermi level pinning of the metal electrode, and the hole barrier height relative to the silicon germanium layer or germanium layer shows a high value. For example, the hole barrier height before heat treatment of a stacked structure in which a tungsten electrode, a tungsten silicide film (silicon / tungsten composition ratio = 12), a germanium layer, and a p-type silicon layer are stacked in this order indicates 0.68 eV. On the other hand, after heat treatment, the Fermi level is pinned near the valence band edge of the silicon germanium layer or the germanium layer to reduce the hole barrier height. For example, heat treatment is performed at 600 ° C. for 30 minutes in a nitrogen atmosphere on a stacked structure in which a tungsten electrode, a tungsten silicide film (silicon / tungsten composition ratio = 12), a germanium layer, and a p-type silicon layer are stacked in this order The hole barrier height can be reduced to 0.51 eV. The reduction effect of the hole barrier height after the heat treatment is caused by the interdiffusion occurring at the interface between the silicon germanium layer or the germanium layer and the tungsten silicide film by the heat treatment to change the atomic structure. When the (germanium) / (silicon + germanium) composition ratio of the silicon germanium layer is closer to 1 interdiffusion is likely to occur, but the (germanium) / (silicon + germanium) composition ratio of the silicon germanium layer is closer to 0 However, since the interdiffusion occurs, the reduction effect of the hole barrier height can be sufficiently obtained. Therefore, if the composition ratio is greater than 0 and 1 or less, the hole barrier height can be reduced.
また、Ｐ型ＭＯＳでは、シリコンゲルマニウム層又はゲルマニウム層は、隣接するシリコン層に圧縮歪を加えるために、広く用いられている。この際、シリコンゲルマニウム層又はゲルマニウム層も通常の結晶状態からひずんだ状態となるが、この場合も、同様の正孔障壁高さの低減効果を奏する。また、シリコンゲルマニウム層又はゲルマニウム層は、ｐタイプのキャリアを有する半導体であるため、不純物元素として、ボロン（Ｂ）、アルミニウム（Ａｌ）、ガリウム（Ｇａ）などが入っている場合や、結晶欠陥や原子空孔をアクセプタとして利用している場合がある。
In P-type MOS, a silicon germanium layer or a germanium layer is widely used to apply compressive strain to an adjacent silicon layer. At this time, the silicon germanium layer or the germanium layer is also in a distorted state from the normal crystalline state, but also in this case, the same reduction effect of the hole barrier height is exerted. In addition, since a silicon germanium layer or a germanium layer is a semiconductor having a p-type carrier, when boron (B), aluminum (Al), gallium (Ga), or the like is contained as an impurity element, a crystal defect or There are cases where atomic vacancies are used as acceptors.
金属電極にタングステン電極を用いた場合の、エネルギー障壁とシリコン／タングステン組成比との関係について調べた。
The relationship between the energy barrier and the silicon / tungsten composition ratio was investigated when a tungsten electrode was used as the metal electrode.
図８は、タングステン（Ｗ）電極、タングステンシリサイドＷＳｉｎ膜、シリコン（Ｓｉ）層の順で積層されたショットキーダイオードの電流（Ｉ）－電圧（Ｖ）特性を示す図である。シリコン層のキャリアタイプは、左図がｎ型、右図がｐ型である。通常の金属電極とキャリア密度の低い半導体層の積層構造は、ショットキーダイオードと呼ばれ、積層界面にはエネルギー障壁が形成されて、整流特性を示す。本図の左側の図中の線は、下から、線ＡはＷ電極／ｎ型Ｓｉ、線ＢはＷ電極／ＷＳｉｎ膜（ｎ＝３）／ｎ型Ｓｉ、線ＣはＷ電極／ＷＳｉｎ膜（ｎ＝１２）／ｎ型Ｓｉである。本図の右側の図中の線は、上から、線ＤはＷ電極／ｐ型Ｓｉ、線ＥはＷ電極／ＷＳｉｎ膜（ｎ＝３）／ｐ型Ｓｉ、線ＦはＷ電極／ＷＳｉｎ膜（ｎ＝１２）／ｐ型Ｓｉである。
FIG. 8 is a diagram showing current (I) -voltage (V) characteristics of a Schottky diode stacked in the order of a tungsten (W) electrode, a tungsten silicide WSi n film, and a silicon (Si) layer. The carrier type of the silicon layer is n-type on the left and p-type on the right. A stacked structure of a normal metal electrode and a semiconductor layer with a low carrier density is called a Schottky diode, and an energy barrier is formed at the stacked interface to exhibit rectification characteristics. In the figure on the left side of the figure, from the bottom, line A is W electrode / n-type Si, line B is W electrode / WSi n film (n = 3) / n-type Si, line C is W electrode / WSi n film (n = 12) / n-type Si. The lines in the right side of the figure are from the top, line D is W electrode / p-type Si, line E is W electrode / WSi n film (n = 3) / p-type Si, and line F is W electrode / WSi It is n film (n = 12) / p type Si.
図９は、タングステン電極、シリコン層の順で積層されたショットキーダイオードと、タングステン電極、タングステンシリサイド膜、ｎ型シリコン層の順で積層されたショットキーダイオードと、タングステン電極、タングステンシリサイド膜、ゲルマニウム層、ｐ型シリコン層の順で積層されたショットキーダイオードの、エネルギー障壁高さとタングステンシリサイド膜の組成比の関係を示した図である。
FIG. 9 shows a Schottky diode laminated in the order of a tungsten electrode and a silicon layer, a Schottky diode laminated in the order of a tungsten electrode, a tungsten silicide film and an n-type silicon layer, a tungsten electrode, a tungsten silicide film and germanium It is the figure which showed the relationship between the energy barrier height and the composition ratio of a tungsten silicide film | membrane of the Schottky diode laminated | stacked in order of a layer and a p-type silicon layer.
図８及び図９によれば、次のことが分かる。本実施形態の、タングステン電極、タングステンシリサイド膜、シリコンの順で積層されたショットキーダイオードでは、タングステンシリサイド膜の組成比を変えることにより、積層界面に形成される障壁高さを調整することが可能である。例えば、ｎ型シリコン対する電子障壁高さは、Ｗ電極／ｎ型Ｓｉの積層構造では、０．６８ｅＶとなり、Ｗ電極／ＷＳｉｎ膜（ｎ＝３）／ｎ型Ｓｉの積層構造では、０．６０ｅＶとなり、Ｗ電極／ＷＳｉｎ膜（ｎ＝１２）／ｎ型Ｓｉの積層構造では、０．３２ｅＶとなる。一方、タングステン電極、タングステンシリサイド膜、ｐ型シリコンの順で積層されたショットキーダイオードでは、ｐ型シリコンに対する正孔障壁高さを調整することができる。例えば、正孔障壁高さは、Ｗ電極／ｐ型Ｓｉの積層構造では０．４２ｅＶとなり、Ｗ電極／ＷＳｉｎ膜（ｎ＝３）／ｐ型Ｓｉの積層構造では、０．４８ｅＶとなり、Ｗ電極／ＷＳｉｎ膜（ｎ＝１２）／ｐ型Ｓｉの積層構造では、０．６８ｅＶとなる。以上の障壁高さは、電流－電圧測定と容量－電圧測定から求めることができる。
According to FIGS. 8 and 9, the following can be understood. In the Schottky diode in which the tungsten electrode, the tungsten silicide film, and the silicon are stacked in this order according to this embodiment, it is possible to adjust the barrier height formed on the stacked interface by changing the composition ratio of the tungsten silicide film. It is. For example, the electron barrier height for n-type silicon is 0.68 eV in the laminated structure of W electrode / n-type Si, and in the laminated structure of W electrode / WSi n film (n = 3) / n-type Si, 0. 60eV next, the multilayer structure of W electrodes / WSi n film (n = 12) / n-type Si, the 0.32 eV. On the other hand, in the case of a Schottky diode stacked in the order of a tungsten electrode, a tungsten silicide film, and p-type silicon, the hole barrier height with respect to p-type silicon can be adjusted. For example, a hole barrier height, becomes 0.42eV is a stacked structure of W electrode / p-type Si, the multilayer structure of W electrodes / WSi n film (n = 3) / p-type Si, 0.48 eV becomes, W In the laminated structure of electrode / WSi n film (n = 12) / p type Si, it is 0.68 eV. The above barrier height can be determined from current-voltage measurement and capacitance-voltage measurement.
よって、タングステン電極、タングステンシリサイド膜、シリコン層の順で積層されたショットキーダイオードにおいて、タングステンシリサイド膜のシリコン／タングステン組成比を増大させることで、ｎ型シリコンに対する電子障壁高さを減少させて、ｐ型シリコンに対する正孔障壁高さを増大させることができる。また、同じ組成比に対する電子と正孔の障壁高さの合計は、シリコンのバンドギャップの１．１ｅＶに近い値を示す。また、ｐ型シリコン層とタングステンシリサイド膜との間にゲルマニウム層を挿入することで、正孔障壁高さを０．５１ｅＶまで低減することができる。
Therefore, in a Schottky diode in which a tungsten electrode, a tungsten silicide film, and a silicon layer are stacked in this order, the height of the electron barrier to n-type silicon is reduced by increasing the silicon / tungsten composition ratio of the tungsten silicide film. The hole barrier height for p-type silicon can be increased. Further, the sum of the barrier heights of electrons and holes for the same composition ratio shows a value close to 1.1 eV of the band gap of silicon. Further, the hole barrier height can be reduced to 0.51 eV by inserting a germanium layer between the p-type silicon layer and the tungsten silicide film.
以上をまとめると、タングステン電極を用いたＣＭＯＳ構造のｎ－ＭＯＳ及びｐ－ＭＯＳのバンド模式図は、例えば、図１０のように図示できる。図１０は、タングステン電極／タングステンシリサイド膜／シリコン層の順で積層されたｎ型ＭＯＳの積層構造と、タングステン電極／タングステンシリサイド膜／ゲルマニウム層／シリコン層の順で積層されたｐ型ＭＯＳの積層構造のバンド模式図である。
Summarizing the above, a band schematic diagram of an n-MOS and p-MOS of a CMOS structure using a tungsten electrode can be illustrated, for example, as shown in FIG. FIG. 10 shows a stacked structure of n-type MOS stacked in the order of tungsten electrode / tungsten silicide film / silicon layer, and a stacked structure of p-type MOS stacked in the order of tungsten electrode / tungsten silicide film / germanium layer / silicon layer It is a band schematic diagram of a structure.
〈ＣＭＯＳの製造方法〉
本実施形態のＣＭＯＳの製造方法について、ソース／ドレインの金属電極接触部の構造の製造方法を中心に、以下説明する。以下に説明するソース／ドレインの金属電極接触部の構造及び電子障壁高さ調整のための処理以外は、通常のＣＭＯＳの製造方法を適宜採用することができる。
（工程１） ソース／ドレインの金属電極接触部の構造の形成の前段階として、ｎ型ＭＯＳ構造のためのｎ型シリコン層と、ｐ型ＭＯＳ構造のためのシリコンゲルマニウム層を形成する工程。
（工程２） ｎ型ＭＯＳ構造のためのｎ型シリコン層と、ｐ型ＭＯＳ構造のためのシリコンゲルマニウム層とに、タングステンシリサイド層を形成する工程。
（工程３） ｎ型ＭＯＳ構造のためのタングステンシリサイド層と、ｐ型ＭＯＳ構造のためのタングステンシリサイド層とに、金属電極を形成する工程。
（工程４） 電子障壁高さ調整のための熱処理工程。 <CMOS manufacturing method>
The method of manufacturing the CMOS of this embodiment will be described below, focusing on the method of manufacturing the structure of the metal electrode contact portion of the source / drain. Except for the structure of the metal electrode contact portion of the source / drain described below and the process for adjusting the electron barrier height, a usual CMOS manufacturing method can be appropriately adopted.
(Step 1) A step of forming an n-type silicon layer for an n-type MOS structure and a silicon-germanium layer for a p-type MOS structure as a preliminary step of formation of a structure of metal electrode contact portions of source / drain.
(Step 2) A step of forming a tungsten silicide layer on an n-type silicon layer for the n-type MOS structure and a silicon germanium layer for the p-type MOS structure.
(Step 3) A step of forming a metal electrode on a tungsten silicide layer for an n-type MOS structure and a tungsten silicide layer for a p-type MOS structure.
(Step 4) A heat treatment step for adjusting the electron barrier height.
本実施形態のＣＭＯＳの製造方法について、ソース／ドレインの金属電極接触部の構造の製造方法を中心に、以下説明する。以下に説明するソース／ドレインの金属電極接触部の構造及び電子障壁高さ調整のための処理以外は、通常のＣＭＯＳの製造方法を適宜採用することができる。
（工程１） ソース／ドレインの金属電極接触部の構造の形成の前段階として、ｎ型ＭＯＳ構造のためのｎ型シリコン層と、ｐ型ＭＯＳ構造のためのシリコンゲルマニウム層を形成する工程。
（工程２） ｎ型ＭＯＳ構造のためのｎ型シリコン層と、ｐ型ＭＯＳ構造のためのシリコンゲルマニウム層とに、タングステンシリサイド層を形成する工程。
（工程３） ｎ型ＭＯＳ構造のためのタングステンシリサイド層と、ｐ型ＭＯＳ構造のためのタングステンシリサイド層とに、金属電極を形成する工程。
（工程４） 電子障壁高さ調整のための熱処理工程。 <CMOS manufacturing method>
The method of manufacturing the CMOS of this embodiment will be described below, focusing on the method of manufacturing the structure of the metal electrode contact portion of the source / drain. Except for the structure of the metal electrode contact portion of the source / drain described below and the process for adjusting the electron barrier height, a usual CMOS manufacturing method can be appropriately adopted.
(Step 1) A step of forming an n-type silicon layer for an n-type MOS structure and a silicon-germanium layer for a p-type MOS structure as a preliminary step of formation of a structure of metal electrode contact portions of source / drain.
(Step 2) A step of forming a tungsten silicide layer on an n-type silicon layer for the n-type MOS structure and a silicon germanium layer for the p-type MOS structure.
(Step 3) A step of forming a metal electrode on a tungsten silicide layer for an n-type MOS structure and a tungsten silicide layer for a p-type MOS structure.
(Step 4) A heat treatment step for adjusting the electron barrier height.
（工程２）におけるタングステンシリサイド層の形成は、タングステンの原料ガスとシリコンの原料ガスを気相中で化学反応させることにより作製することができる。特許文献４に記載されたと同様の製造方法である。タングステンの原料ガスとシリコンの原料ガスを基板表面で化学反応させるのではなく、原料ガスを気相中で化学反応させることによって、より具体的にいえば、シリコン／タングステンの組成比が４を超える前駆体を気相中で作製し、該前駆体を基板上へ堆積させることによって、シリコン／タングステンの組成比が４を超えるタングステンシリサイド膜を作製できる。例えば、シリコンの原料ガス同士が反応しない温度の４００℃に維持した反応炉の中に、シリコンの原料ガスを予め満たしておき、その反応炉の中にタングステンの原料ガスを導入することにより、気相中でタングステンシリサイド膜の前駆体を作製する。気相中での熱的な化学反応を利用することが望ましいが、基板温度の高温化も効果的である。タングステンの原料ガスとして、フッ化タングステンガス、塩化タングステンガス、有機タングステンガス等が挙げられる。シリコンの原料ガスとして、シランガス、ジシランガス、ジクロロシラン、四塩化ケイ素等が挙げられる。
The formation of the tungsten silicide layer in (Step 2) can be produced by chemically reacting a tungsten source gas and a silicon source gas in a gas phase. It is the same manufacturing method as that described in Patent Document 4. More specifically, the composition ratio of silicon / tungsten exceeds 4 by chemically reacting the raw material gas with the raw material gas of tungsten and the raw material gas of silicon, instead of chemically reacting the raw material gas of silicon on the substrate surface. By producing the precursor in the vapor phase and depositing the precursor on the substrate, a tungsten silicide film having a silicon / tungsten composition ratio of more than 4 can be produced. For example, by filling the silicon source gas in advance in a reactor maintained at 400 ° C. at a temperature at which the silicon source gases do not react with each other and introducing the tungsten source gas into the reactor, In the phase, a precursor of a tungsten silicide film is produced. Although it is desirable to use a thermal chemical reaction in the gas phase, raising the substrate temperature is also effective. Tungsten fluoride gas, tungsten chloride gas, organic tungsten gas etc. are mentioned as source gas of tungsten. As source gases for silicon, silane gas, disilane gas, dichlorosilane, silicon tetrachloride and the like can be mentioned.
（工程２）におけるタングステンシリサイド層の形成工程の具体例を、図１１を参照して説明する。図１１は、二次イオン質量分析（ＳＩＭＳ）より得られたシリコン／タングステン組成比が１２のタングステンシリサイド膜中のフッ素原子濃度を示す図である。原料ガスとして四フッ化タングステンガスとシランガスを利用して作製したタングステンシリサイド膜は、膜中の残留フッ素濃度が０．１原子％以下であることが特徴である。不純物のフッ素は半導体装置に悪影響を及ぼすことが知られおり、四フッ化タングステンガスを利用して作製した従来のタングステン膜やタングステンシリサイド膜では、膜中の残留フッ素濃度が少なくとも１原子％以上であった。本実施形態のタングステンシリサイド膜中のフッ素濃度が小さい理由は、気相中で合成されたタングステンシリサイド膜の前駆体が、シランなどの還元性ガスにより四フッ化タングステンガス中のフッ素を完全に還元するためである。
A specific example of the step of forming the tungsten silicide layer in (Step 2) will be described with reference to FIG. FIG. 11 is a view showing the fluorine atom concentration in a tungsten silicide film having a silicon / tungsten composition ratio of 12 obtained by secondary ion mass spectrometry (SIMS). The tungsten silicide film manufactured using tungsten tetrafluoride gas and silane gas as source gases is characterized in that the residual fluorine concentration in the film is 0.1 atomic% or less. The impurity fluorine is known to adversely affect the semiconductor device, and the residual fluorine concentration in the film is at least 1 atomic% or more in the conventional tungsten film or tungsten silicide film manufactured using tungsten tetrafluoride gas. there were. The reason why the concentration of fluorine in the tungsten silicide film of this embodiment is small is that the precursor of the tungsten silicide film synthesized in the vapor phase completely reduces the fluorine in the tungsten tetrafluoride gas with a reducing gas such as silane. In order to
（工程３）における金属電極の形成工程は、通常のＣＭＯＳにおける電極形成方法を適宜用いることができる。金属電極としてＣＭＯＳに用いられる電極材料であれば用いることができ、特に限定されない。前述した電極材料がより好ましい。本実施形態では、タングステン金属又はタングステンの化合物がより好ましい。タングステンの化合物として、窒化タングステン等が挙げられる。電極として、タングステン金属又はタングステンの化合物を用いる場合は、工程２で使用した原料ガスを、続く電極形成工程においても使用することができるので、製造工程の簡素化等も図れる。タングステンの原料ガスとシリコンの原料ガスの組合せで、タングステンシリサイド膜とタングステン電極の両方を作製することが可能である。例えば、タングステンシリサイド膜は、フッ化タングステンガスとジシランガスの組合せで作製し、タングステン電極は、フッ化タングステンガスとシランガスの組合せで作製することができる。他の例として、タングステンシリサイド膜は、フッ化タングステンガスとシランガスの組合せで作製し、タングステン電極は、塩化タングステンガスとシランガスの組合せで作製することができる。このように、電極作製工程は、タングステンシリサイド膜形成工程で使用したタングステンの原料ガスとシリコンの原料ガスのうち少なくとも１つ以上の原料ガスを含む原料ガスを用いて、タングテン電極を前記タングステンシリサイド膜上に作製することができる。
In the step of forming the metal electrode in (Step 3), an electrode forming method in a normal CMOS can be appropriately used. Any electrode material can be used as long as it is used in CMOS as a metal electrode, and is not particularly limited. The electrode material mentioned above is more preferable. In the present embodiment, tungsten metal or a compound of tungsten is more preferable. Tungsten nitride etc. are mentioned as a compound of tungsten. When tungsten metal or a compound of tungsten is used as the electrode, the source gas used in step 2 can be used also in the subsequent electrode forming step, so that simplification of the manufacturing process can be achieved. It is possible to produce both a tungsten silicide film and a tungsten electrode by a combination of a tungsten source gas and a silicon source gas. For example, a tungsten silicide film can be produced by a combination of a tungsten fluoride gas and a disilane gas, and a tungsten electrode can be produced by a combination of a tungsten fluoride gas and a silane gas. As another example, a tungsten silicide film can be made of a combination of tungsten fluoride gas and silane gas, and a tungsten electrode can be made of a combination of tungsten chloride gas and silane gas. As described above, in the electrode manufacturing step, the tungsten silicide film is formed using the source gas containing at least one source gas of the source gas of tungsten and the source gas of silicon used in the step of forming the tungsten silicide film. It can be made on top.
（工程４）における熱処理工程について詳しく説明する。ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属電極接触部に、共通のタングステンシリサイド膜、および金属電極を形成した後に、窒素雰囲気下６００℃の熱処理を行うことによって、ｎ型ＭＯＳの電子障壁高さを０．３２ｅＶに維持しながら、ｐ型ＭＯＳの正孔障壁高さを０．５１ｅＶまで低減することができる。また、この熱処理条件に限らずに、真空雰囲気下や水素雰囲気下でも、ｎ型ＭＯＳの電子障壁高さ低減効果とｐ型ＭＯＳの正孔障壁高さ低減効果は有効である。酸素雰囲気下での熱処理は、金属電極の酸化を促進させるために望ましくない。また、熱処理温度の範囲は、６００℃に限定されることはなく、４００℃以上７００℃以下の範囲が望ましい。熱処理のタイミングは、タングステンシリサイド膜を成膜した後であれば、いつでも良い。電子障壁高さと正孔障壁高さの両方を低減する効果を得るためには、タングステンシリサイド膜のシリコン／タングステン組成比が高く、１２に近い方が望ましい。その理由は、タングステンシリサイド膜のシリコン／タングステン組成比が増大するに伴い、タングステンシリサイド膜のエネルギーギャップが増大し、タングステンシリサイド膜と半導体層との接触界面における状態密度を低減できるからである。一方、タングステンシリサイド膜のシリコン／タングステン組成比は４より大であることが重要である。４より小さい場合は、タングステンシリサイド膜のエネルギーギャップが小さく、タングステンシリサイド膜と半導体層との接触界面における状態密度を低減することができないために電子障壁高さを十分に低減することができず、正孔障壁高さ低減のみに有効となるからであ。よって、シリコン／タングステン組成比は４より大で１２以下であることが重要である。
The heat treatment step in (Step 4) will be described in detail. A common tungsten silicide film and metal electrode are formed at the metal electrode contact portion of both the n-type MOS and the p-type MOS, and then heat treatment is performed in a nitrogen atmosphere at 600 ° C. The hole barrier height of the p-type MOS can be reduced to 0.51 eV while maintaining the electron barrier height at 0.32 eV. In addition to the heat treatment conditions, the electron barrier height reducing effect of the n-type MOS and the hole barrier height reducing effect of the p-type MOS are effective even in a vacuum atmosphere or a hydrogen atmosphere. Heat treatment under an oxygen atmosphere is not desirable to promote the oxidation of the metal electrode. Further, the range of the heat treatment temperature is not limited to 600 ° C., and the range of 400 ° C. or more and 700 ° C. or less is desirable. The timing of the heat treatment may be any time after forming the tungsten silicide film. In order to obtain the effect of reducing both the electron barrier height and the hole barrier height, it is desirable that the silicon / tungsten composition ratio of the tungsten silicide film is high and close to 12. The reason is that the energy gap of the tungsten silicide film increases as the silicon / tungsten composition ratio of the tungsten silicide film increases, and the density of states at the contact interface between the tungsten silicide film and the semiconductor layer can be reduced. On the other hand, it is important that the silicon / tungsten composition ratio of the tungsten silicide film is larger than four. If it is smaller than 4, the energy gap of the tungsten silicide film is so small that the density of states at the contact interface between the tungsten silicide film and the semiconductor layer can not be reduced, so the electron barrier height can not be sufficiently reduced. This is because it is effective only for reducing the hole barrier height. Therefore, it is important that the silicon / tungsten composition ratio be greater than 4 and 12 or less.
タングステンシリサイド膜の熱処理後の状態を調べた。図１２は、シリコン／タングステン組成比が１２のタングステンシリサイド膜中のシリコン原子の結合状態を示すラマン散乱スペクトルである。アモルファスシリコンの結合ネットワークと同じ４７５ｃｍ－１と１６５ｃｍ－１付近の２つのブロードなピークが観測できた。これは、タングステンシリサイド膜中では、シリコン原子同士がアモルファスな結合状態を有することを示している。また、このアモルファスの結合状態は、１０００℃以上まで熱処理しても維持され、強固な結合ネットワークを有している。
The state after heat treatment of the tungsten silicide film was examined. FIG. 12 is a Raman scattering spectrum showing the bonding state of silicon atoms in a tungsten silicide film having a silicon / tungsten composition ratio of 12. Two broad peaks of the same 475cm around -1 and 165cm -1 with coupling network of the amorphous silicon could be observed. This indicates that silicon atoms have an amorphous bonding state in the tungsten silicide film. In addition, this amorphous bonding state is maintained even by heat treatment up to 1000 ° C. or more, and has a strong bonding network.
図１３は、熱処理前の堆積後と、熱処理条件を熱処理温度４００℃、５００℃、６００℃とした場合の、タングステン電極、タングステンシリサイド膜、ゲルマニウム層、ｐ型シリコン層の順で積層されたショットキーダイオードの電流（Ｉ）－電圧（Ｖ）特性を示す図である。７００℃については図示されていないが、同様に優れた特性を示した。本図から、熱処理温度の範囲は４００℃から７００℃の範囲が望ましいことがわかる。
FIG. 13 shows shots formed in the order of a tungsten electrode, a tungsten silicide film, a germanium layer, and a p-type silicon layer after deposition before heat treatment and when the heat treatment conditions are heat treatment temperatures of 400 ° C., 500 ° C. and 600 ° C. It is a figure which shows the electric current (I) -voltage (V) characteristic of a key diode. Although not shown for 700 ° C., the same excellent properties were exhibited. From this figure, it is understood that the range of the heat treatment temperature is desirably in the range of 400 ° C. to 700 ° C.
本実施形態で示した製造方法により、ＣＭＯＳのｎ型及びｐ型のソース／ドレインの金属電極接触部の構造を製造した場合、次のような効果も得られる。一般的に、新材料をＣＭＯＳへ適用すると、新しい製造プロセスの導入や製造プロセス数の増大を伴うため、製造コストが増大してしまう。しかし、本実施形態のように、ｎ型ＭＯＳとｐ型ＭＯＳのソース／ドレインの金属電極接触部に、共通のタングステンシリサイド膜を適用可能であるので、ＣＭＯＳ製造時のプロセス数の削減あるいは維持が可能となり、製造コストの上昇を抑えることができる。さらに、タングステンシリサイド膜の作製後に、タングステンシリサイド膜と同じ原料ガスを利用してタングステンシリサイド膜上部にタングステン電極を作製することが可能であるため、製造コストの上昇を抑えことができる。また、本実施の形態により作製したタングステンシリサイド膜は、段差被覆性が優れている特徴を有する。例えば、アスペクト比が約５０と高く、幅が４０ｎｍと微細な段差上に、タングステンシリサイド膜を（側壁／最表面）の膜厚比を約１／２で完全に被覆することが可能である。この優れた段差被覆性を発揮できる理由は、タングステンシリサイド膜の特徴的な形成過程に基づいている。気相中で合成されたタングステンシリサイド膜の前駆体が、堆積基板に対して低い付着確率を有しており、付着した後は堆積基板表面上で高い拡散性を有しているためである。タングステンシリサイド膜の優れた被覆性は、ＣＭＯＳのソース／ドレインの１００ｎｍ未満の直径で空いているコンタクト穴への埋め込みを可能とし、ＣＭＯＳの動作特性のばらつき抑制効果や接触抵抗低減効果を得ることができる。
When the structure of the n-type and p-type source / drain metal electrode contact portions of the CMOS is manufactured by the manufacturing method described in the present embodiment, the following effects can also be obtained. In general, application of a new material to CMOS entails an increase in manufacturing cost due to the introduction of a new manufacturing process and an increase in the number of manufacturing processes. However, as in the present embodiment, a common tungsten silicide film can be applied to the metal electrode contact portion of the source / drain of n-type MOS and p-type MOS, so reduction or maintenance of the number of processes in CMOS manufacturing can be achieved. It is possible to suppress an increase in manufacturing cost. Furthermore, after the formation of the tungsten silicide film, the tungsten electrode can be formed on the upper portion of the tungsten silicide film using the same source gas as the tungsten silicide film, so that the increase in the manufacturing cost can be suppressed. Further, the tungsten silicide film manufactured according to the present embodiment is characterized in that the step coverage is excellent. For example, it is possible to completely cover the tungsten silicide film (sidewall / uppermost surface) at a film thickness ratio of about 1/2 on a fine step with a high aspect ratio of about 50 and a width of 40 nm. The reason why the excellent step coverage can be exhibited is based on the characteristic formation process of the tungsten silicide film. This is because the tungsten silicide film precursor synthesized in the vapor phase has a low adhesion probability to the deposition substrate, and after deposition, has a high diffusivity on the deposition substrate surface. The excellent coverage of the tungsten silicide film makes it possible to bury the open source contact holes with a diameter of less than 100 nm of the source / drain of the CMOS, and obtain the effect of suppressing the variation of the operating characteristics of the CMOS and the contact resistance reduction effect. it can.
（第２の実施形態）
第２の実施形態の半導体装置は、第１の実施形態における第１の積層構造のシリコン層に替えて、シリコンとカーボンの化合物層を用いた場合に係る。本実施形態のｎ型ＭＯＳにおいても、タングステンシリサイド膜がフェルミレベルのピンニング緩和を行い、シリコンとカーボンの化合物層に対する電子障壁高さを低減することができるので、第１の実施形態と同様の効果が得られる。シリコンとカーボンの化合物層はシリコンよりも高い融点を持っているので、熱処理を行ってもタングステンシリサイド膜とシリコンとカーボンの化合物層の界面での相互拡散は生じ難く、フェルミレベルのピンニング解除効果は熱処理工程後も維持される。不純物元素として、リン（Ｐ）、ヒソ（Ａｓ）、アンチモン（Ｓｂ）などが入っていても第１の実施形態と同様の効果が得られる。 Second Embodiment
The semiconductor device of the second embodiment relates to the case where a compound layer of silicon and carbon is used in place of the silicon layer of the first laminated structure in the first embodiment. Also in the n-type MOS of the present embodiment, the tungsten silicide film can relieve the pinning at the Fermi level and reduce the height of the electron barrier to the compound layer of silicon and carbon. Therefore, the same effect as the first embodiment Is obtained. Since the compound layer of silicon and carbon has a melting point higher than that of silicon, mutual diffusion at the interface between the tungsten silicide film and the compound layer of silicon and carbon is difficult to occur even if heat treatment is performed, and the Fermi level depinning effect is It is maintained also after the heat treatment process. Even if phosphorus (P), hydrogen (As), antimony (Sb) or the like is contained as an impurity element, the same effect as that of the first embodiment can be obtained.
第２の実施形態の半導体装置は、第１の実施形態における第１の積層構造のシリコン層に替えて、シリコンとカーボンの化合物層を用いた場合に係る。本実施形態のｎ型ＭＯＳにおいても、タングステンシリサイド膜がフェルミレベルのピンニング緩和を行い、シリコンとカーボンの化合物層に対する電子障壁高さを低減することができるので、第１の実施形態と同様の効果が得られる。シリコンとカーボンの化合物層はシリコンよりも高い融点を持っているので、熱処理を行ってもタングステンシリサイド膜とシリコンとカーボンの化合物層の界面での相互拡散は生じ難く、フェルミレベルのピンニング解除効果は熱処理工程後も維持される。不純物元素として、リン（Ｐ）、ヒソ（Ａｓ）、アンチモン（Ｓｂ）などが入っていても第１の実施形態と同様の効果が得られる。 Second Embodiment
The semiconductor device of the second embodiment relates to the case where a compound layer of silicon and carbon is used in place of the silicon layer of the first laminated structure in the first embodiment. Also in the n-type MOS of the present embodiment, the tungsten silicide film can relieve the pinning at the Fermi level and reduce the height of the electron barrier to the compound layer of silicon and carbon. Therefore, the same effect as the first embodiment Is obtained. Since the compound layer of silicon and carbon has a melting point higher than that of silicon, mutual diffusion at the interface between the tungsten silicide film and the compound layer of silicon and carbon is difficult to occur even if heat treatment is performed, and the Fermi level depinning effect is It is maintained also after the heat treatment process. Even if phosphorus (P), hydrogen (As), antimony (Sb) or the like is contained as an impurity element, the same effect as that of the first embodiment can be obtained.
なお、上記実施形態等で示した例は、発明を理解しやすくするために記載したものであり、この形態に限定されるものではない。
Note that the examples shown in the above embodiments and the like are described to facilitate understanding of the invention, and the present invention is not limited to this embodiment.
本発明の半導体装置は、ｎ型ＭＯＳとｐ型ＭＯＳの両方のソース／ドレインの金属接触部の接触抵抗の低減が可能な構造であるので、ＣＭＯＳの微細化、駆動力の向上が要求される製品に、幅広く利用できる。また、本発明の製造方法によれば、ＣＭＯＳの微細化及び集積化、並びに製造工程の効率化がさらに期待でき、産業上有用である。
Since the semiconductor device of the present invention has a structure capable of reducing the contact resistance of the metal contact portion of both the n-type MOS and the p-type MOS, the miniaturization of the CMOS and the improvement of the driving force are required. It can be widely used for products. Further, according to the manufacturing method of the present invention, miniaturization and integration of CMOS and further efficiency of the manufacturing process can be further expected, which is industrially useful.
１、１１ 金属電極（ソース／ドレイン）
２、１２ タングステンシリサイド膜
３、４、１４ シリコン層
５、１５ 金属電極（ゲート）
６、１６ 酸化物
１３ シリコンゲルマニウム層又はゲルマニウム層 1, 11 Metal electrode (source / drain)
2, 12 tungsten silicide film 3, 4, 14 silicon layer 5, 15 metal electrode (gate)
6, 16oxide 13 silicon germanium layer or germanium layer
２、１２ タングステンシリサイド膜
３、４、１４ シリコン層
５、１５ 金属電極（ゲート）
６、１６ 酸化物
１３ シリコンゲルマニウム層又はゲルマニウム層 1, 11 Metal electrode (source / drain)
2, 12
6, 16
Claims (9)
- 金属電極、タングステンシリサイド膜、並びにシリコン層若しくはシリコンとカーボンの化合物層の順で積層された第１の積層構造と、前記金属電極、前記タングステンシリサイド膜、及びシリコンとゲルマニウムの化合物層の順で積層された第２の積層構造とを備え、前記タングステンシリサイド膜のシリコン／タングステンの組成比が４より大で１２以下であることを特徴とする半導体装置。 A first laminated structure in which a metal electrode, a tungsten silicide film, and a silicon layer or a compound layer of silicon and carbon are laminated in this order, and the metal electrode, the tungsten silicide film, and a compound layer of silicon and germanium in this order A semiconductor device comprising: the second stacked structure; and a composition ratio of silicon / tungsten of the tungsten silicide film is greater than 4 and 12 or less.
- 前記金属電極が、タングステン、窒化タングステン、チタン、窒化チタン、タンタル、窒化タンタル、ニッケル、コバルト、モリブデンのうちの少なくとも１つ以上であることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the metal electrode is at least one or more of tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, nickel, cobalt, and molybdenum.
- 前記シリコンとゲルマニウムの化合物層は、（ゲルマニウム）／（シリコン＋ゲルマニウム）の組成比が０より大で１以下であることを特徴とする請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the compound layer of silicon and germanium has a composition ratio of (germanium) / (silicon + germanium) of more than 0 and 1 or less.
- 前記シリコンとカーボンの化合物層は、（カーボン）／（シリコン＋カーボン）の組成比が０より大で０．５以下であることを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。 4. The compound layer of silicon and carbon according to any one of claims 1 to 3, wherein a composition ratio of (carbon) / (silicon + carbon) is more than 0 and 0.5 or less. Semiconductor device.
- 前記第１の積層構造における前記シリコン層又はシリコンとカーボンの前記化合物層が、ｎ型のキャリアタイプであり、前記第２の積層構造におけるシリコンとゲルマニウムの前記化合物層が、ｐ型のキャリアタイプであることを特徴とする請求項１乃至４のいずれか１項に記載の半導体装置。 The silicon layer or the compound layer of silicon and carbon in the first laminated structure is an n-type carrier type, and the compound layer of silicon and germanium in the second laminated structure is a p-type carrier type The semiconductor device according to any one of claims 1 to 4, characterized in that:
- 前記第１及び第２の積層構造の少なくともいずれか一方の積層構造が、２つ以上並列する構造であって、該並列する構造の、中間位置に金属と酸化膜と半導体層の順で積層されたＭＯＳ構造を備えていることを特徴とする請求項１乃至５のいずれか１項に記載の半導体装置。 The laminated structure of at least one of the first and second laminated structures is a structure in which two or more are arranged in parallel, and the metal, the oxide film, and the semiconductor layer are laminated in the middle position in the parallel structure. The semiconductor device according to any one of claims 1 to 5, further comprising a MOS structure.
- 複数の前記第１の積層構造及び複数の第２の積層構造が金属配線によって接続された、ＣＭＯＳ構造を備えることを特徴とする請求項１乃至６のいずれか１項記載の半導体装置。 The semiconductor device according to any one of claims 1 to 6, further comprising a CMOS structure in which the plurality of first stacked structures and the plurality of second stacked structures are connected by metal interconnections.
- タングステンの原料ガスとシリコンの原料ガスを気相中で化学反応させることにより、シリコン／タングステンの組成比が４より大で１２以下の前駆体を気相中で作製した後に、前記前駆体を、シリコン層若しくはシリコンとカーボンの化合物層並びにシリコンとゲルマニウムの化合物層の上に堆積して、タングステンシリサイド膜を作製する工程と、
金属電極を前記タングステンシリサイド膜上に作製する電極作製工程と、
を備えることを特徴とする、請求項１記載の半導体装置の製造方法。 The chemical reaction of the tungsten source gas and the silicon source gas in the gas phase produces a precursor having a silicon / tungsten composition ratio of greater than 4 and 12 or less in the gas phase, Depositing on a silicon layer or a compound layer of silicon and carbon and a compound layer of silicon and germanium to form a tungsten silicide film;
An electrode manufacturing step of manufacturing a metal electrode on the tungsten silicide film;
The method of manufacturing a semiconductor device according to claim 1, comprising: - 前記電極作製工程は、
前記タングステンの原料ガスと前記シリコンの原料ガスのうち少なくとも１つ以上の原料ガスを含む原料ガスを用いて、タングテン電極を前記タングステンシリサイド膜上に作製する工程であることを特徴とする、請求項８記載の製造方法。 The electrode preparation step is
A process for producing a tungsten electrode on the tungsten silicide film, using a source gas containing at least one source gas of the source gas of tungsten and a source gas of silicon from the source gas. The manufacturing method of 8.
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