JP2000058755A - Semiconductor device and manufacture of it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the occupied area of a high precision ladder resistance circuit with a small partial voltage output error by employing p-type as the impurities introduced in a polycrystalline silicon of the ladder resistance circuit comprising the polycrystalline silicon. SOLUTION: An oxide film 103 is formed on the surface of a silicon substrate 101, and the oxide film 103 is coated with a polycrystalline silicon film 102. A p-type impurity, for example, BF2 is introduced for the thickness of the 102 to be 500-1500 Åwhile the sheet resistance value to be 1 kΩ/square-25 kΩ/square. Then the polycrystalline silicon film 102 resistor is patterned, there the length of the polycrystalline silicon film resistor being 10-150 μm. A photo- resist 107 is so patterned on the polycrystalline silicon film 102 that the upper part of a region of a heavily doped region 108 is opened, and the p-type impurity BF2 is introduced. Then an intermediate insulating film 104 and a metal wiring 105 are formed, and the front part of a semiconductor substrate is coated with a surface protection film 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a ladder resistance circuit using a polycrystalline silicon resistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a ladder resistor circuit using a polycrystalline silicon resistor into which an N-type impurity is introduced has been widely used. However, in order to obtain a highly accurate ladder resistor circuit having a small divided voltage output error. It is known that the length of a polycrystalline silicon resistor is increased.

[0003]

However, a conventional ladder resistance circuit using an N-type polycrystalline silicon resistor is:
Since the means for increasing the length of the resistor is used to reduce the divided voltage output error, there is a problem that the occupied area of the ladder resistor circuit increases.

An object of the present invention is to provide a high-precision ladder resistance circuit with a small divided voltage output error and a small occupation area, which was impossible with a ladder resistance circuit using a conventional N-type polycrystalline silicon resistor. With the goal.

[0005]

The main means adopted by the semiconductor device of the present invention to achieve the above object are as follows: (1) Impurities introduced into polycrystalline silicon of a ladder resistance circuit using polycrystalline silicon are: P type. (2) the P-type impurity introduced into the polycrystalline silicon resistor and a BF _2.

(3) P-type impurities to be introduced into the P-type polycrystalline silicon resistor are boron. (4) Two or more types of impurities are introduced into the P-type polycrystalline silicon resistor. (5) The thickness of the P-type polycrystalline silicon resistor is from 500 to 15
00 °.

(6) A semiconductor device characterized in that the P-type polycrystalline silicon resistor has a sheet resistance of 1 kΩ / □ to 25 kΩ / □. (7) The P-type polycrystalline silicon resistor has a temperature coefficient of -40.
A semiconductor device characterized by being at most 00 ppm / ° C. (8) The semiconductor device is characterized in that the length of the P-type polycrystalline silicon resistor is 10 μm to 150 μm.

(9) A step of forming an oxide film on the semiconductor substrate, a step of forming a polycrystalline silicon film of 500 to 1500 ° on the oxide film, and doping a P-type impurity in the polycrystalline silicon film region Forming a region of the polycrystalline silicon film by etching the polycrystalline silicon film, and adding 1 × 10 ¹⁵ to a part of the polycrystalline silicon film.
Doping up to 5 × 10 ¹⁶ atom / cm ² , forming an intermediate insulating film on the oxide film and the polycrystalline silicon film, and forming the intermediate insulating film on the first polycrystalline silicon film and the semiconductor substrate. A method for manufacturing a semiconductor device includes a step of providing a contact hole in a film and a step of providing a metal wiring in the contact hole.

(10) A step of forming an oxide film on a semiconductor substrate, a step of forming a first polysilicon film on the oxide film, and doping impurities in the first polysilicon film region Forming a region of the first polycrystalline silicon film by etching the first polycrystalline silicon film; and forming an insulating film on a surface of the semiconductor substrate including over the first polycrystalline silicon film region. Forming a;
Forming a second polycrystalline silicon film of 500 to 1500 degrees on the insulating film; and doping the second polycrystalline silicon film with 1 × 10 ¹⁴ to 1 × 10 ¹⁵ atom / cm ² of P-type impurities. Forming a region of a second polycrystalline silicon resistor by etching the second polycrystalline silicon film;
1 × 10 ^{15 to} 5 × 5 in a part of the region of the second polycrystalline silicon film.
× 10 ¹⁶ atom / cm ² doping; forming an intermediate insulating film on the insulating film and the second polycrystalline silicon film; and forming the first polycrystalline silicon film and the second polycrystalline silicon film on the second polycrystalline silicon film. A method for manufacturing a semiconductor device includes a step of providing a contact hole in a silicon film and the intermediate insulating film on the semiconductor substrate, and a step of providing a metal wiring in the contact hole.

(11) The insulating film has a thickness of 300Å to 1
The structure is characterized by being an oxide film of 000 °. (12) The insulating film has a laminated structure of a thermal oxide film having a thickness of 300 to 700 °, a nitride film having a thickness of 200 to 1000 ° and a thermal oxide film having a thickness of 100 ° or less.

(13) A P-type impurity doped into a part of the second polycrystalline silicon film and a P-type impurity doped into a diffusion region of a MOS transistor having a P-type diffusion region are simultaneously introduced. did. (14) a step of forming an oxide film on a semiconductor substrate, and a step of forming a first polycrystalline silicon film on the oxide film;
Doping an impurity in the first polycrystalline silicon film region, forming a region of the first polycrystalline silicon film by etching the first polycrystalline silicon film, Forming an insulating film on the surface of the semiconductor substrate including above a film region; forming a second polycrystalline silicon film of 500 to 1500 degrees on the insulating film; and forming a second polycrystalline silicon film on the second polycrystalline silicon film. 1x P-type impurities
A step of doping 10 ¹⁴ -1 × 10 ¹⁵ atom / cm ^2, a step of forming a region of the second polycrystalline silicon film by etching the second polycrystalline silicon film, and a step of forming an N-type polycrystalline silicon resistor. Doping the ^second polycrystalline silicon film with N-type impurities at 1 × 10 ^{15 to} 5 × 10 ¹⁶ atom / cm ^{2, and} forming the second polycrystalline silicon film at a high resistance element and a capacitor electrode.
P-type impurity is added to a part of the region of the polycrystalline silicon film and the second polycrystalline silicon film constituting the low resistance element by 1 × 10
^{15 to} 5 × 10 ¹⁶ atom / cm ² doping, forming an intermediate insulating film on the insulating film and the second polycrystalline silicon film, and forming the first polycrystalline silicon film and the second polycrystalline silicon film on the second polycrystalline silicon film.
Forming a contact hole in the polycrystalline silicon film and the intermediate insulating film on the semiconductor substrate; and providing a metal wiring in the contact hole.

(15) The method of manufacturing a semiconductor device, wherein the N-type impurity doped in the polycrystalline silicon film region is phosphorus. (16) N doping the polycrystalline silicon film region
A method for manufacturing a semiconductor device, wherein the impurity of the mold is arsenic. (17) P-type impurities and P-type diffusion regions doped in a part of the region of the second polycrystalline silicon film constituting the high resistance element and the second polycrystalline silicon film constituting the low resistance element Wherein a P-type impurity to be doped is simultaneously introduced into the diffusion region of the MOS transistor having the above structure.

(18) N-type impurities to be doped into a region of the second polycrystalline silicon film constituting the N-type polycrystalline silicon resistor and doping to a diffusion region of a MOS transistor having an N-type diffusion region. A method of manufacturing a semiconductor device, characterized by simultaneously introducing N-type impurities.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention is a polycrystalline silicon resistor having a small occupied area, a small divided voltage output error, and a high accuracy ladder-resistor circuit in which a P-type impurity is introduced.
(Hereinafter referred to as a P-type polycrystalline silicon resistor). Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a ladder resistance circuit showing one embodiment of the semiconductor device of the present invention. Terminal A11 and Terminal B12
A divided voltage Vo is obtained from the terminal C13 by the respective resistors R1 and R2. The divided voltage Vo can be expressed by the following equation. Vo = (R2 / (R1 + R2)) * V-The divided voltage Vo in the equation is a theoretical value, and the difference between the theoretical value and the measured value is a divided voltage output error. The divided voltage output error can be expressed by the following equation.

Divided voltage output error = ((| theoretical value Vo−actual value Vo |) / theoretical value Vo) * 100− Here, the impurity introduced into the polycrystalline silicon resistor is changed from N-type to P-type. The fact that the divided voltage output error can be reduced will be described based on data. As the characteristics required for the polycrystalline silicon resistor constituting the ladder circuit,
It is considered that the divided voltage output error of the ladder circuit is small and the integrated area is small. In general, when the thickness of polycrystalline silicon is reduced, the variation in the concentration of low-concentration impurities is reduced, so that the divided voltage output error of the ladder circuit is reduced, and a high-precision ladder circuit can be manufactured. However, even if the thickness of the polycrystalline silicon is reduced, if the length of the polycrystalline silicon resistor into which N-type impurities are introduced (hereinafter referred to as N-type polycrystalline silicon resistor) is reduced, the divided voltage output error increases. As a result, it is difficult to reduce the integration area. However, by using a P-type polycrystalline silicon resistor, the length of the resistor can be reduced and the integration area can be reduced. An example will be described with reference to FIG.

FIG. 3 shows a film thickness of 1000 mm and a sheet resistance of 10 kΩ / □.
FIG. 5 is a diagram showing a relationship between the lengths of P-type and N-type polycrystalline silicon resistors constituting the ladder circuit of FIG.
As a P-type impurity introduced into a P-type polycrystalline silicon resistor
An example is shown in which phosphorus is used as N-type impurities introduced into BF ₂ ions and N-type polycrystalline silicon. As can be seen from FIG. 3, even if the thickness of the polycrystalline silicon of the ladder circuit composed of the N-type polycrystalline silicon resistor is reduced to 1000 °, the divided voltage output error occurs when the length of the polycrystalline silicon resistor becomes 30 μm or less.
0.5% or less cannot be secured. However, in a ladder circuit composed of a P-type polycrystalline silicon resistor, even if the length of the polycrystalline silicon resistor is 10 μm, a divided voltage output error of 0.5% or less can be ensured. Further, if the polycrystalline silicon film thickness is further reduced for the above-mentioned reason, the divided voltage output error is reduced, which is effective. However, when the thickness of the polycrystalline silicon is reduced, the variation in the film thickness within the substrate and between the substrates is increased, and the variation in the resistance value is also increased. As a result, the divided voltage output error is increased. Therefore, the film thickness is desirably from 500 ° to 1500 °, and the optimum value is 500 °. Further, when the length of the polycrystalline silicon resistor is reduced, the influence of the grain size cannot be ignored, and the variation in the resistance value increases. For this reason, the divided voltage output error increases, so that the length of the polycrystalline silicon resistor is desirably 10 μm or more, and since the integration area increases, the limit is 150 μm.

Furthermore, FIG. 4 is P-type as the impurity in the polycrystalline silicon film thickness 1000Å is BF _2, N-type relationship impurity dose amount and the sheet resistance value upon the introduction of the impurity using ion implantation technique phosphorus FIG. From FIG. 4, it can be seen that the concentration variation of the low-concentration impurities is reduced by changing the ions to be introduced into polycrystalline silicon from phosphorus to BF ₂ .

As an example, a case where phosphorus and BF ₂ are introduced into polycrystalline silicon to form a sheet resistance value of 20 kΩ / □ will be described. Usually, the impurity dose varies ± 10% of the impurity dose to be introduced. The dose required to create a polycrystalline silicon resistor with a sheet resistance of 20kΩ / □ using phosphorus is
3.5 × 10 ¹⁴ atom / cm ² at because ^{± 0.35 × 10 14 atom / cm} 2
The dose amount varies. In other words, the sheet resistance value in phosphorus
When a polycrystalline silicon resistor of 20 kΩ / □ is to be produced, it can be seen that the sheet resistance varies from 13 kΩ / □ to 30 kΩ / □. Also, BF ₂ has a sheet resistance of 20 kΩ
The dose required to create a polycrystalline silicon resistor of / □ is 1.35 × 10 ¹⁴ atom / cm ² , ± 0.135 × 10 ¹⁴ atom / cm
^The dose varies by about ^two . That is, the sheet resistance value is BF ₂
When an attempt is made to produce a polycrystalline silicon resistor of 20 kΩ / □, the sheet resistance varies from 17 kΩ / □ to 25 kΩ / □. From the above, it can be seen that the variation in the concentration of the low-concentration impurities is smaller in BF ₂ than in phosphorus. As described above, when the concentration variation of the low concentration impurities is reduced, the divided voltage output error of the ladder circuit is reduced. That is, the ladder circuit composed of the P-type polycrystalline silicon resistor can increase the sheet resistance value of the polycrystalline silicon resistor while maintaining the divided voltage output error at 0.5% or less.

A switching regulator (hereinafter referred to as S)
In order to reduce the divided voltage output error and the area of the ladder circuit composed of the polycrystalline silicon film in an integrated circuit such as WR), the sheet resistance is usually 5k.
It is composed of an N-type polycrystalline silicon resistor having a resistance of about Ω / □ to 25 kΩ / □.
ppm / ° C to -4800 ppm / ° C.
When used also in the constant current section for setting the oscillation frequency of R, the oscillation frequency fluctuates in the operating temperature range of −40 ° C. to 85 ° C. However, the sheet resistance value of P-type conductivity is 5
The resistance change of the polycrystalline silicon resistor from about kΩ / □ to about 25 kΩ / □ with respect to temperature is from −1700 ppm / ° C. to −4000 p.
pm / ° C., the resistance value fluctuation is smaller than that of the N-type polycrystalline silicon resistor, and the oscillation frequency fluctuation can be reduced.

FIG. 5 shows the relationship between the sheet resistance and the temperature coefficient when using BF ₂ for P-type and phosphorus for N-type as impurities in polycrystalline silicon having a thickness of 1000 °, and N-type polycrystalline silicon. This shows that the resistance value variation with temperature of the P-type polycrystalline silicon resistor is smaller than that of the resistor. When the sheet resistance value is increased, as described above, the concentration variation of the low-concentration impurities increases, and the divided voltage output error increases. Furthermore, the sheet resistance value is desirably 25 kΩ / □ or less, since the resistance value variation with temperature increases.
Also, if the resistance value is small, the variation in grain size cannot be ignored, so the sheet resistance value is desirably 1 kΩ / □ or more. That is, the sheet resistance of the P-type polycrystalline silicon resistor is desirably from 1 kΩ / □ to 25 kΩ / □.
-Type polycrystalline silicon resistor has a resistance variation with temperature
4000 ppm / ° C or less.

FIG. 2 is a schematic sectional view showing one embodiment of a semiconductor device according to the manufacturing method of the present invention. FIG. 2 is a sectional view of a resistance element used in the ladder resistance circuit of the present invention.
Denotes a field oxide film 10 on a silicon semiconductor substrate 101.
3, a high-resistance polycrystalline silicon resistor 102 in a low-concentration impurity region into which BF ₂ or boron, which is a P-type impurity, is introduced. The thickness of the polycrystalline silicon film is set to 500Å1500Å. Further, at both ends of the resistor, a P-type high-concentration region 107 in which the impurity concentration is increased so that sufficient contact with the aluminum wiring 105 can be obtained.
Having. A metal electrode 105 is provided on the high concentration region via a contact hole of the intermediate insulating film 104. Further, a protective film 106 is provided thereon.

FIG. 6 is a cross-sectional view in the order of steps showing the manufacturing method of FIG. 2 of the present invention. FIG. 6A shows that an oxide film 103 is formed on the surface of a silicon substrate 101, and a CVD method (Chemical Va) is used.
a polycrystalline silicon film 102 is deposited on the oxide film 103 by por deposition or sputtering.
This figure shows how BF ₂ , which is a P-type impurity, is introduced to obtain a desired sheet resistance value by an ion implantation method. The film thickness of this polycrystalline silicon film 102 is from 500 ° to 1500
Å thickness, sheet resistance value from 1kΩ / □ to 25kΩ / □
In order to obtain P, a P-type impurity BF2 is introduced. The P-type impurity introduced into the polycrystalline silicon resistor 102 may be boron. For example, in the present invention, the thickness of the polycrystalline silicon film is set to 1000 °, and BF2, which is a P-type impurity, is reduced to about 1 × 1.
0 ¹⁴ 〜1 × 10 ¹⁵ atom / cm ² doping, sheet resistance 1k
25 kΩ / □ was obtained from Ω / □.

FIG. 6B shows a state where the polycrystalline silicon resistor 102 is patterned by photolithography and dry etching. At that time, the polycrystalline silicon resistor needs to have a length of 10 μm to 150 μm. FIG. 6C shows that the photoresist 107 is patterned by photolithography so as to open an area on the polycrystalline silicon resistor 102 to be a high impurity concentration area 108 in order to make sufficient contact with the aluminum wiring. This figure shows a state in which a dose of 1 × 10 ^{15 to} 5 × 10 ¹⁶ atom / cm ² is introduced into the BF ₂ which is a type impurity by an ion implantation method. The P-type impurity to be introduced is phosphorus in the present invention.
BF ₂ , which is a P-type impurity, was introduced at 5 × 10 ¹⁵ atom / cm ² into a high impurity concentration region for making sufficient contact with the aluminum wiring of the polycrystalline silicon resistor.

After that, the photoresist 107 is removed, the intermediate insulating film 104 is formed by a CVD method or the like, and is flattened by a heat treatment. Next, a contact hole is formed to selectively communicate the intermediate insulating film 104 with the high impurity concentration region 108 of the polycrystalline silicon resistor. Subsequently, a contact reflow process is performed, and finally, a metal material or the like is formed on the front surface by vacuum evaporation or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 105, and the front surface of the semiconductor substrate is surface protected. Cover with membrane 106. FIG. 6D shows a state of the P-type polycrystalline silicon resistor 102 thus formed. It is not always necessary to use P-type polycrystalline silicon as a polycrystalline silicon resistor constituting a part other than the ladder circuit. They may be used properly in consideration of characteristics and forming steps. However, a P-type polycrystalline silicon resistor should be used where precision is required.

FIG. 7 is a sectional view of a substrate when the manufacturing method of the present invention is applied to an integrated circuit device including a MOS transistor and a capacitor. P-type silicon semiconductor substrate 2
01, N, which has a conductivity type opposite to that of the P-type silicon semiconductor substrate.
A mold well region 210 is formed. Further, on the P-type silicon semiconductor substrate 201, an N-type diffusion layer 208 having a conductivity type opposite to that of the P-type silicon semiconductor substrate, and an N-type well region 21 are formed.
0, a P-type diffusion layer 20 having a conductivity type opposite to that of the well region is formed.
Thus, a MOS transistor having the respective diffusion layers and the gate electrode 203 made of the first polycrystalline silicon film is formed. It is not always necessary to use a P-type silicon semiconductor substrate, but a P-type well region is formed using an N-type silicon semiconductor substrate, a P-type transistor is formed in the N-type silicon semiconductor substrate, and a P-type transistor is formed in the P-type well region. An N-type transistor may be made. Next, the first polycrystalline silicon film forms a gate electrode 203 and a capacitor electrode 204 on the field oxide film 202. On the capacitor electrode 204 made of the first polycrystalline silicon film, a capacitor electrode 207 made of a second polycrystalline silicon resistor into which BF ₂ or boron is introduced is formed via an insulating film 205. Further, the second polycrystalline silicon resistor forms the capacitor electrode 207 and forms the ladder circuit.
To form The gate electrode in FIG. 7 may be formed of second polycrystalline silicon. Further, the thickness of the second polycrystalline silicon and the thickness of the first polycrystalline silicon need not be equal, and the resistance value can be arbitrarily set according to the thickness of the polycrystalline silicon. For example, the thickness of the first polycrystalline silicon may be 4000 ° and the thickness of the second polycrystalline silicon may be 1000 °.

FIG. 8 is a sectional view in the order of steps showing a method of manufacturing a substrate when the manufacturing method of the present invention is applied to an integrated circuit device including a MOS transistor and a capacitor. FIG. 8A shows that a silicon nitride film (Si ₃ N ₄ ) is patterned on a P-type semiconductor substrate 201 so as to open an N-type well region 210 of a conductivity type opposite to that of the P-type semiconductor substrate, and then an N-type impurity is formed. Is doped by ion implantation to remove the silicon nitride film. Next, a state in which an isolation region and an active region are formed using the Locos method is shown.

FIG. 8B shows that the film thickness is 3
After the formation of the gate insulating film of 00 °, the gate electrode 203 is formed.
Then, a first polycrystalline silicon film serving as the capacitor electrode 204 is deposited on the oxide film by a CVD method or a sputtering method, and is doped with a high concentration of phosphorus by an ion implantation method or an impurity diffusion furnace. Next, a state in which the gate electrode 203 and the first polycrystalline silicon resistor 204 are patterned by photolithography and dry etching is shown.

Normally, in order to guarantee the reliability of a semiconductor device, the thickness of a gate insulating film formed of a thermal oxide film is 3 MV / cm.
It is necessary to set the thickness to about the same. For example, when the MOS transistor has a power supply voltage of 30 V, an oxide film thickness of 1000 ° or more is required. FIG. 8C shows the result of the thermal oxidation method.
An oxide film 205 is formed on the first polycrystalline silicon film so as to have a thickness of 100 ° to 3000 °, and then a second polycrystalline silicon resistor 2 is formed by a CVD method or a sputtering method.
06. A second polycrystalline silicon film to be the capacitor electrode 207 is deposited, and is a P-type impurity by ion implantation.
This shows how BF ₂ is doped. The thickness of this second polycrystalline silicon film is set to a thickness of 500 ° to 1500 °, and a P-type impurity BF ₂ is doped to obtain a sheet resistance of 1 kΩ / □ to 25 kΩ / □. Incidentally, the P-type impurity doped into the polycrystalline silicon resistor may be boron. The insulating film 205 on the first polycrystalline silicon film 204 is formed of a thermal oxide film (Bo) having a thickness of, for example, 300 ° for the purpose of forming a high-quality capacitor other than the thermal oxide film.
ttom. Ox), an insulating film having a laminated structure composed of a nitride film formed by a CVD method having a thickness of 500 ° and a thermal oxide film (Top. Ox) having a thickness of about 10 ° may be used. Bottom. Ox film thickness is about 300-700Å
The thickness of the nitride film is about 200 to 1000 °, and the top. Ox
The film thickness is set to 100 ° or less. However, Bottom. O
It is preferable that x and the nitride film be determined based on a required breakdown electric field.

FIG. 8D shows a second polycrystalline silicon resistor 20 formed by photolithography and dry etching.
6 and 207 are shown patterned. At that time, the polycrystalline silicon resistor needs to have a length of 10 μm to 150 μm. FIG. 8E shows that the photoresist is patterned by photolithography so as to open the region for forming the diffusion region 208 of the N-type transistor, and arsenic, which is an N-type impurity, is implanted at a dose of 3 × by ion implantation. After implanting 10 ^{15 to} 5 × 10 ¹⁹ atom / cm ² , a high-temperature heat treatment is performed to activate and diffuse the implanted impurities. Next, a region for forming a P-type high impurity concentration region 211 and a region for forming a P-type transistor diffusion region 209 in order to make sufficient contact with the aluminum wiring to the polycrystalline silicon resistor by photolithography. Patterning the photoresist 107 so as to open the
This shows a state in which BF ₂ which is a P-type impurity is introduced by an ion implantation method. According to the present invention, BF ₂ , which is a P-type impurity, is added to the high impurity concentration region 211 for making sufficient contact with the aluminum wiring of the polycrystalline silicon resistor.
× 10 ¹⁵ atom / cm ^{2 was} introduced.

After that, the photoresist is removed and CVD is performed.
An intermediate insulating film 104 is formed by a method or the like, and is flattened by a heat treatment. Next, a contact hole is formed in the intermediate insulating film 104 to selectively communicate with the high impurity concentration region 211 of the polycrystalline silicon resistor. Subsequently, a contact reflow process is performed, and finally, a metal material or the like is formed on the front surface by vacuum evaporation or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 105, and the front surface of the semiconductor substrate is formed as a protective film. Cover with 106. FIG. 7 shows the state of the P-type polycrystalline silicon resistor thus formed.

The gate electrode shown in FIG. 8C may be formed of second polycrystalline silicon. Further, the thickness of the second polycrystalline silicon and the thickness of the first polycrystalline silicon need not be equal, and the resistance value can be arbitrarily set according to the thickness of the polycrystalline silicon. For example, the thickness of the first polycrystalline silicon may be 4000 ° and the thickness of the second polycrystalline silicon may be 1000 °.

FIG. 9 is a sectional view of a substrate in the order of steps in the case where the manufacturing method of the present invention is applied to an integrated circuit device including a MOS transistor, a capacitor and a resistive element other than a ladder circuit. The steps up to FIG. 8D are the same, and FIG.
Photoresist is patterned by photolithography so as to open a region for forming the diffusion region 208 of the N-type transistor and a region for forming the N-type polycrystalline silicon resistor 216, and removes arsenic which is an N-type impurity. Dose 3 × 10 ^{15 to} 5 × 10 ¹⁹ atom / cm ² by ion implantation
Is implanted, a high-temperature heat treatment is performed to activate and diffuse the implanted impurities.

Next, as shown in FIG. 9B, a P-type high impurity concentration region 21 is formed by a lithography method in order to make sufficient contact with the aluminum wiring to the polycrystalline silicon resistor.
1 and diffusion region 20 of P-type transistor
Photoresist 107 is patterned so as to open over a region to be 9 and a region to be a low-resistance P-type polycrystalline silicon resistor 215, and BF ₂ as a P-type impurity is introduced by ion implantation. Is shown. In the present invention, the high impurity concentration region 211 for making sufficient contact with the aluminum wiring of the polycrystalline silicon resistor is provided.
BF ₂ as a P-type impurity was introduced at 5 × 10 ¹⁵ atom / cm ² .

After that, the photoresist is removed and the CVD
An intermediate insulating film 104 is formed by a method or the like, and is flattened by a heat treatment. Next, a contact hole is formed in the intermediate insulating film 104 to selectively communicate with the high impurity concentration region 211 of the polycrystalline silicon resistor. Subsequently, a contact reflow process is performed, and finally, a metal material or the like is formed on the front surface by vacuum evaporation or sputtering, and then photolithography and etching are performed to form a patterned metal wiring 105, and the front surface of the semiconductor substrate is formed as a protective film. Cover with 106. FIG. 10 shows three kinds of polycrystalline silicon resistors having different sheet resistances formed as described above.

Incidentally, a polycrystalline silicon resistor constituting a ladder circuit may be used as a polycrystalline silicon resistor constituting other than the ladder circuit. Also, in order to make a polycrystalline silicon resistor constituting a part other than the ladder circuit a high resistance body, FIG.
(d) Thereafter, Ar ions were implanted at a dose of 1e14 to 1E16 atom / cm ² . The subsequent steps are shown in FIG. 9 (A) → (B) → FIG.
Is the same as The ion implantation of Ar damages the polycrystalline silicon film, reduces the grain size, and increases the grain boundaries. Therefore, segregation at the grain boundary
The sheet resistance of the N-type polycrystalline silicon resistor implanted with N-type ions increases, and the sheet resistance of the P-type polycrystalline silicon resistor implanted with P-type ions that do not segregate at the grain boundaries does not change. Thus, the sheet resistance of the N-type polycrystalline silicon resistor can be changed by changing the dose of Ar for ion implantation.

[0037]

As described above, according to the present invention, in a ladder resistor circuit using a polycrystalline silicon resistor, a sheet resistance value can be increased by introducing a P-type impurity into the polycrystalline silicon resistor. It can be made high, short in length and small in temperature coefficient. As a result, it is possible to obtain a ladder resistor circuit having a short resistor length and a small divided voltage output error, which was impossible with a ladder resistor circuit using a conventional N-type polycrystalline silicon resistor. As a result, a high-precision ladder resistor circuit can be realized with a small occupied area, and cost reduction can be achieved. In addition, a great effect can be obtained in many ICs such as application to an IC having a limited chip size. Can be

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a ladder resistance circuit showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view showing a resistance element of the semiconductor device of the present invention shown in FIG. 1;

FIG. 3 is a diagram showing the length of a polycrystalline silicon resistor having a thickness of 1000 ° with BF2 introduced for a P type and phosphorus introduced for an N type and the voltage division of a ladder resistance circuit constituted by each polycrystalline silicon resistor. FIG. 6 is a diagram illustrating a relationship between output voltage errors.

FIG. 4 is a diagram showing the relationship between the impurity dose and the sheet resistance when BF ₂ and P-type are introduced as impurities into polycrystalline silicon having a thickness of 1000 ° P-type and N-type, respectively.

FIG. 5 is a diagram showing the relationship between the sheet resistance value and the temperature coefficient when using BF ₂ for P-type and phosphorus for N-type as impurities in polycrystalline silicon having a thickness of 1000 °;

FIG. 6 is a cross-sectional view showing a method of manufacturing the resistance element of the semiconductor device of the present invention shown in FIG. 1 in the order of steps.

FIG. 7 is a sectional view when the present invention is applied to a semiconductor device including a MOS transistor and a capacitor.

FIG. 8 is a process order sectional view showing a manufacturing method when the present invention is applied to a semiconductor device including a MOS transistor and a capacitor.

FIG. 9 is a cross-sectional view in the order of steps showing a manufacturing method in the case where the present invention is applied to a semiconductor device including a polycrystalline silicon resistor, a MOS transistor, and a capacitor constituting a circuit other than a ladder circuit.

FIG. 10 is a process diagram showing a state of a completed product when the present invention is applied to a semiconductor device including a polycrystalline silicon resistor, a MOS transistor, and a capacitor constituting a component other than a ladder circuit.

[Explanation of symbols]

Reference Signs List 101 silicon semiconductor substrate 102 p-type polycrystalline silicon resistor 103 insulating film 104 intermediate insulating film 105 aluminum wiring 106 protective film 107 photoresist 108 high-concentration impurity region of p-type 201 p-type silicon semiconductor substrate 202 field oxide film 203 1 Gate electrode made of polycrystalline silicon resistor 204 Capacitor electrode made of first polycrystalline silicon resistor 205 Interlayer insulating film 206 Second polycrystalline silicon resistor 207 Capacitor electrode made of second polycrystalline silicon resistor 208 P-type silicon N, which is of the opposite conductivity type to the semiconductor substrate
D-type diffusion layer 209 P-type diffusion layer having the opposite conductivity type to the N-type well region 210 N having the opposite conductivity type to the P-type silicon semiconductor substrate
Type well layer 211 P-type high-concentration impurity region 212 Gate insulating film 213 Thin-film high-resistance body with P-type impurity introduced 214 Thin-film low-resistance body with P-type impurity introduced 215 Thin-film low-level with N-type impurity introduced Resistor

Claims (19)

[Claims] 2. A semiconductor device according to claim 1, wherein the impurity introduced into the polycrystalline silicon resistor in the ladder resistance circuit composed of the polycrystalline silicon resistor is P-type. 2. The method according to claim 1, wherein P is introduced into said polycrystalline silicon resistor.
2. The semiconductor device according to claim 1, wherein the type impurity is BF2. 3. The semiconductor device according to claim 1, wherein the P-type impurity introduced into said P-type polycrystalline silicon resistor is boron. 4. The P-type polycrystalline silicon resistor has a thickness of 5
2. The semiconductor device according to claim 1, wherein the angle is from 00 to 1500 °. 5. The semiconductor device according to claim 1, wherein the P-type polycrystalline silicon resistor has a sheet resistance of 1 kΩ / □ to 25 kΩ / □. 6. The semiconductor device according to claim 1, wherein a temperature coefficient of said P-type polycrystalline silicon resistor is −4000 ppm / ° C. or less. 7. The length of said P-type polycrystalline silicon resistor is
The semiconductor device according to claim 1, wherein the thickness is 10 μm to 150 μm. 8. A step of forming an oxide film on a semiconductor substrate, a step of forming a polycrystalline silicon film of 500 ° to 1500 ° on the oxide film, and doping a P-type impurity in the polycrystalline silicon film region. Forming a region of the polycrystalline silicon film by etching the polycrystalline silicon film; and 1 × 10 ^{15 to} 5
× 10 ¹⁶ atom / cm ² doping, forming an intermediate insulating film on the oxide film and the polycrystalline silicon film, and forming the intermediate insulating film on the polycrystalline silicon film and the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: providing a contact hole; and providing a metal wiring in the contact hole. 9. A P-type impurity in the polycrystalline silicon film region.
BF which is a thing_Two1 × 10 ¹⁴~ 1 × 10^Fifteenatom / cm^TwoDoping
3. The method of manufacturing a semiconductor device according to claim 1, wherein
Law. 10. The method according to claim 1, wherein the P-type impurity doped in the polycrystalline silicon film region is boron. 11. A step of forming an oxide film on a semiconductor substrate
Forming a first polycrystalline silicon film on the oxide film
And doping an impurity into the first polysilicon film region.
And etching the first polycrystalline silicon film.
Forming a region of a first polycrystalline silicon film by etching
And a step including above the first polycrystalline silicon film region.
Forming an insulating film on the surface of the semiconductor substrate;
A second polycrystalline silicon film of 500 to 1500 mm on the insulating film
Forming a P-type impurity on the second polycrystalline silicon film.
1 × 10 objects¹⁴~ 1 × 10^Fifteenatom / cm^TwoDoping process
And etching the second polycrystalline silicon film by etching.
Forming a region of the second polycrystalline silicon film;
1 × 10 in part of the area of the polycrystalline silicon film^Fifteen~ 5 × 10 ¹⁶
atom / cm^TwoDoping step, the insulating film and the second
Forming an intermediate insulating film on the second polycrystalline silicon film
And the first polycrystalline silicon film and the second polycrystalline silicon film.
A capacitor film and the intermediate insulating film on the semiconductor substrate.
Providing a tact hole and metal wiring in the contact hole.
Providing a semiconductor device. 12. The insulating film according to claim 1, wherein said insulating film has a thickness of 300.degree.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the oxide film is 0 °. 13. The insulating film according to claim 1, wherein said insulating film has a thickness of 300 to 700.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the thermal oxide film has a laminated structure of a thermal oxide film having a thickness of 200 to 1000 ° and a thermal oxide film having a thickness of 100 ° or less. 14. A P-type impurity doped into a part of the second polycrystalline silicon film and a P-type impurity doped into a diffusion region of a MOS transistor having a P-type diffusion region are simultaneously introduced. 3. The method for manufacturing a semiconductor device according to claim 2, wherein: 15. A step of forming an oxide film on a semiconductor substrate, a step of forming a first polysilicon film on the oxide film, and a step of doping impurities in the first polysilicon film region. Forming a region of the first polycrystalline silicon film by etching the first polycrystalline silicon film; and forming an insulating film on a surface of the semiconductor substrate including a region above the first polycrystalline silicon film region. Forming, forming a second polycrystalline silicon film of 500 ° to 1500 ° on the insulating film, and adding a P-type impurity to the second polycrystalline silicon film at 1 × 10 ¹⁴ to 1 × 10 ¹⁵ atom / cm ² doping step, forming a second polycrystalline silicon film region by etching the second polycrystalline silicon film, and forming the second polycrystalline silicon resistor into the second polycrystalline silicon film. N-type impurity in silicon film 1 × 10 ^{15 to} 5 × 10 ¹⁶ a tom / cm ² doping step, and a P-type doped part of the region of the second polycrystalline silicon film forming the high resistance element and the capacitor electrode and the second polycrystalline silicon film forming the low resistance element. Doping an impurity at 1 × 10 ^{15 to} 5 × 10 ¹⁶ atom / cm ² , forming an intermediate insulating film on the insulating film and the second polycrystalline silicon film, A method for manufacturing a semiconductor device, comprising: providing a contact hole in a silicon film, a second polycrystalline silicon film, and the intermediate insulating film on the semiconductor substrate; and providing a metal wiring in the contact hole. 16. The semiconductor device according to claim 1, wherein the N-type impurity doped into the polycrystalline silicon film region is phosphorus.
6. The method for manufacturing a semiconductor device according to item 5. 17. The method according to claim 15, wherein the N-type impurity doped in the polycrystalline silicon film region is arsenic. 18. A P-type impurity and a P-type impurity which dope a part of a region of a second polycrystalline silicon film forming the high resistance element and a second polycrystalline silicon film forming the low resistance element. 16. The method of manufacturing a semiconductor device according to claim 15, wherein a P-type impurity for doping is simultaneously introduced into the diffusion region of the MOS transistor having the diffusion region. 19. A method for doping N in a region of a second polysilicon film constituting the N-type polysilicon resistor.
16. The method of manufacturing a semiconductor device according to claim 15, wherein an N-type impurity to be doped is simultaneously introduced into the diffusion region of the MOS transistor having the N-type impurity and the N-type diffusion region.