JPH0918012A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the area of an insular semiconductor thin film, and to bring into the state of high density by a method wherein a source and drain and a wiring metal are electrically connected on the side face part of the semiconductor thin film. SOLUTION: The semiconductor thin film 12, to be provided on an insulative board 10, is insularly separated for the separation of elements. Besides, a gate electrode 16 is provided on the semiconductor thin film 12 through a gate oxide film. A source and a drain 18 and 20 are provided on the semiconductor thin film 12 of the region which is in alignment with the gate electrode 16. Besides, an intermediate insulating film is provided in such a manner that the source and drain 18 and 29 on the side face of the semiconductor thin film 12 are exposed, and a wiring metal 26 is provided in such a manner that the source and drain 18 and 20 on the side face of the semiconductor thin film 12 are connected. To be more precise, the source and drain 18 and 29 and the metal wiring 26 are electrically connected on the side face of the semiconductor thin film 12. As a result, a contact window forming region is unnecessitated, and the occupation area of the insular semiconductor thin film 12 can be made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOS for forming a semiconductor element on an insulating substrate or a semiconductor thin film formed on an insulating film.
(Silicon On Sapphire) and SOI
The present invention relates to a structure of a wiring metal of a MOS transistor used in (Silicon On Insulator) and a manufacturing method thereof.

[0002]

2. Description of the Related Art By forming a semiconductor element on an insulating substrate or a semiconductor thin film on an insulating film, the junction capacitance between the source / drain and the substrate and between the wiring and the substrate is reduced, and the operating speed of the semiconductor integrated circuit device is increased. Research and development of such a semiconductor integrated circuit device have been actively carried out because of the advantages of high efficiency, low power consumption, and high density arrangement of semiconductor elements without the need for pn junction separation. . This conventional technique will be described with reference to SOS using a sapphire substrate.

An example of means for forming a MOS transistor in SOS is disclosed in Japanese Patent Laid-Open No. 59-112650. A manufacturing process for obtaining a conventional MOS transistor structure will be described with reference to the sectional view of FIG.

First, as shown in FIG. 7A, a semiconductor thin film 12 made of a single crystal silicon film formed on an insulating substrate 10 made of sapphire is etched to be separated into islands, thereby separating elements. To do.

Next, an oxidation treatment is performed in an oxygen atmosphere to form a gate oxide film 14 on the semiconductor thin film 12. Then, polycrystalline silicon is formed on the entire surface, and the gate electrode 16 is formed by photoetching.
Further, impurities are introduced into the region of the semiconductor thin film 12 aligned with the gate electrode 16 by ion implantation to form source drains 18 and 20.

Next, as shown in FIG. 7B, an intermediate insulating film 22 is formed on the entire surface, and a contact window 24 penetrating to the source / drain regions 18 and 20 is formed by photoetching. After that, a wiring metal 26 connected to the source drains 18 and 20 is formed through the contact window 24 to make electrical connection.

[0007]

In the conventional MOS transistor structure, as shown in FIG. 7B, the semiconductor thin film 12 is connected to the source / drain 18, 20 and the wiring metal 26.
Is done on the top of.

Therefore, in consideration of misalignment of the photomask when forming the contact window 24, it is necessary to increase the distance between the end of the contact window 24 and the gate electrode 16 to some extent to allow a dimensional margin. Moreover, the size of the opening of the contact window 24 cannot be extremely miniaturized. Therefore,
The distance from the end of the semiconductor thin film 12 to the gate electrode 16, that is, the length of the source / drain 18 and 20 regions is increased,
The area of the island-shaped semiconductor thin film 12 increases. As a result,
There is a problem that the high density, which is a feature of the semiconductor element on the insulating substrate, is not sufficiently dealt with.

An object of the present invention is to solve the above problems and
An object of the present invention is to provide a wiring metal structure capable of increasing the density of a semiconductor integrated circuit device and a manufacturing method for forming this structure.

[0010]

In order to achieve the above object, a semiconductor integrated circuit device and a manufacturing method thereof according to the present invention employ the following means.

In the semiconductor integrated circuit device of the present invention,
A semiconductor thin film provided on an insulating substrate or an insulating film and separated into islands, a source / drain provided on the semiconductor thin film in a region matching the gate electrode provided via a gate oxide film, and a source on the side surface of the semiconductor thin film An insulating film having an opening region for exposing the drain and the insulating substrate or insulating coating near the source drain, a first wiring metal provided so as to be embedded in the opening region of the insulating film, and the first wiring metal is exposed It is characterized in that it is provided with an intermediate insulating film provided with an opening region and a second metal wiring provided so as to be connected to the first wiring metal.

In the method for manufacturing a semiconductor integrated circuit device of the present invention, a semiconductor thin film is formed on an insulating substrate or an insulating film, an oxidation resistant film is formed on the semiconductor thin film, and the oxidation resistant film is formed by photoetching. In the patterning process, approximately half the thickness of the semiconductor thin film exposed from the oxidation resistant film is etched, and oxidation treatment is performed using the oxidation resistant film as an antioxidant film. Forming, removing the oxidation resistant film, performing oxidation treatment to form a gate oxide film on the semiconductor thin film, forming a gate electrode, and forming a source drain on the semiconductor thin film in a region matching the gate electrode, Photolithography is performed on the insulating film using a resist film so that the source / drain on the side surface of the semiconductor thin film and the insulating substrate or insulating film near the source / drain are exposed. A step of providing an opening area by,
A step of forming a wiring metal material on the entire surface and removing the resist film to form the first wiring metal so as to be embedded in the opening area of the insulating film, and a step of forming an intermediate insulating film on the entire surface and performing a photoetching process. Forming an opening region in the intermediate insulating film so that the first wiring metal is exposed, and forming a second wiring metal connected to the first wiring metal through the opening region of the intermediate insulating film. Characterize.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor integrated circuit device and a method of manufacturing the same according to the preferred embodiments of the present invention will be described below with reference to the drawings. Note that the following description will be made by taking an SOS MOS transistor as an example. FIG. 1 is a sectional view showing a wiring metal structure of a MOS transistor according to an embodiment of the present invention. First, the MOS transistor structure of the present invention will be described with reference to FIG.

A semiconductor thin film 12 provided on the insulating substrate 10.
Separates into islands for element isolation. Further, the semiconductor thin film 12 is provided with a gate electrode 16 via a gate oxide film.
Is provided. Then, the source drains 18 and 20 are provided in the semiconductor thin film 12 in the region matching the gate electrode 16. Further, the source / drain 18, 2 on the side surface of the semiconductor thin film 12
An intermediate insulating film is provided so that 0 is exposed, and a wiring metal 26 is provided so as to be connected to the source drains 18 and 20 on the side surface of the semiconductor thin film 12. That is, in the wiring metal structure of the present invention, the source / drain 18, 20 and the wiring metal 26 are electrically connected at the side surface of the semiconductor thin film 12.

In the wiring metal structure of the present invention, the electrical connection is not made on the upper surface of the semiconductor thin film 12 as in the prior art shown in FIG. 7B, and the source / drain 18, 20 is formed on the side surface of the semiconductor thin film 12. And the wiring metal 26 are electrically connected to each other. Therefore, in the present invention, the formation region of the contact window is unnecessary, and the area occupied by the island-shaped semiconductor thin film 12 is smaller than that in the conventional technique.

That is, the island-shaped semiconductor thin film 1 shown in FIG.
Source / drain 18 from the 2nd end to the 16th end of the gate electrode 16,
For the length dimension L of the 20 region, a length in which about 1 μm is added to the dimension considering the photomask misalignment of the gate electrode 16 is sufficient. For this reason, the area of the island-shaped semiconductor thin film 12 is reduced, the density can be increased, and the advantages of the semiconductor integrated circuit device on the insulating substrate or the insulating film can be further increased.

Next, an embodiment of the manufacturing method for forming the wiring metal structure of the MOS transistor of the present invention will be described with reference to the drawings. 2A and 2B are cross-sectional views showing a manufacturing method for forming the wiring metal structure of the MOS transistor of the present invention.

First, as shown in FIG. 2A, a semiconductor thin film of the first conductivity type is formed of a single crystal silicon film having a plane orientation of 100 on an insulating substrate 10 made of sapphire having a crystal orientation 1012. 12 is formed. This semiconductor thin film 12 is formed by an epitaxial growth method.
It is formed with a thickness of about 6 μm.

Then, a silicon oxide film (not shown) having a film thickness of about 100 nm is formed by a chemical vapor deposition method (CVD method).
Is formed on the entire surface. This silicon oxide film is used as an etching mask for the semiconductor thin film 12. Thereafter, a photosensitive resin is formed on the entire surface by a spin coating method, exposure processing and development processing are performed using a predetermined photomask, the photosensitive resin is patterned, and the patterned photosensitive resin is used as an etching mask. A silicon oxide film is patterned on the element formation region by photoetching for etching.

After that, the semiconductor thin film 12 is etched by using the patterned silicon oxide film as an etching mask to form an island-shaped semiconductor thin film 12 which is an element forming region.
To form The etching of the semiconductor thin film 12 is performed using an anisotropic etching solution obtained by adding isopropyl alcohol (C ₃ H ₇ OH) to an aqueous solution of potassium hydroxide (KOH) to form a silicon oxide film as an etching mask. Semiconductor thin film 12 in the non-existing region, that is, the element isolation region
Is completely removed. In this anisotropic etching,
The etching rate of the semiconductor thin film 12 depends on the plane index of the single crystal silicon film, and the 111 plane is extremely slower than the 100 plane. As a result, the side surface portion of the island-shaped semiconductor thin film 12 becomes an oblique surface.

Next, the silicon oxide film used as the etching mask is removed using a hydrofluoric acid-based etching solution. After that, oxidation treatment is performed at a temperature of 1000 ° C. for 25 minutes in a dry oxygen atmosphere to form a gate oxide film 14 having a film thickness of 30 nm on the semiconductor thin film 12.

After that, a polycrystalline silicon film is formed on the entire surface as a gate electrode material of the MOS transistor. This polycrystalline silicon film is formed with a film thickness of about 450 nm by the CVD method. Then, the polycrystalline silicon film is patterned by photoetching to form the gate electrode 16.

Next, the second conductivity type impurities are introduced into the semiconductor thin film 12 in the aligned region of the gate electrode 16 by the ion implantation method to form the source drains 18 and 20.
The amount of ion implantation for forming the source drains 18 and 20 is about 4 × 10 ¹⁵ cm ⁻² . As a result, the source drains 18 and 20 are formed on the surface and side surfaces of the semiconductor thin film 12.

Next, a thickness 5 mainly composed of a silicon oxide film
The intermediate insulating film 22 having a thickness of about 00 nm is formed on the entire surface by the CVD method. Thereafter, the intermediate insulating film 22 is left only on the semiconductor thin film 12 by the photoetching process to expose the source drains 18 and 20 on the side surface of the semiconductor thin film 12.
At this time, the intermediate insulating film 22 may slightly remain on the side surface of the semiconductor thin film 12, or the side surface and the semiconductor thin film 1 may be removed.
The surface of the semiconductor thin film 12 at the boundary between the two surfaces may be slightly exposed.

Next, as shown in FIG. 2B, aluminum is formed as the material of the wiring metal 26 on the entire surface by a vacuum deposition method, a sputtering method or the like. Then, a photoetching process is performed to form a wiring metal 26 connected to the side surface portion of the semiconductor thin film 12, and the source / drain 18, 2 is formed.
0 and the wiring metal 26 are electrically connected.

FIG. 3 is a cross-sectional view showing an embodiment of a method of forming a wiring metal of a MOS transistor of the present invention and showing a manufacturing method different from that of FIG.

The source / drain 18, 2 is formed on the semiconductor thin film 12 by the same manufacturing process as the method described with reference to FIG.
0 is formed, and then the intermediate insulating film 22 is formed on the entire surface by the CVD method. After that, a resist film 28, which is a photosensitive resin, is formed on the entire surface by a spin coating method, and the resist film 28 in the formation region of the wiring metal is formed by a photolithography process in which an exposure process and a development process are performed using a predetermined photomask. Remove. That is, the resist film 28 is formed on the semiconductor thin film 12 and the region where the wiring metal is not formed.

Next, aluminum is formed on the entire surface as the wiring metal 26. After that, the resist film 28 is removed to remove the film on the resist film 28, and the wiring metal 26 is formed by a so-called lift-off method. As a result, the source / drain 18, 2 on the side surface of the semiconductor thin film 12 is formed.
The wiring metal 26 that is electrically connected to 0 can be formed.

FIG. 4 shows an M different from the embodiment described above.
It is sectional drawing which shows the structure of the wiring metal of an OS transistor, and its manufacturing method. First, the structure of the MOS transistor will be described.

The structural difference from the MOS transistors shown in FIGS. 2 and 3 is that an opening region is provided in the intermediate insulating film 22 so that the side surface of the semiconductor thin film 12 and the insulating substrate 10 are exposed. Further, in the opening region, the source drain 18,
A first wiring metal 30 connected to the first wiring metal 30 is provided, and a second wiring metal 32 connected to the first wiring metal 30 is provided on the first wiring metal 30 and the intermediate insulating film 22. In the MOS transistor shown in FIG. 4, the surface step can be reduced and the surface can be flattened. Next, a manufacturing method for forming this structure will be described.

The source / drain 1 is formed on the semiconductor thin film 12 by the same method as the processing step described with reference to FIG.
8 and 20 are formed, and the intermediate insulating film 2 is further formed by the CVD method.
2 is formed on the entire surface.

Then, as shown in FIG. 4A, a resist film 28 which is a photosensitive resin is formed on the intermediate insulating film 22,
The photoetching process forms an opening region in which the semiconductor thin film 12 and the insulating substrate 10 are exposed. After the formation of this opening region, the resist film 28 used as the etching mask is not removed but remains.

After that, as the material of the first wiring metal 30,
Aluminum containing silicon and copper is formed on the entire surface by a vacuum deposition method or a sputtering method. After that, by the lift-off method of removing the resist film 28, the first side surface of the semiconductor thin film 12 and the insulating substrate 10 are first exposed in the opening region.
The wiring metal 30 is formed. As a result, the first wiring metal 30 connected to the source / drain 18, 20 can be formed so as to be embedded in the opening region.

Next, as shown in FIG. 4B, aluminum is formed as the material of the second wiring metal 32 on the entire surface by a vacuum deposition method or a sputtering method. Then, a second wiring metal 32 is formed on the first wiring metal 30 and the intermediate insulating film 22 by photoetching. As a result, the second wiring metal 32 connected to the first metal wiring 30
Can be formed.

FIG. 5 shows an M different from the embodiment described above.
It is sectional drawing which shows the structure of the wiring metal of an OS transistor, and its manufacturing method. First, the structure of the MOS transistor will be described.

The structural difference from the MOS transistors shown in FIGS. 2, 3 and 4 is that the metal which is an alloy film of silicon and a refractory metal is formed on the surface of the source / drain 18, 20 on the side surface of the semiconductor thin film 12. The point is that the silicide layer 34 is provided. By thus connecting the source / drain 18, 20 and the wiring metal 26 via the metal silicide layer 34, an effect that an even more reliable ohmic contact can be obtained between the wiring metal 26 and the source / drain 18, 20. With.

A metal silicide layer may be provided in the structure shown in FIG. That is, an opening region is provided in the intermediate insulating film so that the source / drain 18, 20 having the metal silicide layer formed on the side surface of the semiconductor thin film 12 and the insulating substrate 10 are exposed, and the first wiring metal is formed in the opening region. May be provided, and a second wiring metal connected to the first wiring metal may be provided. Next, an embodiment of a manufacturing method for forming the structure shown in FIG. 5 will be described.

The source / drain 1 is formed on the semiconductor thin film 12 by the same method as the processing step described with reference to FIG.
8 and 20 are formed, and the intermediate insulating film 2 is further formed by the CVD method.
2 is formed on the entire surface.

Then, as shown in FIG. 5A, a resist film (not shown) which is a photosensitive resin is formed on the intermediate insulating film 22, and the semiconductor thin film 12 is formed by photoetching.
The source / drain 1 is formed by forming the intermediate insulating film 22 only on the upper side.
8 and 20 are exposed.

Next, as shown in FIG. 5B, titanium (Ti) as a refractory metal is formed on the entire surface by a sputtering method to a thickness of about 100 nm. After that, 800 ℃
When heat treatment is performed at about a temperature, titanium reacts with silicon on the side surface of the semiconductor thin film 12 to form titanium silicide (TiSi ₂ ) which is the metal silicide layer 34.

After that, titanium not silicided is removed by etching with an etching solution composed of an aqueous solution of ammonia and hydrogen peroxide. As a result, the semiconductor thin film 1
The metal silicide layer 34 can be formed on the surfaces of the source / drain 18, 20 on the two side surfaces.

Next, as shown in FIG. 5C, aluminum is formed as the material of the wiring metal 26 on the entire surface by sputtering or vacuum evaporation. After that, the wiring metal 26 is formed by photoetching so as to be connected to the source drains 18 and 20 on the side surface of the semiconductor thin film 12.

In the above description, titanium is used as the refractory metal, but tantalum, molybdenum, or tungsten is used as the refractory metal.
Similar effects can be obtained.

FIG. 6 shows an M different from the embodiment described above.
It is sectional drawing which shows the structure of the wiring metal of an OS transistor, and its manufacturing method. First, the structure of the MOS transistor will be described.

A structural difference from the MOS transistors shown in FIGS. 2, 3, 4 and 5 is that the insulating film 38 and the intermediate insulating film 22 are provided on the insulating substrate 10. Further, an opening region is provided in the insulating film 38 and the intermediate insulating film 22 so that the side surface of the semiconductor thin film 12 and the insulating substrate 10 are exposed.

Further, the source / drain 1 is provided in this opening region.
A first wiring metal 30 connected to the wirings 8 and 20 is provided, and a second wiring metal 32 connected to the first wiring metal 30.
Is provided on the first wiring metal 30 and the intermediate insulating film 22 in the opening regions of the intermediate insulating film 22 and the insulating film 38.

A metal silicide layer may be provided in the structure shown in FIG. That is, the source / drain 18, 2 in which the metal silicide layer 34 is formed on the side surface of the semiconductor thin film 12.
0 and the insulating substrate 10 are exposed so that an opening region is provided in the insulating film 38 and the intermediate insulating film 22, and the first region is provided in the opening region.
The wiring metal may be provided, and the second wiring metal connected to the first wiring metal may be provided. Next, an embodiment of a manufacturing method for forming the structure shown in FIG. 6 will be described.

First, as shown in FIG. 6A, an oxidation resistant film 36 made of silicon nitride is formed on the semiconductor thin film 12 of the insulating substrate 10. This silicon nitride has a film thickness of 1
It is formed on the entire surface by a CVD method with a thickness of about 50 nm. At this time, a silicon oxide film may be formed between the semiconductor thin film 12 and the oxidation resistant film 36.

After that, the oxidation resistant film 36 is etched by photoetching and patterned so that the oxidation resistant film 36 remains only on the element region. Next, by wet etching or dry etching using an anisotropic etching solution, approximately half the film thickness of the semiconductor thin film 12 is removed by etching.

Thereafter, the oxidation resistant film 36 is used as an anti-oxidation film, and the semiconductor thin film 1 in the region not covered with the oxidation resistant film 36 is subjected to a so-called selective oxidation process of oxidizing in an oxygen atmosphere.
2 is oxidized to form an insulating film 38 in the element isolation region. Next, the oxidation resistant film 36 on the semiconductor thin film 12 is removed.

Next, as shown in FIG. 6B, a gate oxide film and a gate electrode 16 are formed. After that, the source drains 18 and 20 are formed on the semiconductor thin film 12 in the region matching the gate electrode 16, and the intermediate insulating film 22 is formed on the CV.
Formed on the entire surface by the D method. After that, the resist film 2 which is a photosensitive resin is formed on the intermediate insulating film 22 by a spin coating method.
8 is formed, and an opening region is formed by photoetching so that the side surface portion of the semiconductor thin film 12 and the insulating substrate 10 are exposed. After forming this opening region, the resist film 28 used as the etching mask is left without being removed.

After that, a first wiring metal 30 material made of aluminum containing silicon and copper is formed on the entire surface by a sputtering method. And by the lift-off method,
The first wiring metal 30 is formed so as to be embedded in the opening region between the side surface portion of the semiconductor thin film 12 and the insulating substrate 10.

Next, as shown in FIG. 6C, aluminum is formed on the entire surface as the material of the second wiring metal 32,
The second wiring metal 32 is formed by photoetching.

[0054]

As is clear from the above description, by adopting the present invention in which electrical connection is made on the side surface of the semiconductor thin film, the area occupied by the island-shaped semiconductor thin film can be reduced, and the high It is possible to achieve densification. Therefore, the advantage of the semiconductor integrated circuit device on the insulating substrate or the insulating film can be further enhanced.

As described above with respect to the SOS, the non-single crystal silicon film formed on the insulating substrate or the insulating film is single-crystallized by a single crystallizing means such as a laser beam and the single crystal silicon is used as a semiconductor element. Similar effects can be obtained by using the structure and manufacturing method of the present invention for an SOI for forming a film, a thin film transistor (TFT) formed on a non-single crystal silicon film on an insulating substrate, and the like.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a wiring metal structure of a semiconductor integrated circuit device and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a wiring metal structure of a semiconductor integrated circuit device and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a wiring metal structure of a semiconductor integrated circuit device and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a wiring metal structure of a semiconductor integrated circuit device and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a wiring metal structure of a semiconductor integrated circuit device and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a wiring metal structure of a semiconductor integrated circuit device and a manufacturing method thereof according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a wiring metal structure of a semiconductor integrated circuit device and a method for manufacturing the same in a conventional technique.

[Explanation of symbols]

 12 semiconductor thin film 18, 20 source / drain 22 intermediate insulating film 26 wiring metal 28 resist film 30 first wiring metal 32 second wiring metal 38 insulating film

Claims (2)

[Claims] 1. A semiconductor thin film which is provided on an insulating substrate or an insulating film and is separated into islands, a source / drain provided in the semiconductor thin film in a region matching the gate electrode provided through a gate oxide film, and a semiconductor thin film. An insulating film having an opening region exposing the source drain on the side surface of the substrate and the insulating substrate or insulating coating near the source drain, a first wiring metal provided so as to be embedded in the opening region of the insulating film,
An intermediate insulating film that provides an opening region where the wiring metal of is exposed,
A semiconductor integrated circuit device comprising: a second metal wiring provided so as to be connected to the first wiring metal. 2. A step of forming a semiconductor thin film on an insulating substrate or an insulating film, forming an oxidation resistant film on the semiconductor thin film, and patterning the oxidation resistant film by photoetching, and exposing from the oxidation resistant film. The process of etching approximately half the thickness of the semiconductor thin film, performing oxidation treatment using the oxidation resistant film as an antioxidant film, forming an insulating film in the region where the oxidation resistant film is not formed, and removing the oxidation resistant film. , A step of forming a gate oxide film on the semiconductor thin film by performing an oxidation process and forming a gate electrode, and forming a source / drain on the semiconductor thin film in a region matching the gate electrode, and using a resist film to A step of forming an opening region in the insulating film by photoetching so as to expose the source drain and the insulating substrate or the insulating coating near the source drain, and wiring gold over the entire surface. A step of forming a material and removing the resist film to form a first wiring metal so as to be embedded in an opening region of the insulating film; and a step of forming an intermediate insulating film on the entire surface and performing a photoetching process on the first wiring metal Forming an opening region in the intermediate insulating film so as to expose the first wiring metal and forming a second wiring metal connected to the first wiring metal through the opening region in the intermediate insulating film. Manufacturing method of integrated circuit device.