JPS5760868A - Cmos memory cell - Google Patents

Abstract

PURPOSE:To reduce cell size and to increase memory capacity, by a method wherein gate electrodes of a CMOS inverter are made common and N-channel and P- channel FETs are arranged under and above the gate electrodes respectively and each drain is connected. CONSTITUTION:A gate oxide film is made in a border 18 by selective oxidization for openings 10, 11 and poly Si layers 19-21, 27 are made and a source and a drain 31-33 are made by P-ion implantation. Next, an oxide film 36 is stacked to provide openings on the layers 19, 20 and a gate oxide film is made on the surface by thermal oxidization. Next, openings 12-14 are provided to stack poly Si 22, 23 and selective P<+> diffusion is applied.Furthermore, openings 15, 16 are provided after piling up an oxide film 35 and Al-Si layers 24-26 are made. As a result, an N- channel FET of a source 31, a drain 32, and a gate 20 connected to a power source VSS and a P-channel FET of a source 35, a channel 34, a drain 36, and a gate 20 connected to a power source VDD will be obtained and a CMOS inverter connecting each drain through diodes will be finished and N and P channel FETs are in solid arrangement which permits small size and memory capacity is increased an compared with the same size ones.