JPS59228764A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59228764A JPS59228764A JP58103800A JP10380083A JPS59228764A JP S59228764 A JPS59228764 A JP S59228764A JP 58103800 A JP58103800 A JP 58103800A JP 10380083 A JP10380083 A JP 10380083A JP S59228764 A JPS59228764 A JP S59228764A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- transistor
- region
- diffusion layer
- withstand voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 20
- 230000015556 catabolic process Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
（１１発明の利用分野
本発明は高耐圧ＭＯ８）ヲンジスタに関するもので、特
にドレイン拡散層が高濃度拡散層と低濃度拡散層で形成
された高耐圧ＭＯ８Ｏ８型トランジスタするものである
。DETAILED DESCRIPTION OF THE INVENTION (11) Field of Application of the Invention The present invention relates to a high voltage MO8O8 transistor, particularly a high voltage MO8O8 type transistor in which the drain diffusion layer is formed of a high concentration diffusion layer and a low concentration diffusion layer. It is.
（２１従来技術
従来の高耐圧ＭＯ８Ｏ８型トランジスタ第１図のような
ものがＣ以下オフセットゲート型トヲンジスタとよぶ）
ある。第１−０図は平面図、第１−ｂ図は断面図である
。以下の説明においては、説明の都合上、電子を担体と
したＮチャンネルトランジスタにつ込て説明するが、正
孔を担体としたＰチャンネルトランジスタについても同
様である。第１図におりてＩｌｌはＰ型基板、（２Ｉは
ソースとなるＮ型拡散層、ドレインは］３１の高濃度Ｎ
型拡散層と〔４）の低濃度Ｎ型拡散層で形成されている
。(21 Prior Art A conventional high-voltage MO8O8 type transistor as shown in Figure 1 is called a C or lower offset gate type transistor)
be. 1-0 is a plan view, and FIG. 1-b is a sectional view. In the following description, for convenience of explanation, an N-channel transistor using electrons as carriers will be explained, but the same applies to a P-channel transistor using holes as carriers. In Figure 1, Ill is a P-type substrate, (2I is an N-type diffusion layer that becomes a source, and the drain is] 31, a high concentration N
It is formed of a type diffusion layer and a low concentration N type diffusion layer [4].
５、ｌＯは絶縁膜、６はゲート電極、７はソース電極、
８はドレイン電極である。5, IO is an insulating film, 6 is a gate electrode, 7 is a source electrode,
8 is a drain electrode.
動作を簡単に説明すると、ドレイン電極８に電圧がかか
ると、４が低濃度であるため、空乏層が４の方に拡がる
ため高耐圧化が可能となるが、耐圧は９の低濃度拡散層
の角部で決まってしまｂ１１の濃度で決まる平面接合の
耐圧よりも低い値となってしまう。このため、１００ｖ
程度までの耐圧は比較的容易に得ることができるが、さ
らに高耐圧の用途には用いられず、さらに高耐圧の場合
には第２図のようなリングゲート型のトランジスタが提
案されている。１１はゲート電極であり１１の内部にド
レインとして１２の高濃度Ｎ型拡散層、１３の低濃度Ｎ
型拡散層が形成され、１１の外部にソースとして１４の
高濃度Ｎ型拡散層が形成されている。To briefly explain the operation, when a voltage is applied to the drain electrode 8, the depletion layer expands toward 4 because 4 has a low concentration, making it possible to achieve a high breakdown voltage. The breakdown voltage is determined by the corner of b11, which is lower than the breakdown voltage of a planar junction, which is determined by the concentration of b11. For this reason, 100v
Although it is relatively easy to obtain a breakdown voltage up to a certain level, it is not used for applications requiring even higher breakdown voltages.For even higher breakdown voltages, a ring gate type transistor as shown in FIG. 2 has been proposed. 11 is a gate electrode, and inside 11 there are 12 high-concentration N-type diffusion layers and 13 low-concentration N-type diffusion layers as a drain.
A type diffusion layer is formed, and 14 high-concentration N-type diffusion layers are formed outside of 11 as sources.
第２図のような八角形の場合には拡散層の角部１５の角
度は１３５度となり第１図の９０度に比較し大きくなる
ため拡散層の角部での電界集中がおさえられ第１図の場
合よフもさらに高耐圧化が可能となる。しかし、第２図
のようなリングゲート型の場合には、チャネルが放射状
となっているためにチャネル長、チャネル幅が一義に決
まらな因という本質的な欠点をもっている。さらに１２
の大きさは１６のドレイン電極をとる関係からあまシ小
さくできず、チャネル幅の小さいトランジスタが作れな
いという欠点もある。In the case of an octagon as shown in Figure 2, the angle of the corner 15 of the diffusion layer is 135 degrees, which is larger than the 90 degree angle in Figure 1, so that electric field concentration at the corner of the diffusion layer is suppressed and In the case shown in the figure, even higher voltage resistance is possible. However, the ring gate type shown in FIG. 2 has an essential drawback in that the channel length and channel width cannot be determined uniquely because the channel is radial. 12 more
The size of the transistor cannot be made much smaller because it requires 16 drain electrodes, and there is also the drawback that a transistor with a small channel width cannot be manufactured.
以上説明してきたように、第１図のような構造のトラン
ジスタは１００Ｖ程度の耐圧は簡単に得られるが、それ
以上の耐圧を得るのは難しいという問題点、第２図のよ
うな構造のトランジスタは高耐圧は比較的容易に得られ
るが、トランジスタの基本パラメータであるチャネル長
、チャネル幅が単純に寸法からは決まらないという問題
点があった。As explained above, the transistor with the structure shown in Figure 1 can easily obtain a breakdown voltage of about 100V, but the problem is that it is difficult to obtain a breakdown voltage higher than that. Although a high breakdown voltage can be obtained relatively easily, there is a problem in that the channel length and channel width, which are the basic parameters of a transistor, cannot be determined simply from the dimensions.
（３１本発明の目的
本発明はこのような問題点を解決するために、ドレイン
の低濃度拡散層の形状を五角形以上の多角形とすること
で、オフセットゲート形トヲンジスタとリングゲート形
トヲンジスタの利点であわせもつトランジスタを提供す
るものである。(31 Purpose of the Present Invention) In order to solve these problems, the present invention provides advantages of offset gate type transistors and ring gate type transistors by making the shape of the low concentration diffusion layer of the drain into a polygon of pentagon or more. The present invention provides a transistor that has the following characteristics.
以下、図面に基づいて詳細に説明する。Hereinafter, a detailed description will be given based on the drawings.
（４１本発明の実施例
第３図は本発明実施例である。１７は低濃度Ｎ膨拡散層
であ〕、第３−０図のように八角形をしている。このた
め従来例の第１図に比較し拡散層の角部１８で電界が集
中することなく、従来例よｐも高耐圧のトランジスタが
得られる。またチャネル幅は一部分が広いだけであるた
め実効的なチャネル幅は２０できマ少、チャネル長も通
常のトランジスタの様に１９できまる。このため寸法だ
けでＭＯＳトヲンジスタの特性が決まるという利点もあ
る。(41 Embodiment of the Present Invention FIG. 3 shows an embodiment of the present invention. 17 is a low concentration N expansion diffusion layer) and has an octagonal shape as shown in FIG. 3-0. Compared to FIG. 1, the electric field does not concentrate at the corner 18 of the diffusion layer, and a transistor with a high breakdown voltage can be obtained compared to the conventional example.Also, since the channel width is only partially wide, the effective channel width is 20, and the channel length can be reduced to 19, just like a normal transistor.Therefore, there is also the advantage that the characteristics of the MOS transistor are determined by the dimensions alone.
製造方法としても、１７の低沿度Ｎ型拡散層は、通常６
のゲート電極の端と５の絶縁膜の段差をマスクとして、
例えばイオン注入法によ多形成するため本発明の実施例
を得るためには５の絶縁膜の段差を２１のような形状と
することにより従来の製造方法と同様の製造方法でよい
。As for the manufacturing method, the 17 low creepage N-type diffusion layers are usually 6
Using the step between the edge of the gate electrode and the insulating film 5 as a mask,
For example, in order to obtain the embodiment of the present invention, since the multilayer structure is formed by ion implantation, a manufacturing method similar to the conventional manufacturing method may be used by making the step of the insulating film 5 into a shape like 21.
第３図においては、１７は八角形となっているが、六角
形等でもよい。In FIG. 3, 17 is an octagon, but it may be a hexagon or the like.
以上説明してきたようにオフセットゲート型トヲンジス
タの低濃度拡散層の形状を五角形以上の多角形とし、角
部の角度と９０度以上とすることにより高耐圧ＭＯ８）
ヲンジスタを形成することができる。As explained above, by making the shape of the low concentration diffusion layer of the offset gate type transistor into a polygon of pentagon or more, and making the angle of the corner part more than 90 degrees, high breakdown voltage MO8) can be achieved.
A single register can be formed.
第１図（α１は従来の高耐圧オフセットゲート型トヲン
ジスタの平面図。第１図１ｂ＋はその断面図、第２図（
ａｌは従来の高耐圧リングゲート型トヲンジスタの平面
図。第２図１ｂ＋はその断面図。第３図１ｃＬｌは本発
明の実施例の平面図。第３図（ｂｌはその断面図である
。
１・・Ｐ型ｓ７基板 ２ 、３ 、１２ 、１４・・高
洩度Ｎ型拡散層 ４ 、１３ 、１７・・低濃度Ｎ型拡
散層５、ｌＯ・・絶縁膜 ６，１１・・ゲート電極 ７
・・ソース電極 ８，１６・・ドレイン電極 ９，１５
．１８・・低濃度Ｎ型拡散層の角部 １９＠・チャネル
長 加・・チャネル幅 ２１・・絶縁膜の段差。
以 上
出願人 株式会社諏訪精工舎
代理人 弁理士最 上 務
第１図（り
第１図（り
第２図（α）
第２図（し）Figure 1 (α1 is a plan view of a conventional high voltage offset gate type transistor. Figure 1 1b+ is its cross-sectional view, Figure 2 (
al is a plan view of a conventional high voltage ring gate type transistor. FIG. 2b+ is a sectional view thereof. FIG. 3 1cLl is a plan view of an embodiment of the present invention. FIG. 3 (bl is its cross-sectional view. 1. P-type S7 substrate 2 , 3 , 12 , 14 . . . High leakage N-type diffusion layer 4 , 13 , 17 . . . Low concentration N-type diffusion layer 5, lO... Insulating film 6, 11... Gate electrode 7
・・Source electrode 8, 16 ・・Drain electrode 9, 15
．． 18... Corner of low concentration N-type diffusion layer 19 @ Channel length addition... Channel width 21... Step in insulating film. Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Mogami
Claims (1)
設けた第２導電形の低濃度不純物領域と、該低濃度不純
物領域内に設けた第２導電形の高濃度不純物領域からな
る、ドレイン領域と、該半導体基板の主表面領域に設け
られた第２導電型のソース領域と、該ドレイン領域と該
ソース領域の一部をおおうように絶縁膜を介して設けら
れたゲート電極からなるＭＩＳ型トヲンジスタにおいて
、該低濃度不純物領域の平面的形状が五角形以上の多角
形であることを特徴とする半導体装置。consisting of a semiconductor substrate of one conductivity type, a low concentration impurity region of a second conductivity type provided in the main surface region of the semiconductor substrate, and a high concentration impurity region of a second conductivity type provided within the low concentration impurity region, Consisting of a drain region, a second conductivity type source region provided in the main surface region of the semiconductor substrate, and a gate electrode provided with an insulating film interposed so as to cover a portion of the drain region and the source region. 1. A semiconductor device in an MIS type transistor, wherein the planar shape of the low concentration impurity region is a polygon of pentagon or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58103800A JPS59228764A (en) | 1983-06-10 | 1983-06-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58103800A JPS59228764A (en) | 1983-06-10 | 1983-06-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59228764A true JPS59228764A (en) | 1984-12-22 |
Family
ID=14363468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58103800A Pending JPS59228764A (en) | 1983-06-10 | 1983-06-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59228764A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2617642A1 (en) * | 1987-06-30 | 1989-01-06 | Thomson Semiconducteurs | Field-effect transistor |
| US6104064A (en) * | 1996-10-01 | 2000-08-15 | Advanced Micro Devices, Inc. | Asymmetrical transistor structure |
| US6274442B1 (en) | 1998-07-15 | 2001-08-14 | Advanced Micro Devices, Inc. | Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54147787A (en) * | 1978-05-09 | 1979-11-19 | Rca Corp | Insulated gate field effect transistor |
-
1983
- 1983-06-10 JP JP58103800A patent/JPS59228764A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54147787A (en) * | 1978-05-09 | 1979-11-19 | Rca Corp | Insulated gate field effect transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2617642A1 (en) * | 1987-06-30 | 1989-01-06 | Thomson Semiconducteurs | Field-effect transistor |
| US6104064A (en) * | 1996-10-01 | 2000-08-15 | Advanced Micro Devices, Inc. | Asymmetrical transistor structure |
| US6274442B1 (en) | 1998-07-15 | 2001-08-14 | Advanced Micro Devices, Inc. | Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same |
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