FR2617642A1 - Field-effect transistor - Google Patents
Field-effect transistor Download PDFInfo
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- FR2617642A1 FR2617642A1 FR8709240A FR8709240A FR2617642A1 FR 2617642 A1 FR2617642 A1 FR 2617642A1 FR 8709240 A FR8709240 A FR 8709240A FR 8709240 A FR8709240 A FR 8709240A FR 2617642 A1 FR2617642 A1 FR 2617642A1
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- 230000005669 field effect Effects 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000015556 catabolic process Effects 0.000 claims abstract description 5
- 238000013459 approach Methods 0.000 claims description 3
- 241000238631 Hexapoda Species 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Abstract
Description
TRANSISTOR A EFFET DE CHAMP
La présente invention concerne un transistor a effet de champ.FIELD EFFECT TRANSISTOR
The present invention relates to a field effect transistor.
De façon classique, comme cela est représenté sur la figure 1, un transistor à effet de champ comporte une région de source 4, une région de drain 3 et une région de canal recouverte par la grille de commande 20 de ce transistor. Les régions de source et de drain sont obtenues par implantation et diffusion de dopants dans le substrat . En dehors de ces zones le substrat est recouvert d'oxyde épais 1. Les réglons de drain et de source ont chacune une zone adjacente à la grille. En vue de dessus,. la grille à la forme d'un ruban, les régions de drain et de source sont délimitées de oxyde épais 1 par deux bords 11 et 12 de longueur suffisante pour permettre les connexions sur le circuit.Pour simplifier, les bords 11 et 12 ont été interrompus de manière à faire apparaître deux autres frontières 10 et 14 avec l'oxyde épais pour définir la zone active 100 du transistor. Bien entendu, les bords 11 et 12 peuvent, comme cela est représenté, avoir une direction rectiligne en se rapprochant des frontières 10 et 14, mais ils peuvent également avoir une direction oblique en se rapprochant de ces frontières. Conventionally, as shown in FIG. 1, a field effect transistor has a source region 4, a drain region 3 and a channel region covered by the control gate 20 of this transistor. The source and drain regions are obtained by implantation and diffusion of dopants in the substrate. Outside these areas the substrate is covered with thick oxide 1. The drain and source regions each have an area adjacent to the grid. In top view ,. the grid in the form of a ribbon, the drain and source regions are delimited by thick oxide 1 by two edges 11 and 12 of sufficient length to allow connections on the circuit. For simplicity, edges 11 and 12 have been interrupted so as to reveal two other borders 10 and 14 with the thick oxide to define the active area 100 of the transistor. Of course, the edges 11 and 12 can, as shown, have a rectilinear direction by approaching the borders 10 and 14, but they can also have an oblique direction by approaching these borders.
Les bords 10 et 11 délimitant les régions de drain et de source sont perpendiculaires aux bords de la grille dans les zones drain et source adjacentes à la grille. Ces deux bords 10 et 11 forment chacun avec chacun des bords de la grille un coin 21.The edges 10 and 11 delimiting the drain and source regions are perpendicular to the edges of the grid in the drain and source zones adjacent to the grid. These two edges 10 and 11 each form with each of the edges of the grid a wedge 21.
Les frontières 10, 11, 12, 14 de l'oxyde épais définissent la zone active du transistor. Les bords de la grille se trouvent à l'aplomb des régions source et drain du transistor.The borders 10, 11, 12, 14 of the thick oxide define the active region of the transistor. The edges of the gate lie directly above the source and drain regions of the transistor.
Or, ces transistors sont vulnérables en cas de surtension entre la région de drain et le substrat ou en cas de surtension entre la région de source et le substrat. However, these transistors are vulnerable in the event of an overvoltage between the drain region and the substrate or in the event of an overvoltage between the source region and the substrate.
On a constaté en effet, qu'en présence de surtension entre l'une de ces régions et le substrat, il se produit fréquemment un phénomène de claquage par avalanche engendré par des champs électriques intenses au niveau des jonctions. Le claquage du transisior se produit en particulier dans les coins 21 de la région drain 3 (ou source) qui sont situés du côté du canal. On constate que dans ces coins les champs électriques sont les plus intenses lors de la surtension. Si bien que lorsque se produisent de telles surtensions les coins 21 sont détériorés. It has in fact been found that, in the presence of an overvoltage between one of these regions and the substrate, there is frequently an avalanche breakdown phenomenon generated by intense electric fields at the junctions. The breakdown of the transisior occurs in particular in the corners 21 of the drain region 3 (or source) which are located on the side of the channel. It can be seen that in these corners the electric fields are most intense during the overvoltage. So that when such overvoltages occur the corners 21 are deteriorated.
Le problème général que l'invention résoud est celui de la protection d'un transistor à effet de champs contre les surtensions entre la région de drain et le substrat et/ou entre la région de source et le substrat. The general problem that the invention solves is that of protecting a field effect transistor against overvoltages between the drain region and the substrate and / or between the source region and the substrate.
Ce problème de protection du transistor est . résolu selon l'invention d'une façon inattendue par une modification de la forme du transistor. This transistor protection problem is. unexpectedly resolved according to the invention by a modification of the shape of the transistor.
La présente invention a donc pour objet un transistor à effet de champ comportant une région de source, une région de drain et une région de canal recouverte par une grille de commande, la région de source et/ou la région de drain ayant une zone adjacente à la grille, délimitée par deux bords formant deux coins avec la grille, ces deux coins étant situés du côté du canal, principalement caractérisé en ce que les coins du côté du canal sont biseautés ou arrondis pour réduire le risque de claquage dans ces coins en cas de surtension entre la région considérée et le substrat. The subject of the present invention is therefore a field effect transistor comprising a source region, a drain region and a channel region covered by a control gate, the source region and / or the drain region having an adjacent region. to the grid, delimited by two edges forming two corners with the grid, these two corners being located on the side of the channel, mainly characterized in that the corners of the side of the channel are bevelled or rounded to reduce the risk of breakdown in these corners in overvoltage between the region considered and the substrate.
L'invention sera mieux comprise à l'aide de la description détaillée qui est donnée à titre indicatif et nullement limitatif et qui est Illustrée par les schémas qui représentent
- La figure 1, une vue du dessus d'un transistor a effet de champ selon l'art antérieur
- La figure 2, une vue de dessus de la zone active 100 d'un transistor à effet de champ
- La figure 3, une vue de dessus d'un transistor à effet de champ selon une première variante d'un premier mode de réalisation de l'invention;
- La figure 4, une vue de dessus d'un transistor à effet de champ selon une deuxième variante du premier mode de réalisation de l'invention;;
- La figure 5, une vue de dessus de la zone active 500 d'un transistor à effet de champ selon une première variante d'un deuxième mode de réalisation;
- La figure 6, une vue de dessus du transistor à effet de champ selon la figure 4
- La figure 7, une vue de dessus d'un transistor à effet de champ selon une deuxième variante du deuxième mode de réalisation
La figure 2 représente la vue de dessus de la zone active 100 du transistor. Cette zone est définie par les frontières 10, 11, 12, 14 entre l'oxyde épais 1 et le transistor. Les bords 11 et 12 sont suffisamment longs pour permettre les connexions du transistor. Ces bords sont interrompus sur toutes les figures pour mieux montrer la zone active du transistor.Pour simplifier également la représentation, les bords 11 et 12 sont rectilignes proches des frontières 10 et 14, ils pourraient bien entendu être obliques à ce niveau là. On a donc, pour simplifier, délimité la zone active 100 du transistor par les frontières 10, 11, 12, 14.The invention will be better understood with the aid of the detailed description which is given by way of indication and in no way limitative and which is illustrated by the diagrams which represent
- Figure 1, a top view of a field effect transistor according to the prior art
- Figure 2, a top view of the active area 100 of a field effect transistor
- Figure 3, a top view of a field effect transistor according to a first variant of a first embodiment of the invention;
- Figure 4, a top view of a field effect transistor according to a second variant of the first embodiment of the invention;
- Figure 5, a top view of the active area 500 of a field effect transistor according to a first variant of a second embodiment;
- Figure 6, a top view of the field effect transistor according to Figure 4
- Figure 7, a top view of a field effect transistor according to a second variant of the second embodiment
FIG. 2 represents the top view of the active area 100 of the transistor. This area is defined by the borders 10, 11, 12, 14 between the thick oxide 1 and the transistor. The edges 11 and 12 are long enough to allow the connections of the transistor. These edges are interrupted in all the figures to better show the active area of the transistor. To also simplify the representation, the edges 11 and 12 are rectilinear near the borders 10 and 14, they could of course be oblique at this level. To simplify, we therefore delimited the active area 100 of the transistor by the borders 10, 11, 12, 14.
La définition de la zone active du transistor se fait de manière classique par un procédé d'oxydation localisée qui consiste en un premier temps à déposer du nitrure de silicium que l'on grave ensuite selon le motif définissant cette zone active. On procède ensuite à une oxydation du silicium là où il n'est pas protégé par le nitrure puis on retire ce nitrure. Les autres étapes sont décrites en référence à la figure 3 puisque cette figure 3 représente une vue de dessus complète du transistor à effet de champ. l,'étape suivante consiste à effectuer une oxydation en couche mince pour former l'oxyde de grille. On pratique ensuite un dépôt de silicium polycristallin que l'on grave pour définir la grille et des interconnexions.The definition of the active area of the transistor is done conventionally by a localized oxidation process which consists firstly in depositing silicon nitride which is then etched according to the pattern defining this active area. The silicon is then oxidized where it is not protected by the nitride and then this nitride is removed. The other steps are described with reference to FIG. 3 since this FIG. 3 represents a complete top view of the field effect transistor. The next step is to perform a thin layer oxidation to form the gate oxide. A polycrystalline silicon deposit is then practiced which is etched to define the grid and interconnections.
On procède par ailleurs de manière classique a une implantation de type n pour un transistor MOS à canal n, ce qui permet de définir de part et d'autre de la grille une région de drain et une région de source dans la zone active où l'implantation n'est pas masquée ni par l'oxyde épais, ni par la grille. In addition, a n-type layout is conventionally implemented for an n-channel MOS transistor, which makes it possible to define on either side of the gate a drain region and a source region in the active area where the he implantation is not masked neither by the thick oxide, nor by the grid.
La figure 3 représente donc le schéma complet du transistor dont la réalisation correspond aux étapes précédemment décrites mais dont le dessin de la grille 30 est différent des dessins classiques. Cette figure correspond à un premier mode de réalisation de l'invention. Ce premier mode consiste à utiliser une grille 30 en forme de ruban ayant deux bords longitudinaux 7 et 8 et deux extrémités 5 et 6, les extrémités étant situées au delà des frontières 11 et 12. Les extrémités 5 et 6 sont, selon l'invention, évasées à l'endroit où la grille s'approche des bords frontières 11 et 12. FIG. 3 therefore represents the complete diagram of the transistor, the production of which corresponds to the steps previously described but the design of the gate 30 of which is different from the conventional designs. This figure corresponds to a first embodiment of the invention. This first mode consists in using a grid 30 in the form of a ribbon having two longitudinal edges 7 and 8 and two ends 5 and 6, the ends being located beyond the borders 11 and 12. The ends 5 and 6 are, according to the invention , flared at the point where the grid approaches the border edges 11 and 12.
Selon une première variante de ce mode de réalisation, l'évasement consiste en un écartement des bords 7 et 8 de la grille, ces bords prenant en s'écartant, une forme arrondie définie par les arcs de cercle 9. According to a first variant of this embodiment, the flaring consists of a spacing of the edges 7 and 8 of the grid, these edges taking, by deviating, a rounded shape defined by the arcs of a circle 9.
L'évasement peut également consister en un évasement du bord 8 du côté du drain par rapport au bord 7 du côté de la source. Ainsi, au moins un bord, le bord situé du côté du drain, comporte en chacune de ses extrémités un arrondi 9. La projection verticale de ces arrondis intercepte les bords 11 et 12. The flaring can also consist of a flaring of the edge 8 on the side of the drain relative to the edge 7 on the side of the source. Thus, at least one edge, the edge located on the side of the drain, has at each of its ends a rounded 9. The vertical projection of these rounded intercepts the edges 11 and 12.
La figure 4 représente une deuxième variante du premier mode de réalisation du transistor selon l'invention. FIG. 4 represents a second variant of the first embodiment of the transistor according to the invention.
Cette variante consiste également à utiliser une grille en forme de ruban dont les extrémités 5 et fi s'évasent à l'endroit où la grille s'approche des bords frontières il et 12. Cependant selon cette variante les bords 7 et 8 du ruban ont une forme biseautée au lieu d'un arrondi. Les bords 7 et 8, ou le bord 8, au moins, (bord situé du côté de la région de drain), comporte en ses extrémités 5 et 6 un tronçon 13 biseauté. La grille est placée de sorte que la projection verticale de chaque tronçon 13 intercepte un côté 11 ou 12.This variant also consists in using a ribbon-shaped grid, the ends 5 and fi of which widen at the point where the grid approaches the border edges 11 and 12. However, according to this variant, the edges 7 and 8 of the ribbon have a beveled shape instead of a rounded one. Edges 7 and 8, or edge 8, at least, (edge located on the side of the drain region), has at its ends 5 and 6 a beveled section 13. The grid is placed so that the vertical projection of each section 13 intercepts a side 11 or 12.
Sur la figure 5, on a représenté la zone active 500 d'un transistor selon l'invention. Cette figure correspond à un deuxième mode de réalisation de l'invention dans laquelle, la frontière entre l'oxyde épais 1 et la zone active a un dessin différent du dessin classique. Cette frontière est constituée par les bords 51, 52, 10 et 14. Pour les mêmes raisons que celles énnoncées à propos de la figure 2, les bords 51 et 52 ont été interrompus. In Figure 5, there is shown the active area 500 of a transistor according to the invention. This figure corresponds to a second embodiment of the invention in which the border between the thick oxide 1 and the active area has a design different from the conventional design. This border is formed by edges 51, 52, 10 and 14. For the same reasons as those stated in connection with FIG. 2, edges 51 and 52 have been interrupted.
Cette figure représente une - vue de dessus du transistor. La région active 500 est entourée d'oxyde épais 1. This figure represents a - top view of the transistor. The active region 500 is surrounded by thick oxide 1.
Cette région active 500 a dans la partie relative à l'invention définie par les zones proches de la grille, la forme d'un diabolo ou d'une section diamétrale de poulie. La partie relative à l'invention est définie par les bords 51 et 52 et deux autres frontières fictives 40 qui sont tracées en traits pointillés pour délimiter ce que l'on entend par zone proches de la grille. Cette figure correspond donc à un deuxième mode de réalisation, mais également à une première variante de ce deuxième mode.This active region 500 has in the part relating to the invention defined by the zones close to the grid, the shape of a diabolo or of a diametrical section of pulley. The part relating to the invention is defined by the edges 51 and 52 and two other fictitious borders 40 which are drawn in dotted lines to delimit what is meant by zone close to the grid. This figure therefore corresponds to a second embodiment, but also to a first variant of this second mode.
Sur la figure 6, on a représenté le schéma complet du transistor vu de dessus, d'après le deuxième mode de réalisation. Le transistor a la forme d'un papillon dont la région de source 4 et la région de drain 3 représentent les ailes et dont la grille 60 représente le corps. In Figure 6, there is shown the complete diagram of the transistor seen from above, according to the second embodiment. The transistor has the shape of a butterfly whose source region 4 and drain region 3 represent the wings and whose gate 60 represents the body.
la grille 60 à la forme d'un ruban. Les bords 51 et 52 ont la forme d'une gorge au niveau de la région de canal. La gorge 42 correspondant À la gorge de la poulie et constituant la région de canal, s'évase en prenant une forme arrondie (selon cette première variante). Les bords frontières 51 et- 52 comportent donc au moins deux arrondis 41 ces arrondis étant situés du côté de la région du drain 3. Elle peut également comporter deux arrondis 41 du côté de la région de source 4. La grille est placée de sorte que les bords 61 et 62 de la projection verticale de cette grille 60 interceptent les arrondis 41. the grid 60 in the form of a ribbon. The edges 51 and 52 have the shape of a groove at the level of the channel region. The groove 42 corresponding to the groove of the pulley and constituting the channel region, flares taking a rounded shape (according to this first variant). The border edges 51 and 52 therefore comprise at least two rounded 41 these rounded being located on the side of the drain region 3. It can also include two rounded 41 on the side of the source region 4. The grid is placed so that the edges 61 and 62 of the vertical projection of this grid 60 intercept the rounded 41.
Sur la figure 7, on a représenté une vue de dessus d'un schéma complet d'un transistor selon l'invention, qui correspond à une deuxième variante de ce deuxième mode de réalisation. D'après cette variante la gorge 42 de la poulie s'évase en prenant une forme biseautée. La grille en forme de ruban ou de bande, est placée de sorte que les tronçons de biseau 43 des bords 51 et 52 interceptent le bord 61 (côté drain) de la projection verticale de la grille 60. Les tronçons de biseau 43 peuvent également intercepter le bord 62 (côté source) de la projection verticale de la grille 60. In Figure 7, there is shown a top view of a complete diagram of a transistor according to the invention, which corresponds to a second variant of this second embodiment. According to this variant the groove 42 of the pulley flares taking a beveled shape. The grid in the form of a ribbon or strip, is placed so that the bevel sections 43 of the edges 51 and 52 intercept the edge 61 (drain side) of the vertical projection of the grid 60. The bevel sections 43 can also intercept the edge 62 (source side) of the vertical projection of the grid 60.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8709240A FR2617642A1 (en) | 1987-06-30 | 1987-06-30 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8709240A FR2617642A1 (en) | 1987-06-30 | 1987-06-30 | Field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2617642A1 true FR2617642A1 (en) | 1989-01-06 |
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ID=9352698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR8709240A Withdrawn FR2617642A1 (en) | 1987-06-30 | 1987-06-30 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2617642A1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0504992A2 (en) * | 1991-03-22 | 1992-09-23 | Philips Electronics Uk Limited | A lateral insulated gate field effect semiconductor device |
| US6621123B1 (en) * | 1996-06-12 | 2003-09-16 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, and semiconductor integrated device |
| US6750517B1 (en) * | 2000-11-06 | 2004-06-15 | Taiwan Semiconductor Manufacturing Company | Device layout to improve ESD robustness in deep submicron CMOS technology |
| US6855606B2 (en) * | 2003-02-20 | 2005-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-rod devices |
| US7005330B2 (en) | 2003-06-27 | 2006-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for forming the gate electrode in a multiple-gate transistor |
| US7074656B2 (en) | 2003-04-29 | 2006-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
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| GB2020484A (en) * | 1978-05-09 | 1979-11-14 | Rca Corp | Integrated gate field effect transistors having closed gate structure with controlled avalanche characteristics |
| JPS56118349A (en) * | 1980-02-22 | 1981-09-17 | Fujitsu Ltd | Semiconductor device |
| JPS59228764A (en) * | 1983-06-10 | 1984-12-22 | Seiko Epson Corp | Semiconductor device |
| JPS604263A (en) * | 1983-06-22 | 1985-01-10 | Nec Corp | Mos field effect semiconductor device |
| JPS60119782A (en) * | 1983-12-01 | 1985-06-27 | Nec Corp | Semiconductor device |
| EP0239250A2 (en) * | 1986-02-28 | 1987-09-30 | Kabushiki Kaisha Toshiba | Short channel MOS transistor |
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1987
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|---|---|---|---|---|
| GB2020484A (en) * | 1978-05-09 | 1979-11-14 | Rca Corp | Integrated gate field effect transistors having closed gate structure with controlled avalanche characteristics |
| JPS56118349A (en) * | 1980-02-22 | 1981-09-17 | Fujitsu Ltd | Semiconductor device |
| JPS59228764A (en) * | 1983-06-10 | 1984-12-22 | Seiko Epson Corp | Semiconductor device |
| JPS604263A (en) * | 1983-06-22 | 1985-01-10 | Nec Corp | Mos field effect semiconductor device |
| JPS60119782A (en) * | 1983-12-01 | 1985-06-27 | Nec Corp | Semiconductor device |
| EP0239250A2 (en) * | 1986-02-28 | 1987-09-30 | Kabushiki Kaisha Toshiba | Short channel MOS transistor |
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| PATENT ABSTRACTS OF JAPAN, vol. 5, no. 197 (E-86)[869], 15 décembre 1981; & JP-A-56 118 349 (FUJITSU K.K.) 17-09-1981 * |
| PATENT ABSTRACTS OF JAPAN, vol. 9, no. 102 (E-312)[1825], 4 mai 1985; & JP-A-59 228 764 (SUWA SEIKOSHA K.K.) 22-12-1984 * |
| PATENT ABSTRACTS OF JAPAN, vol. 9, no. 115 (E-315)[1838], 18 mai 1985; & JP-A-60 4263 (NIPPON DENKI K.K.) 10-01-1985 * |
| PATENT ABSTRACTS OF JAPAN, vol. 9, no. 277 (E-355)[2000], 6 novembre 1985; & JP-A-60 119 782 (NIPPON DENKI K.K.) 27-06-1985 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0504992A2 (en) * | 1991-03-22 | 1992-09-23 | Philips Electronics Uk Limited | A lateral insulated gate field effect semiconductor device |
| EP0504992A3 (en) * | 1991-03-22 | 1993-06-16 | Philips Electronics Uk Limited | A lateral insulated gate field effect semiconductor device |
| US6621123B1 (en) * | 1996-06-12 | 2003-09-16 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, and semiconductor integrated device |
| US6750517B1 (en) * | 2000-11-06 | 2004-06-15 | Taiwan Semiconductor Manufacturing Company | Device layout to improve ESD robustness in deep submicron CMOS technology |
| US6855606B2 (en) * | 2003-02-20 | 2005-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor nano-rod devices |
| US7074656B2 (en) | 2003-04-29 | 2006-07-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
| US7701008B2 (en) | 2003-04-29 | 2010-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
| US8053839B2 (en) | 2003-04-29 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
| US8790970B2 (en) | 2003-04-29 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Doping of semiconductor fin devices |
| US7005330B2 (en) | 2003-06-27 | 2006-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for forming the gate electrode in a multiple-gate transistor |
| US7276763B2 (en) | 2003-06-27 | 2007-10-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for forming the gate electrode in a multiple-gate transistor |
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