FR2526586A1 - Insulated gate FET with extended gate depth - formed by depositing polycrystalline silicon in grooves of semiconductor substrate along channel between source and drain regions - Google Patents

Abstract

The insulated gate FET is formed in a semiconductor substrate and has a source region (10), a drain region (12) and a channel regions (14). The gate (24) has its depth (36) extended into at least one groove in the semiconductor along almost the entire length of the channel between the source and drain regions. The gate is insulated from the channel region by a thin insulating layer (26) which completely covers the interior surface of the grooves, whose depth is greater than their width. The upper surface of the channel region outside the slots is covered by a thin insulating layer itself covered by the gate. The gate is realized in polycrystalline silicon. The transistor fabrication procedure consists in first forming grooves in the semiconductor substrate by reactive ionic etching. The silicon surface is then oxidised to create a thin insulating layer. Finally, polycrystalline silicon is deposited inside the grooves and over the intervals between the grooves. This structure reduces the resistance of the transistor without increasing its surface.

Description

DEEP GRID FIELD EFFECT TRANSISTOR
AND MANUFACTURING METHOD
The present invention relates to a field effect transistor and it aims to obtain a transistor having a reduced resistance in the on state.

 FIGS. 1 and 2 show an example of a conventional MOS (metal-oxide-seniconductive) transistor structure, respectively in longitudinal section (fig 1) and in cross section (fig 2) along line A-A in FIG. 1.

 The transistor, formed on a silicon substrate, co # carries a source region 10, doped by an impurity of a first type of conductivity, for example Nt (N channel MOS), a drain region 12, of the same type N +, a channel region 14 of the opposite type, P, separating the source region from the drain region. These regions are located inside an active transistor zone delimited by thick silicon oxide isolation walls 16 under which P-type doped regions 18 can be provided, avoiding the creation of an inversion layer. conductivity under the thick oxide. A source electrode 20 of polycrystalline silicon comes into contact with the source region 10 and a drain electrode 22 comes into contact with the drain region 12.

A gate electrode 24, also made of polycrystalline silicon, overhangs the channel region between the source and the drain and is isolated from it by a thin insulating layer 26 (made of silicon oxide).

 Aluminum conductors 28, 30, 32 in contact with the source, drain and gate electrodes respectively, serve to connect this transistor to other circuit elements. A protective oxide 33 covers the assembly.

 This basic structure of an insulated gate MOS transistor is only an example defined summarily to show the contribution of the present invention, but this contribution would be the same for a transistor of different structure, for example a transistor whose electrodes would be interdigitated, a D type MOS transistor (diffused channel MOS) whose proper P type channel region would occupy only a small part of the interval between the source and the drain, etc.

 In the transistor of FIG. 1, the resistance in the on state is defined, apart from the resistance of the connections, essentially by the resistance of the inversion layer of conductivity type formed under the gate 24 when the latter is worn. at a sufficient potential (positive for an N-channel transistor). This inversion layer is a thin zone 34 extending throughout the channel region 14, immediately below the thin oxide 26 overhangs by the grid 24 in this zone of thin thickness e, the type of conductivity of the semiconductor, which is Normally the P type (for an N channel transistor), is inverted and becomes N due to the proximity of the gate, the positive potential of which attracts a large amount of negative mobile electrical charges. calls the N-type channel between the source and the drain.

 The inherent resistance of this layer obviously depends on its length L (distance between source and drain region), on its width W (transverse distance over which the grid is only separated from silicon by thin oxide), its thickness e, and the conductivity of the silicon in the layer. These last two characteristics, thickness and conductivity are assumed to be fixed for a given potential of the gate, a given thickness of silicon oxide, and a given initial conductivity of the channel. The length L is reduced as much as possible to the extent that technology allows. To decrease the resistance of the transistor, it would be necessary to increase the section of passage of the current, thus in practice to increase the width (W) of the transistor, but that would be at the price of an increase in the surface of this one, which is often undesirable.

 The present invention therefore proposes a new transistor structure making it possible to increase the distance W over which the inversion layer extends (transversely to the direction of current flow between source and drain), without increasing the surface of the transistor.

 The transistor according to the invention comprises a gate extending deep into the substrate over practically the entire length of the channel between the source region and the drain region, inside at least one groove formed in the semiconductor, the grid being isolated from the channel region by a thin insulating layer completely covering the inner surface of the groove.

 The groove (or grooves) is preferably deeper than wide. Outside the grooves, the channel region is covered with a thin insulating layer which is itself covered by the grid.

 The grid is preferably made of polycrystalline silicon deposited in the vapor phase at low pressure.

Other characteristics and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the accompanying drawings in which
- Figures 1 and 2 already described represent a MOS transistor of conventional type
- Figure 3 shows in cross section the modification made according to the invention on the transistor shown in Figure 2
- Figures 4 and 5 show in longitudinal section the transistor of Figure 3, respectively along the lines CC and DD of Figure 3, and they show the modification made according to the invention with respect to the transistor shown in Figure 1.

 - Figure 6 shows a perspective view, partially exploded, of the transistor according to the invention, before deposition of protective oxide and metal contacts.

 - Figures 7a to 7i show the main stages of manufacturing the transistor according to the invention.

 In FIGS. 3 to 6, the same references have been used as in FIGS. 1 and 2 to designate the same elements.

 In FIG. 3, representing the analog of FIG. 2, that is to say a transistor seen in cross section, along the line A'A 'of FIG. 4 which is a longitudinal section, it can be seen that the gate 24 of the transistor according to the invention is not simply constituted by a planar layer of polycrystalline silicon, but it has extensions 36 deep in the substrate, the thin oxide layer 26 extending all around these extensions to isolate them from the channel region. More specifically, the extensions are located inside grooves formed in the monocrystalline silicon of the substrate, these grooves being entirely covered internally with a thin insulating layer (of oxide); the grooves extend over practically the entire length L of the channel between the source and the drain, as can be seen in FIG. 4 which represents a section along the line CC in FIG. 3 therefore a longitudinal section in the vertical plane of symmetry of a groove.

 Between two grooves, if there are several (which is desirable), the grid is in the form of a horizontal surface covering thin oxide formed on the upper surface of the channel; Figure 5 shows a section along the line DD of Figure 3, so a section in a vertical plane between two grooves. It is therefore a section quite similar to that of a normal transistor (Figure 1).

 If we refer again to FIG. 3, and with reference to FIG. 2, we see that the width over which the inversion layer extends is no longer the width of the transistor itself. It is much more important because the inversion layer extends sinuously over the entire periphery of the extensions 36 of the grid; in fact, the inversion layer exists everywhere where the grid is separated from the channel region 14 only by a thin oxide layer.

 The more numerous and deep the grooves, the more the effective width of the inversion layer is increased relative to the width of the transistor, provided that the Nt layer 12 extends fairly deeply.

 Therefore, without having to increase the surface thereof, one can significantly reduce the resistance of the transistor in the on state. This reduction in resistance is moreover done without creating a parasitic capacitance due to the inversion layer if one takes grooves sufficiently close to one another so that the inversion layers of two conductive faces opposite meet practically.

 Figure 6 shows, in a more visible perspective, the arrangement of the electrodes of the transistor, with the gate electrode 24 partially cut to show the parallel grooves 38 formed in the channel region; in this figure, the protective oxide 33 has been removed and the conductive contacts 28, 30, 32 have not been shown.

 We will now describe with reference to FIGS. 7a to 7i the essential steps of a manufacturing method making it possible to arrive at the transistor structure according to the invention.

 Starting from a semiconductor substrate, for example of P-type monocrystalline silicon, a step of delimiting an active transistor area is carried out if necessary by forming a thick silicon oxide wall 16 surrounding this area, by a conventional localized oxidation process comprising a spite of thin silicon oxide, a spite of silicon nitride, an etching of nitride to finish the active areas, an implantation of boron in the inactive areas not covered with nitride, for forming the Pf 18 type layers under the thick oxide walls, prolonged oxidation to form thick oxide, dissolution of the nitride and surface deoxidation to expose the monocrystalline silicon in the active areas. These steps are quite conventional.

 We then try to make the grooves (38) in polycrystalline silicon. For this, one can deposit on the substrate a layer of aluminum 40 (by vacuum evaporation), then a layer of protective resin 42 (fig 7a).

 The resin 42 is etched so as to leave it remaining only at the desired locations for the grooves. Aluminum is anodized where the resin no longer protects it, to transform it into alumina 44, by passage through a bath of sulfuric or phosphoric acid (FIG. 7b).

 The resin is then eliminated and the aluminum 42 remaining under the resin is dissolved and an anisotropic dry etching (ionic etching reactive with sulfur fluoride for example) of the monocrystalline silicon of the substrate is carried out. Alumina 44 constitutes a protective mask outside the groove areas.

The grooves 38 are thus formed (Figure 7c).

 The alumina 44 is eliminated and a thin oxidation of the substrate is carried out in order to create, throughout the active area, including over the entire interior surface of the grooves 38, a thin oxide layer 26 which is the gate oxide of the transistor, a few hundred angstroms thick (Figure 7d).

 This oxide 26 is etched to strip the contact regions 46 for the source and drain electrodes (Figure 7e).

 A layer of polycrystalline silicon 48 is deposited (in the vapor phase at low pressure), for example by decomposition of silane optionally in the presence of phosphine. Despite the low pressure, the advantage of having a high covering power so that the polycrystalline silicon is deposited inside the grooves and can fill them completely if they are sufficiently narrow (Figure 7f).

 It is then possible to doping with phosphorus to strongly dop the polycrystalline silicon which could thus serve as a source of phosphorus diffusion for the monocrystalline silicon of the substrate. Source and drain regions 10 and 12 are therefore created below the places where the polycrystalline silicon is in contact with the monocrystalline silicon due to the elimination of thin oxide zones 26 (FIG. 7g).

 It would also be possible to consider deep doping prior to the deposition of polycrista # llin silicon to standardize the channel width between the top and bottom of the grooves.

 The polycrystalline silicon is then etched in a pattern intended to form three separate electrodes and interconnections: a source electrode 20 comprising a part in contact with the source region 10, a drain electrode 22 comprising a part in contact with the region of drain 12, and a gate electrode 24 whose length is practically equal to the length of the grooves 38 (Figure 7h).

 One can then carry out an arsenic implantation to dop monocrystalline silicon where it is not covered with polycrystalline silicon or thick oxide, ie between the source electrode and the gate electrode. The source 10 and drain 12 regions are thus extended to the edge of the grid so that the channel region (between source region and drain region) is entirely overhung by the grid electrode without this it does not overflow the source and drain regions (Figure 7i).

 The manufacturing process conventionally ends with a deposition of silicon oxide at low temperature, an etching of the oxide to strip the polycrystalline silicon in order to make contacts, a deposition of an aluminum-silicon metal compound to make conductive connections, an etching of this metal deposit, a deposit of protective silicon oxide, and an opening of contact pads for external connections.

 This leads to the transistor structure according to the invention. For example, the grooves can be 5 microns deep or more, a few microns wide, and they can be spaced 1 to a few microns apart.

 Alternatively, one could form the alumina mask 44 protecting the silicon during the etching of the grooves by a "lift-off" process: a layer of resin is deposited which is etched leaving the resin to remain location of grooves only; an alumina deposition is then carried out by sputtering; then, the resin is eliminated, which removes the alumina covering the resin but not the alumina deposited at the locations not covered with resin

Claims (7)

 1. An insulated gate field effect transistor formed in a semiconductor substrate and comprising a source region (10), a drain region (12) and a channel region (14), characterized in that the gate (24 ) extends deep into the semiconductor over practically the entire length of the channel between the source region and the drain region, inside at least one groove (38) formed in the semiconductor, the grid being isolated from the channel region by a thin insulating layer (26) completely covering the inner surface of the groove.  2. Transistor according to claim 1, characterized in that the groove (38) is deeper than wide.  3. Transistor according to one of claims 1 and 2, characterized in that the upper surface of the channel region outside the grooves is covered with a thin insulating layer (26) itself covered by the grid (24 ).  4. Transistor according to one of claims 1 to 3, characterized in that the grid is made of polycrystalline silicon.  5. Method of manufacturing a field effect transistor, characterized in that it comprises a step of forming grooves (38) in a semiconductor substrate, followed by oxidation of the surface of the silicon, to create a thin layer of gate oxide (26) including inside the grooves (38), and a step of depositing polycrystalline silicon inside the grooves and above the interval between the grooves.  6. Method according to claim 5, characterized in that the grooves are hollowed out by reactive ion etching to a depth greater than their width.  7. Method according to claim 6, characterized in that an alumina mask is formed outside the location of the grooves to be dug.