KR930009478B1 - Insulated gate type fet on soi structure - Google Patents

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Description

Gate Insulated Field Effect Transistor on SOI Structure

1 is a diagram showing the relationship between the drain voltage and the drain current characteristics of transistors with and without a kink phenomenon.

2 is an output pulse waveform diagram of a source follower circuit having an overshoot caused by a kink phenomenon.

3A is a cross sectional view of a conventional SOI type MOS transistor.

3b or 3a is a plan view of the conventional transistor of FIG.

4 is a cross sectional view of the manufacturing stage of the structure of the first preferred embodiment of the present invention.

5 is a plan view of the transistor of FIG.

6 is a graph of drain voltage versus drain current characteristics of the transistor of FIG.

7 is a cross sectional view of the manufacturing stage of the structure of the second preferred embodiment of the present invention.

8 is a graph of drain voltage versus drain current characteristics of the transistor of FIG.

9 is a cross sectional view of the manufacturing stage of the structure of the sixth preferred embodiment of the present invention.

10 is a graph of drain voltage versus drain current characteristics of the transistor of FIG.

11 is a cross sectional view of a seventh preferred embodiment of the present invention.

The present invention relates to an insulated gate type FET (field effect transistor), and in particular, SOI (Si

An insulating gate type FET formed in a semiconductor substrate having a licon on insulator) structure.

It is well known that MOS (metal oxide semiconductor) FETs formed on SOI substrates exhibit kink in drain voltage-current characteristics. The correlation between the drain current and the drain voltage in the state where the gate voltage is kept constant is shown in FIG. 1, and in the figure, the FET on the SOI increases its drain current as compared to bulk transistors without kink. Is shown. The transistor without the kink phenomenon causes an overshoot in the form of the output voltage of the source follower circuit when the pulse voltage is input to the gate electrode, as shown in FIG.

It is known that when the semiconductor substrate on the SOI substrate is as thin as 1,000 GPa, the kink phenomenon does not appear, but when the semiconductor substrate is thicker than 3,000 GPa. However, it is very difficult to form a 1,000 Å thick semiconductor substrate on an SOI substrate, and thus a manufacturing cost is much higher than that of a semiconductor substrate having a thickness of about 1 탆 on an SOI substrate. Therefore, there has been a demand for the development of a semiconductor device substrate which does not cause kink phenomenon even when the semiconductor substrate thickness is about 1 μm. The cause of the kink is presumed to be due to the fact that a part of the element substrate near the insulating substrate is floating in the lower portion of the channel and the potential during operation changes.

In order to suppress substrate power fluctuations, a method in which a substrate contact electrode is provided using a region extending from a channel to a side portion thereof is described in Japanese Patent Laid-Open No. 52-36982 as described below.

3A is a cross-sectional view of an essential part of a transistor of the prior art. 3B is a plan view showing the electrode arrangement. In FIG. 3, reference numeral 1 denotes a support substrate, 2 an insulating layer, 21 an insulating film, 3 a semiconductor substrate, 31 a channel, 32 a substrate contact, (4) is an isolation region, (5) is a gate electrode, (51) is a gate insulating oxide film, (52) is an oxide film, (55) is a gate electrode contact, (6) is a source region, and (61) is a source contact (7) denotes a drain region, and (71) denotes a drain contact, respectively. The SOI substrate is composed of a support substrate 1, an insulating layer 2, and a semiconductor substrate 3. As shown in FIG. 3B, a substrate contact 32 is formed in a portion of the semiconductor substrate that extends laterally from the channel 31 under the gate electrode 5. The substrate contact 32 is connected to the source contact 61 through an external wiring, and is usually grounded. In such a configuration, the distance d (shown in FIG. 3B) between the channel 31 and the substrate contact 32 is long, causing an increase in electrical resistance, thereby causing fluctuations in the channel potential, thus completely suppressing the kink phenomenon. Can't. In addition, there is a drawback that a mask process is further required for the installation of the substrate contact, and the area occupied by each transistor is increased.

A general object of the present invention is to provide an SOI type insulated gate type FET which suppresses the kink phenomenon of drain current characteristics.

It is also an object of the present invention to provide an SOI type insulated gate type FET capable of high density integration.

The SOI type insulated gate type FET according to the present invention is a region containing a metal impurity such as aluminum or tungsten on the source region, a region containing an excessively diffused semiconductor impurity than a normal source region, an amorphous source region or a material of the source region. A layer of a material having a coefficient of thermal expansion different from that of thermal expansion is formed so that the electrical resistance component crossing the pn-junction of the source region is configured to be smaller than the resistance component crossing the pn-junction of the drain region.

These and other features and advantages of the present invention can be clearly understood from the following description with reference to the drawings. Like reference numerals in the previous drawings denote like sites.

The invention is described below with reference to the preferred embodiments.

In the fabrication of the SOI type insulated gate transistor of the first preferred embodiment of the present invention, as shown in FIG. 4A by the wafer bonding and thinning method or the SIMOX (separation by oxygen injection) method, 500 µm thick of silicon. An SOI substrate was fabricated by forming an insulating layer 2 of 1 mu m thick of SiO ₂ (silicon dioxide) on a supporting substrate of < _{RTI ID} = 0.0 > and a 1 mu m thick semiconductor substrate 3 of p-type silicon thereon. By known techniques, an isolation region 4 of 1 탆 thickness and a gate electrode 5 of polycrystalline silicon are formed on the SOI substrate, for example, for isolation of adjacent transistors. Next, as shown in FIG. 4B, metal ions, for example, aluminum ions (Al ⁺ ) are typically formed on a part of the semiconductor substrate 3 under conditions of ⁵⁰ kev and dose amount of 1 × 10 ¹⁵ cm ⁻² . It is implanted to form a source region, and other regions are masked with a resist. Next, as shown in FIG. 4C, after removing the resist, arsenic ions (As ⁺ ) as an n-type impurity are typically implanted into the entire surface under conditions of 100 kev and dose amount 5 × 10 ¹⁵ cm ⁻² . Next, as shown in FIG. 4D, the exposed surface of the polycrystalline silicon gate electrode 5 is oxidized by a known heat treatment method to form an insulating oxide film 52 of 500 kV. During the heat treatment oxidation process, the ion-implanted impurities are diffused so that arsenic impurities form the source region 6 and the drain region 7, and aluminum impurities are formed between the source region 6 and the semiconductor substrate 3. The pn-junction is reached, while the region under the gate electrode 5 becomes the channel 31. Therefore, the impurity concentration is approximately 1.5 × 10 ²⁰ cm ⁻³ in the drain and source regions, and aluminum concentration 3 × 10 ¹⁹ cm ⁻³ in the source region 6.

Next, as shown in FIG. 4E, a typical 1 탆 thick insulating film 21 made of PSG (phospho silicate glass) is deposited by the known technique on the entire surface of the substrate prepared above. By using a known photolithography technique, a contact hole is formed in the insulating film 21 to expose the source region 6, the drain region 7, and the gate electrode 5. After sputtering aluminum representatively on the entire surface by a known technique, the aluminum film is patterned to form the source contact 61, the drain contact 71 and the gate contact 55. A plan view of these contacts is shown in FIG. 5, in which the contacts 32 of the prior art semiconductor substrates are not shown.

The interface between the semiconductor substrate 31 and the arsenic diffused source region 6 forms a pn-junction. The metal impurity diffused into this source region 6, i.e. aluminum, further diffuses to the pn-junction, whereby the function of a leak current path through the center of aluminum atom carrier generation, i.e., through the pn-junction do. Thus, the current in the diode of the pn-junction increases in the forward and reverse directions. This increased leakage current, in particular, the forward increased current inevitably eliminates the potential difference between the semiconductor substrate 31 'and the source region 6 located below the channel. In other words, the floating of the semiconductor substrate 31 ′ under the channel 31 can be prevented. Therefore, the kink phenomenon can be suppressed.

6 shows the diode characteristics of the pn-junction of the source region compared with that of the conventional SOI MOS transistor, where V _F represents the forward voltage in volts, and I _F represents the μA of the pn-junction diode. Indicates the forward current of the unit. Diode characteristics are measured by a contact electrode (not shown) formed for an experiment to lead a semiconductor substrate. Also, from the relationship between the drain voltage and the drain current characteristic (not shown), the drain current due to the kink phenomenon of the SOI MOS transistor in which aluminum ions are implanted according to the present invention is reduced by 20%, and the overshoot of the AC operation is 15 A% reduction can be observed.

7 is a cross sectional view of the manufacturing stage of the second preferred embodiment of the present invention. The SOI substrate is composed of a support substrate 1 made of silicon, an insulating layer 2 and a semiconductor substrate 3 made of p-silicon and is essentially the same as that of the first embodiment shown in FIG. In addition, as shown in FIG. 7A, a device isolation region 4, a gate insulating film 51, a gate electrode 5 made of polycrystalline silicon, and an oxide film 53 are formed on the SOI substrate by a known technique. . Next, as shown in FIG. 7B, an oxide film 54 is formed on the sidewall of the gate electrode 5 by a known technique. Next, a tungsten (W) film 8 is deposited to a thickness of, for example, 3000 kPa on the substrate of FIG. 7B by CVD, and a Si ₃ N ₄ (silicon nitride) film 81 is deposited on the entire surface thereof. For example, it is deposited to a thickness of 500 mW. Then, by the known photolithography technique, the tungsten 8 and the Si ₃ N ₄ film 81 are patterned as in the seventh c-c to leave only the region to be the source region. Next, the patterned substrate is typically heated at 1100 ° C. for 30 minutes in nitrogen gas. Tungsten deposited on the surface by this heat treatment process is diffused to a part of the semiconductor substrate to form the source region 6. Next, as shown in FIG. 7D, arsenic ions (As ⁺ ) are implanted into the entire surface of the substrate of FIG. 7C at a representative amount of 100 kev and a dose amount of 5 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 7E, a SiO ₂ insulating film 22 having a thickness of 1000 kPa is typically deposited on the substrate of FIG. 7D by CVD, and is typically heated in nitrogen gas at 1000 DEG C for 20 minutes. By this heat treatment, arsenic impurities are diffused into the source region 6 and the drain region 7. The concentration of arsenic impurities in the source and drain regions is then 1.5 × 10 ²⁰ cm ⁻³ . During the heat treatment process, tungsten diffuses into the source region and its impurities precipitate to generate spikes across the pn-junction between the source region 6 and the channel region 31. This is because the impurity concentration is larger than the solid solubility of the impurities. Next, as shown in FIG. 7F, a contact is laminated on the entire surface of the insulating films 22 made of PSG in the same manner as in the first preferred embodiment, and the source region 6 and the drain region 7 are exposed. The hole is drilled, aluminum is sputtered on the entire surface of the surface, and the sputtered aluminum is patterned to form the source contact electrode 61 and the drain contact electrode 71. The planar arrangement of the source 6, drain 7 and gate electrode 5 is the same as in the first embodiment. In such a configuration, the precipitated impurity spikes provide a conductive path through the pn-junction to impart forward and reverse diode characteristics to the pn-junction, thereby exhibiting the same advantageous effects as in the case of the first embodiment.

8 is a diagram showing the diode characteristics of the pn-junction of the source region of the SOI MOS transistor according to the second preferred embodiment of the present invention compared with that of the conventional SOI MOS transistor. The diode characteristics are measured in the same manner as in FIG. Further, in the drain voltage vs. drain current characteristic (not shown), the SOI MOS transistor according to the second embodiment reduces the drain current increase caused by the kink phenomenon by 20%, so that the overshoot in the pulse operation is 15%. It can be seen that% is reduced.

A third preferred embodiment of the present invention is described below (not shown). In the third embodiment, instead of injecting aluminum ions into the source region in the process of FIG. 4B, As ⁺ ions are dosed at least 10 times the dose to the drain region, that is, about 10 ¹⁷ cm ⁻² doses. Inject. Next, this doped substrate is heated in nitrogen gas, for example, at about 950 ° C. for 30 minutes. Excess dopants well above the normal impurity concentration do not form a normal pn-junction, i.e., a normal diode, but form a carrier-generating center in the pn-junction, causing a leak current in both the forward and reverse characteristics of the pn-junction diode. do. This leak current contributes to removing the potential difference between the potentials of the semiconductor substrate 31 'under the channel region 31 and the source region 6, and as a result, the same advantageous effects as in the first and second embodiments are obtained. .

A fourth preferred embodiment of the present invention is described below (not shown). Instead of the aluminum ion implantation in the first preferred embodiment of the present invention described above, oxygen or carbon ions are implanted into the source region. Oxygen or carbon atoms combine with silicon atoms in the source region to generate crystal bonds in that region. This generated crystal defect provides a carrier generation center to the pn-junction of the source region to provide a predetermined leakage path to the pn-junction. However, the effect is worse than that of the metal impurities of the first and second embodiments.

In the above-described first, second and fourth embodiments, the impurities additionally doping into the source region are aluminum, tungsten, or a single one such as carbon, but a plurality of these impurities, for example, aluminum + tungsten , Tungsten + carbon, tungsten + titanium, tungsten + oxygen, or the like may be doped into the source region. An advantage of multiple additional dopants is that the leakage current is effectively increased.

A fifth preferred embodiment of the present invention is described below (not shown).

Before the resist formation and before the aluminum ion implantation into the source region shown in FIG. 4B process in the first embodiment, that is, the region to be the source region and the drain region, Arsenic ions are equally implanted under the same conditions. Next, as in FIG. 4B, the drain region is masked, and argon ions are implanted only in the source region under conditions of 100 keV and 10 ¹⁶ cm ⁻² doses to make silicon in the source region amorphous. Argon ions do not react chemically with the implanted silicon. The amorphous silicon in the source region formed above causes crystal defects in the region, and thus a carrier generation center is formed in the pn-junction to provide an electrical leakage passage through the pn-junction diode, and the semiconductor substrate under the channel region 31 ( 31 ') and the source region 6 by removing the potential difference, the same advantageous effect as the above-described preferred embodiments is obtained.

9 is a cross sectional view of the manufacturing process of the sixth preferred embodiment of the present invention. An insulating layer ₂ made of SiO ₂ , a semiconductor substrate 3, and an element isolation region 4 on an SOI substrate composed of a support substrate 1 made of silicon as shown in FIG. 9A; The gate insulating film 51; Gate electrodes 5 and oxide films 53 and 54 made of polycrystalline silicon were formed in essentially the same manner as shown in Figs. 7A and 7B in the second preferred embodiment. Next, as shown in FIG. 9B, a 3,000 ns Si ₃ N ₄ coating film 9 is typically formed by a known CVD method or photolithography technique on a portion of the semiconductor substrate to be the source region. Next, as shown in FIG. 9C, arsenic ions (As ⁺ ) are implanted into the surface of the substrate prepared above under the condition of 100 keV and 5 × 10 ¹⁵ cm ⁻² . The ion implanted substrate is typically heated at 950 ° C. for 30 minutes to diffuse the implanted arsenic to form the source region 6 and the drain region 7.

Next, as shown in FIG. 9D, the PSG film 21 is applied as the insulating film on the entire surface of the surface; Drilling a contact hole to expose the source and drain regions; Aluminum is sputtered and patterned thereon to form source contacts 61 and drain contacts 71, which process is carried out by essentially the same method as in the first embodiment. The thermal expansion coefficients of the source region 6, drain region 7, coating film 9 and insulating film 21 are as follows:

As can be seen from the table, the difference between the thermal expansion coefficients of the source region 6 and the coating film 9 thereon is greater than the thermal expansion coefficient of the drain region 7 and the insulating film 21 applied thereon. Therefore, larger internal stress is generated in the source region 6 than in the drain region 7. This internal stress causes a piezoelectric resistance effect. This piezo-resistive effect is generally caused by the internal stress altering the inhibited bandwidth at the pn-junction, thus changing the ultimate carrier density, thus causing the leakage in both directions across the pn-junction, as the characteristics of the pn-junction diode change. It means the effect of increasing the current.

Fig. 10 shows the diode characteristics of the pn-junction of the source region of the SOI MOS transistor according to the sixth preferred embodiment of the present invention compared with that of the conventional SOI MOS transistor. Diode characteristics are measured in the same manner as in the case of FIG. Also, in the drain voltage vs. drain current characteristic (not shown), the SOI MOS transistor thermally stressed by the present invention reduces the drain current increase caused by the kink phenomenon by 15%, and thus the overshoot during pulse operation. It can be seen that a 10% decrease.

11 is a cross sectional view of a seventh preferred embodiment of the present invention. A device isolation region 4, a gate insulating film 51, and a gate electrode made of polycrystalline silicon on an SOI substrate composed of a support substrate 1 made of silicon, an insulating layer 2, and a semiconductor substrate 3 made of p-silicon. (5) is formed in essentially the same manner as in the first embodiment shown in FIG. 4A. After the resist is patterned on a portion other than the portion to be the next source region, boron ions are typically 50keV, 1 × 10 ¹⁵ cm ^-2 dough instead of aluminum ion implantation in FIG. 4B. Inject under conditions of Next, after removing the resist by essentially the same method as in the first embodiment, the n-type arsenic (As ⁺ ) n-type was formed on the front surface of the substrate under conditions of 100 keV and 5 x 10 ¹⁵ cm ^-2 doses. It is injected as a dopant.

The exposed surface of the polycrystalline silicon gate electrode 5 is oxidized by a known heat treatment method to form an insulating oxide film. By the heat treatment step, the boron and arsenic implanted in the above are diffused so that boron forms a more doped p ⁺ region 33 in the p-Si substrate 3, and the arsenic is the source region 62. And drain region 7 are formed. Therefore, the impurity concentration is typically 1.5 × 10 ²⁰ cm ⁻³ in the drain region 7 and the source region 6, and boron is 1 × 10 ¹⁸ or more, typically in the region 33 doped more than the above. While the concentration is 2 × 10 ¹⁹ cm ⁻³ , the impurity concentration of the p-Si substrate is 10 ¹⁶ cm ⁻³ . Thus, a tunnel diode is formed at the pn-junction. Further, by the same method as in the first preferred embodiment, the PSG insulating film 21, the source contact 61, the drain contact 71 and the gate electrode 55 are formed by a known technique. In the transistor thus manufactured, tunnel current through the pn-junction of the source region 62 is generated. This tunnel current reduces the potential difference between the source region 62 and the lower region 31 'of the channel region 31 in the semiconductor substrate 3, so that the beneficial effect of lowering the kink effect as in the case of the above-described preferred embodiments is obtained. Obtained. In implementing the seventh embodiment, the configuration of the tunnel diode is not limited to that described above as long as it is formed at the pn-junction of the source electrode.

In the above embodiments, aluminum and tungsten were used as the metal impurities causing the leak through the pn-junction, but in the first, second, fourth and fifth preferred embodiments, instead of aluminum or tungsten It is also possible to use molybdenum, platinum, titanium and tin and combinations thereof.

In the above embodiments, although p-type silicon is used as the semiconductor substrate 3, an SOI type insulated gate transistor fabricated on an n-type silicon substrate is of course included in the concept of the present invention. In this case, the dopant forming the source and drain regions would be boron. The metal impurity causing a leakage current in the pn-junction may be the same as that used in the case of the p-type substrate. As a variation of the seventh embodiment, the dopant forming more doped regions in the semiconductor substrate 3, in this case n-Si regions, is arsenic or phosphorus. The conditions for ion implantation and heat treatment can be the same.

In the above-described preferred embodiments, the silicon substrate and the silicon dioxide formed thereon are used as the insulating substrate of the SOI structure, but it is apparent that the insulating gate transistor formed on the other SOI substrate is also included in the concept of the present invention.

The features and advantages of the invention will be apparent from the above detailed description, and all such features and advantages that fall within the scope of the invention are included in the claims. In addition, since various modifications are possible, the above-mentioned content does not limit this invention, and these modifications are also included in the scope of the present invention.

Claims (17)

In an insulated gate field effect transistor formed on a semiconductor layer 3 having a first conductivity type on an insulating substrate 2, doped with a first impurity having a second conductivity type opposite to the first conductivity type. Drain region 7; The gate electrode 5 formed on the channel region 31 adjacent to the drain region 7 formed in the semiconductor layer 3 via the gate insulating layer 51 and the channel facing the drain region. Adjacent to the region 31, the first impurity includes a doped source region 6, and a first pn-junction formed between the source region 6 and the semiconductor layer 3 indicates a carrier generation center. And a conductive passage through the first ppn-junction, whereby the electrical resistance of the first ppn-junction is such that the electrical resistance of the second ppn-junction formed between the drain region 7 and the semiconductor layer 3. Insulated gate field effect transistor characterized by being smaller. The insulated gate field effect transistor according to claim 1, wherein the carrier generation center includes a metal impurity doped in the source region (6). The insulated gate field effect transistor according to claim 2, wherein the metal impurity is implanted into the first pn-junction by ion implantation. 3. The insulated gate field effect transistor according to claim 2, wherein the amount of the metal impurity implanted by the ion implantation method is larger than the solid solubility of the metal impurity. The insulating gate according to claim 2, wherein the metal impurity is diffused from the metal layer 8 stacked on the source region 6 to the first pn-junction through the source region 6 by heat treatment. Type field effect transistor. 3. The insulated gate field effect transistor according to claim 2, wherein said metal impurity precipitates across said first p-junction to form spikes (82). 3. The insulated gate field effect transistor according to claim 2, wherein the source region (6) further comprises at least one metal impurity as compared with the drain region (7). The insulated gate field effect transistor according to claim 2, wherein the metal impurities are selected from aluminum, molybdenum, platinum, tin, titanium, and tungsten. 2. The insulated gate electric field according to claim 1, wherein the concentration of the first impurity in the source region 6 is greater than the concentration in the drain region 7 to provide a carrier generation center for the first p-junction. Effect transistors. 10. The insulated gate field effect transistor according to claim 9, wherein said concentration of said first impurity in said source region (6) is at least 10 times the concentration in said drain region (7). 2. The insulated gate field effect transistor according to claim 1, wherein the source region (6) is formed of an amorphous semiconductor material as an essential component. In an insulated gate field effect transistor formed on a semiconductor layer 3 having a first conductivity type on an insulating substrate 2, doped with a first impurity having a second conductivity type opposite to the first conductivity type. Drain region 7; A gate electrode 5 formed on the channel region 31 adjacent to the drain region 7 formed in the semiconductor layer 3 via a gate insulating film 51 and the channel facing the drain region. And a source region 6 doped with the first impurity, adjacent to the region 31, wherein the source region 6 has a thermal stress greater than that of the drain region to impart a piezoelectric resistance effect. Thus, the electrical resistance of the first ppn-junction formed between the source region 6 and the semiconductor layer 3 is smaller than the electrical resistance of the second ppn-junction formed between the drain region 7 and the semiconductor layer 3. Insulated gate field effect transistor. 13. The method of claim 12, further comprising a layer (9) formed on said source region and not formed on said drain region, wherein said layer (9) has a thermal expansion coefficient different from that of said source region (6). Characterized insulated gate field effect transistor. In an insulated gate field effect transistor formed on a semiconductor layer 3 having a first conductivity type on an insulating substrate 2, doped with a first impurity having a second conductivity type opposite to the first conductivity type. Drain region 7; A gate electrode 5 formed on the channel region 31 adjacent to the drain region 7 formed on the semiconductor 3 layer via a gate insulating film, and the channel facing the drain region 7. A source diode 6 doped with the first impurity adjacent to the region and a tunnel diode 33 formed at a first pn-junction formed between the source region 6 and the semiconductor layer, wherein the tunnel diode 33 Thereby providing a conductive passage through the first ppn-junction, whereby the electrical resistance of the first ppn-junction is smaller than the electrical resistance of the second ppn-junction formed between the drain region 7 and the semiconductor layer 3. Insulated gate field effect transistor. 15. The semiconductor device according to claim 14, wherein the tunnel diode 33 comprises a portion further doped with a second impurity having the first conductivity type in the semiconductor layer 3 near the first pn-junction. Insulated gate field effect transistor. The insulated gate electric field according to any one of claims 1 to 12, characterized in that the insulating substrate (2) essentially comprises a silicon body (1) and a silicon dioxide layer (2) formed thereon. Effect transistors. The insulated gate field effect transistor according to any one of claims 1 to 12 or 14, characterized in that the semiconductor layer (3) is made of a silicon material.

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