JP2577345B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2577345B2 JP2577345B2 JP60207913A JP20791385A JP2577345B2 JP 2577345 B2 JP2577345 B2 JP 2577345B2 JP 60207913 A JP60207913 A JP 60207913A JP 20791385 A JP20791385 A JP 20791385A JP 2577345 B2 JP2577345 B2 JP 2577345B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- film
- semiconductor device
- junction
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 239000000758 substrate Substances 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に係り、特に高耐圧のプレーナ型
半導体装置に関する。Description: TECHNICAL FIELD [0001] The present invention relates to a semiconductor device, and more particularly, to a high breakdown voltage planar semiconductor device.
一般にプレーナ型の半導体装置は、逆バイアス印加時
に接合の湾曲部に電界集中が生じ、平面接合に比べて耐
圧が低くなることが知られている。このため高耐圧プレ
ーナ型半導体装置では、電界集中を緩和する種々の工夫
がなされている。In general, it is known that a planar type semiconductor device has an electric field concentration at a curved portion of a junction when a reverse bias is applied, and the breakdown voltage is lower than that of a planar junction. For this reason, various devices have been devised in the high breakdown voltage planar type semiconductor device to reduce the electric field concentration.
第４図はその様な従来のプレーナ型半導体装置の構造
例である。n-型半導体基板31に選択的にｐ型拡散層32が
形成され、このｐ型拡散層32と基板31の間に逆バイアス
が印加されるようになっている。拡散層32と基板31のな
す接合の基板表面に露出する部分およびその外側に絶縁
膜34が形成され、この絶縁膜34上に所定幅の高抵抗体膜
からなる、所謂フィールド・プレート35が形成されてい
る。フィールド・プレート35の一端は拡散層32の金属電
極36により拡散層32と同電位に設定され、他端は基板31
に形成されたn+型拡散層に設けられた金属電極37により
基板31の電位に設定されている。FIG. 4 shows an example of the structure of such a conventional planar type semiconductor device. A p-type diffusion layer 32 is selectively formed on an n - type semiconductor substrate 31, and a reverse bias is applied between the p-type diffusion layer 32 and the substrate 31. An insulating film 34 is formed on a portion of the junction between the diffusion layer 32 and the substrate 31 exposed on the surface of the substrate and outside thereof, and a so-called field plate 35 made of a high-resistance film having a predetermined width is formed on the insulating film 34. Have been. One end of the field plate 35 is set to the same potential as the diffusion layer 32 by the metal electrode 36 of the diffusion layer 32, and the other end is set to the substrate 31.
The potential of the substrate 31 is set by a metal electrode 37 provided in the n + -type diffusion layer formed in the above.
この様な構造では、pn接合に逆バイアスを印加した
時、高抵抗のフィールド・プレート35に微少電流が流れ
てその内部に電位勾配が形成される。この結果、基板31
に伸びる空乏層は第５図に破線で示すようになり、基板
表面部での電界強度が緩和される。これにより、平坦接
合の耐圧の約70％の耐圧が得られる。In such a structure, when a reverse bias is applied to the pn junction, a minute current flows through the high-resistance field plate 35, and a potential gradient is formed therein. As a result, the substrate 31
The depletion layer extending as shown by the broken line in FIG. 5 reduces the electric field intensity at the substrate surface. Thereby, a withstand voltage of about 70% of the withstand voltage of the flat junction is obtained.
しかしながらこの構造の場合、第５図に示すようにpn
接合に沿って基板内部に伸びる空乏層先端に湾曲部39が
形成され、この湾曲部39に大きい電界の集中が見られ
る。このため前述のように、耐圧は平坦接合のそれの70
％までが限界となっている。However, in the case of this structure, as shown in FIG.
A curved portion 39 is formed at the tip of a depletion layer extending into the substrate along the junction, and a large electric field concentration is observed in the curved portion 39. For this reason, as described above, the breakdown voltage is 70 times that of the flat junction.
% Is the limit.
本発明は上記した点に鑑みなされたもので、従来に比
べてより高い耐圧を実現したプレーナ型の半導体装置を
提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to provide a planar-type semiconductor device having a higher withstand voltage as compared with the related art.
本発明は、前述した抵抗性フィールド・プレートのう
ち、pn接合端から20〜80μｍの範囲を実質的に低抵抗導
電体膜により構成したことを特徴とする。The present invention is characterized in that, of the above-described resistive field plate, a range of 20 to 80 μm from the pn junction end is substantially formed of a low-resistance conductive film.
本発明によれば、pn接合端から所定距離の間フィール
ド・プレートによる電位勾配が形成されないようにして
拡散層と同電位を保ち、その外側に電位勾配を形成する
ことによって、拡散層からの空乏層の伸びをなだらかな
ものとして電界の集中を防止することができ、プレーナ
型半導体装置の高耐圧化を図ることができる。低抵抗導
電体膜とする範囲を20〜80μｍに限定するのは、半導体
基板が20Ω・cm以上の場合にこの範囲に設定することに
より効果的に耐圧向上が図られるからである。According to the present invention, depletion from the diffusion layer is maintained by maintaining the same potential as the diffusion layer and preventing the potential gradient by the field plate from being formed for a predetermined distance from the pn junction end and forming the potential gradient outside the diffusion layer. The concentration of the electric field can be prevented by making the growth of the layer gentle, and the breakdown voltage of the planar semiconductor device can be increased. The reason why the range of the low-resistance conductive film is limited to 20 to 80 μm is that when the semiconductor substrate has a thickness of 20 Ω · cm or more, the breakdown voltage can be effectively improved by setting the range to this range.
以下本発明の実施例を説明する。 Hereinafter, embodiments of the present invention will be described.
第１図は一実施例の縦型MOSFETである。これを製造工
程に従って説明すると、比抵抗50Ω・cm程度のn-型Si基
板11（第１半導体層）を用意し、その表面を酸化してゲ
ート酸化膜14を形成し、この上に5000Å程度の多結晶シ
リコン膜によりゲート電極15を形成する。そしてゲート
電極15をマスクとしてボロンを５μｍ程度拡散してp+型
ベース層12（第２半導体層）を形成する。次いでゲート
電極15による窓のなかにソース層および基板領域のコン
タクト層形成のための開口を持つ酸化膜を形成し、Asの
イオン注入と熱処理を行なってn+型のソース層13および
コンタクト層19を形成する。この後CVD酸化膜16を形成
し、これをベース層12の接合端部からフィールド領域を
覆うようにパターニングする。そして、高抵抗体膜21と
して半絶縁性多結晶シリコン膜（SIPOS）をCVD酸化膜の
絶縁膜16上にパターン形成し、その上にCVD酸化膜等の
絶縁膜23を形成して高抵抗体膜21の端部が露出するよう
にパターニングする。この後、高抵抗体膜21の端部に一
部重なるようにAl膜の蒸着、パターニングを行なって、
ソース層13とベース層12に同時にコンタクトするソース
電極17、18およびコンタクト層19を介して基板にコンタ
クトする電極20を形成する。ここでソース電極18が高抵
抗体膜21と重なる範囲を、p+ベース層12の接合端部から
所定距離Ｌ（＝20〜80μｍ）の範囲とする。最後に基板
表面にＶ−Ni−Au膜の蒸着によりドレイン電極22を形成
する。FIG. 1 shows a vertical MOSFET according to one embodiment. This will be described in accordance with the manufacturing process. An n - type Si substrate 11 (first semiconductor layer) having a specific resistance of about 50 Ω · cm is prepared, and its surface is oxidized to form a gate oxide film 14. The gate electrode 15 is formed from the polycrystalline silicon film. Then, using the gate electrode 15 as a mask, boron is diffused by about 5 μm to form the p + -type base layer 12 (second semiconductor layer). Next, an oxide film having an opening for forming a source layer and a contact layer in a substrate region is formed in a window formed by the gate electrode 15, and ion implantation of As and heat treatment are performed to perform an n + -type source layer 13 and a contact layer 19. To form Thereafter, a CVD oxide film 16 is formed and is patterned so as to cover the field region from the junction end of the base layer 12. Then, a semi-insulating polycrystalline silicon film (SIPOS) is patterned as a high-resistance film 21 on the insulating film 16 of a CVD oxide film, and an insulating film 23 such as a CVD oxide film is formed thereon. Patterning is performed so that the end of the film 21 is exposed. Thereafter, the Al film is deposited and patterned so as to partially overlap the end of the high-resistance body film 21,
Source electrodes 17, 18 that simultaneously contact the source layer 13 and the base layer 12, and an electrode 20 that contacts the substrate via the contact layer 19 are formed. Here, the range in which the source electrode 18 overlaps the high resistance film 21 is a range of a predetermined distance L (= 20 to 80 μm) from the junction end of the p + base layer 12. Finally, a drain electrode 22 is formed on the substrate surface by vapor deposition of a V-Ni-Au film.
この実施例の場合、p+型ベース層12と基板11間に逆バ
イアスを印加した時の基板11に伸びる空乏層は、従来の
ような曲率半径の小さい湾曲部が形成されない。これ
は、ソース電極18がフィールド領域まで距離Ｌだけ高抵
抗体膜21と重なることによりこの部分が高抵抗体膜21と
共にフィールド・プレートの一部を構成しており、しか
もこの部分は低抵抗であってこの範囲内では電位勾配が
ないためである。従ってこの実施例によれば、空乏層の
伸びがなだらかになり、耐圧の大幅な向上が図られる。In the case of this embodiment, the depletion layer extending to the substrate 11 when a reverse bias is applied between the p + -type base layer 12 and the substrate 11 does not have a curved portion having a small radius of curvature unlike the related art. This is because the source electrode 18 overlaps the high-resistance film 21 by a distance L to the field region, and this portion constitutes a part of the field plate together with the high-resistance film 21, and this portion has a low resistance. This is because there is no potential gradient within this range. Therefore, according to this embodiment, the elongation of the depletion layer becomes gentle, and the withstand voltage is greatly improved.
第３図は上記実施例の構造でソース電極18をフィール
ド領域上に延在させる距離Ｌを変化させた時のp+型ベー
ス層12と基板11間の降伏電圧VBを測定した結果である。
距離50μｍで降伏電圧は最大値を示している。基板11の
比抵抗が20Ω・cm以上の場合、Ｌ＝20〜80μｍの範囲に
設定すれば、従来の構造に比べて耐圧は20％以上向上
し、平坦接合の耐圧の90％以上の耐圧が実現できる。Figure 3 is a result of measuring the breakdown voltage V B between the p + -type base layer 12 and the substrate 11 at the time of changing the distance L of extending the source electrode 18 on the field region in the structure of the above embodiment .
At a distance of 50 μm, the breakdown voltage shows a maximum value. When the specific resistance of the substrate 11 is 20 Ω · cm or more, if L is set in the range of 20 to 80 μm, the withstand voltage is improved by 20% or more compared with the conventional structure, and the withstand voltage of 90% or more of the flat junction withstand voltage is improved. realizable.
第２図は、他の実施例の縦型MOSFETである。この実施
例でも先の実施例と対応する部分には先の実施例と同一
符号を付してある。第１図の実施例と異なる点は、絶縁
膜16を形成した後、この上にp+型ベース層12と基板11の
接合部を覆うように例えば不純物をドープした多結晶シ
リコン膜等の低抵抗導電体膜24を形成し、更にこの上に
低抵抗導電体膜24が露出するように絶縁膜25を形成し、
この後、Al膜による電極17、18、20を形成し、アモルフ
ァスSi膜等の高抵抗体膜21を形成している点である。FIG. 2 shows a vertical MOSFET according to another embodiment. Also in this embodiment, parts corresponding to those in the previous embodiment are denoted by the same reference numerals as those in the previous embodiment. The difference from the embodiment of FIG. 1 is that after the insulating film 16 is formed, a low-level material such as a polycrystalline silicon film doped with impurities is formed thereon so as to cover the junction between the p + -type base layer 12 and the substrate 11. Forming a resistive conductor film 24, further forming an insulating film 25 thereon such that the low-resistance conductor film 24 is exposed,
Thereafter, electrodes 17, 18, and 20 of an Al film are formed, and a high-resistance film 21 such as an amorphous Si film is formed.
この実施例の場合も、図に示す距離Ｌを20〜80μｍに
設定することにより、フィールド・プレートの接合端部
近傍を実質的に低抵抗とすることができ、先の実施例と
同様に耐圧向上が図られる。特に低抵抗導電体膜24を組
合わせることにより、接合端部近傍の基板内電界分布、
即ち空乏量の伸びの形状を最適設計することができ、よ
り高い耐圧を実現することができる。Also in the case of this embodiment, by setting the distance L shown in the figure to 20 to 80 μm, the vicinity of the joint end of the field plate can be made substantially low in resistance, and the breakdown voltage can be reduced similarly to the previous embodiment. Improvement is achieved. In particular, by combining the low resistance conductive film 24, the electric field distribution in the substrate near the junction end,
That is, the shape of the elongation of the depletion amount can be optimally designed, and a higher breakdown voltage can be realized.
本発明は上記実施例に限られるものではない。例えば
上記実施例ではフィールド・プレートの接合端部近傍を
実質的に低抵抗導電体膜とするために金属電極を延在さ
せ、、あるいは低抵抗多結晶シリコン膜を介在させてい
るが、フィールド・プレート全体を高抵抗のアモルファ
スSi膜あるいは多結晶シリコン膜により構成してその接
合端部近傍に選択的に不純物をドープして低抵抗とする
ことも可能である。また実施例ではフィールド・プレー
トの一端を基板電位に設定するためにコンタクト層19お
よびこれを介して基板11にコンタクトする電極20を設け
ているが、ある程度以下のコンタクト抵抗をもってフィ
ールド・プレート膜自体を基板にコンタクトさせること
ができれば、これらのコンタクト層19や電極20を省略す
ることができる。更に本発明は縦型MOSFETに限らず、導
電変調型MOSFET等、他の高耐圧用プレーナ型半導体装置
に同様に適用することができる。The present invention is not limited to the above embodiment. For example, in the above embodiment, the metal electrode is extended or the low-resistance polycrystalline silicon film is interposed in order to make the vicinity of the junction end of the field plate substantially a low-resistance conductive film. The entire plate may be made of a high-resistance amorphous Si film or a polycrystalline silicon film, and the vicinity of the junction may be selectively doped with impurities to reduce the resistance. In the embodiment, the contact layer 19 and the electrode 20 for contacting the substrate 11 via the contact layer 19 are provided to set one end of the field plate to the substrate potential. If contact can be made with the substrate, these contact layers 19 and electrodes 20 can be omitted. Further, the present invention is not limited to the vertical MOSFET, but can be similarly applied to other high breakdown voltage planar semiconductor devices such as a conduction modulation MOSFET.
第１図は本発明の一実施例の縦型MOSFETを示す図、第２
図は他の実施例の縦型MOSFETを示す図、第３図は本発明
での数値限定の根拠となるデータを示す図、第４図は従
来の縦型MOSFETを示す図である。 11……n-型Si基板（第１半導体層）、12……p+型ベース
層（第２半導体層）、13……n+型ソース層、14……ゲー
ト酸化膜、15……ゲート電極、16,23,25……絶縁膜、1
7,18……ソース電極、19……n+型コンタクト層、20……
コンタクト電極、21……高抵抗体膜（アモルファスSi
膜，半絶縁性多結晶シリコン膜）。FIG. 1 is a diagram showing a vertical MOSFET according to an embodiment of the present invention.
FIG. 3 is a diagram showing a vertical MOSFET of another embodiment, FIG. 3 is a diagram showing data serving as a basis for limiting numerical values in the present invention, and FIG. 4 is a diagram showing a conventional vertical MOSFET. 11 ...... n - -type Si substrate (first semiconductor layer), 12 ...... p + -type base layer (second semiconductor layer), 13 ...... n + -type source layer, 14 ...... gate oxide film, 15 ...... gate Electrode, 16,23,25 …… Insulating film, 1
7,18 …… Source electrode, 19 …… n + type contact layer, 20 ……
Contact electrode, 21 ... High-resistance film (amorphous Si
Film, semi-insulating polycrystalline silicon film).
Claims (3)
第２導電型の第２半導体層が形成され、これら第１半導
体層と第２半導体層のなす接合の基板表面に露出する部
分およびその外側が絶縁膜により覆われ、この絶縁膜上
に一端が前記第２半導体層の電位に設定され他端が前記
第１半導体層の電位に設定された抵抗性のフィールド・
プレートが設けられた半導体装置において、 前記第１半導体層の比抵抗が20Ω・cm以上であり、前記
フィールド・プレートが前記絶縁膜上の前記接合の基板
表面に露出する部分の外側に形成されて、前記第２半導
体層の電極金属が前記接合の基板表面に露出する部分か
ら20〜80μｍの範囲で前記フィールド・プレートと一部
重なるように形成されていることを特徴とする半導体装
置。A second semiconductor layer of a second conductivity type is selectively formed on a surface of a first semiconductor layer of a first conductivity type, and is exposed on a substrate surface of a junction formed between the first semiconductor layer and the second semiconductor layer. And the outside thereof are covered with an insulating film. On the insulating film, one end is set to the potential of the second semiconductor layer and the other end is set to a potential of the first semiconductor layer.
In a semiconductor device provided with a plate, the first semiconductor layer has a specific resistance of 20 Ω · cm or more, and the field plate is formed outside a portion of the insulating film exposed on the substrate surface of the junction. A semiconductor device, wherein the electrode metal of the second semiconductor layer is formed so as to partially overlap the field plate within a range of 20 to 80 μm from a portion exposed on the substrate surface of the junction.
分が半絶縁性多結晶シリコンである特許請求の範囲第１
項記載の半導体装置。2. The semiconductor device according to claim 1, wherein a main component of said resistive field plate is semi-insulating polycrystalline silicon.
13. The semiconductor device according to claim 1.
分がアモルファスSiであり、前記絶縁膜上に低抵抗多結
晶シリコン膜が形成されかつこの低抵抗多結晶シリコン
膜が前記第２半導体層の電極金属と一部重なっている特
許請求の範囲第１項記載の半導体装置。3. The resistive field plate is mainly composed of amorphous Si, a low-resistance polycrystalline silicon film is formed on the insulating film, and the low-resistance polycrystalline silicon film is formed on the second semiconductor layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device partially overlaps the electrode metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60207913A JP2577345B2 (en) | 1985-09-20 | 1985-09-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60207913A JP2577345B2 (en) | 1985-09-20 | 1985-09-20 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6316087A Division JP2712098B2 (en) | 1994-11-28 | 1994-11-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6267871A JPS6267871A (en) | 1987-03-27 |
| JP2577345B2 true JP2577345B2 (en) | 1997-01-29 |
Family
ID=16547637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60207913A Expired - Lifetime JP2577345B2 (en) | 1985-09-20 | 1985-09-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2577345B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0783123B2 (en) * | 1988-12-08 | 1995-09-06 | 富士電機株式会社 | MOS semiconductor device |
| DE4137341C1 (en) * | 1991-11-13 | 1993-04-29 | Siemens Ag, 8000 Muenchen, De | |
| JP2712098B2 (en) * | 1994-11-28 | 1998-02-10 | 株式会社東芝 | Semiconductor device |
| US5859465A (en) * | 1996-10-15 | 1999-01-12 | International Rectifier Corporation | High voltage power schottky with aluminum barrier metal spaced from first diffused ring |
| JP3591301B2 (en) * | 1998-05-07 | 2004-11-17 | 富士電機デバイステクノロジー株式会社 | Semiconductor device |
| CN106256024B (en) | 2014-04-30 | 2019-11-26 | 三菱电机株式会社 | Manufacturing silicon carbide semiconductor device |
| JP2017050451A (en) * | 2015-09-03 | 2017-03-09 | サンケン電気株式会社 | Semiconductor device |
| JP6790908B2 (en) * | 2017-02-23 | 2020-11-25 | 株式会社デンソー | Semiconductor device |
| JP7241574B2 (en) * | 2019-03-11 | 2023-03-17 | 株式会社東芝 | semiconductor equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5853860A (en) * | 1981-09-26 | 1983-03-30 | Toshiba Corp | High breakdown voltage planar type semiconductor device |
-
1985
- 1985-09-20 JP JP60207913A patent/JP2577345B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6267871A (en) | 1987-03-27 |
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