JPS6373564A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6373564A
JPS6373564A JP61217509A JP21750986A JPS6373564A JP S6373564 A JPS6373564 A JP S6373564A JP 61217509 A JP61217509 A JP 61217509A JP 21750986 A JP21750986 A JP 21750986A JP S6373564 A JPS6373564 A JP S6373564A
Authority
JP
Japan
Prior art keywords
electrode
gate electrode
oxide film
film
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61217509A
Other languages
Japanese (ja)
Inventor
Yoshihiro Yamaguchi
好広 山口
Akio Nakagawa
明夫 中川
Kiminori Watanabe
渡辺　君則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61217509A priority Critical patent/JPS6373564A/en
Publication of JPS6373564A publication Critical patent/JPS6373564A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To improve reliability by disposing a resistive field plate film so as to simultaneously cover a second main electrode and a control electrode. CONSTITUTION:An oxide film 24 is formed onto the surface of an n<-> type drain layer 12 shaped onto an n<+> type drain layer 11 through epitaxial growth, the oxide film 24 is etched to a predetermined pattern, and a gate electrode 16 is formed through a gate oxide film 15. p-type base layers 13 are formed, using the gate electrode 16 and the oxide film 24 as masks. An oxide film is shaped into a diffusion window by the gate electrode 16, and an n<+> type layer 25 as well as n<+> type sources 14 are formed, employing the oxide film and the gate electrode 16 as masks. The surface of the gate electrode 16 is coated with an oxide film 17, a hole is bored to a contact section in the gate electrode 16, and a source electrode 18 and a metallic gate electrode 19 are shaped. An a-Si film is deposited on the whole surface of an element, and a resistive field plate film 27 is formed. A drain electrode 20 is shaped onto the surface of a wafer. Accordingly, the element having high reliability can be acquired through a simple process.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は半導体装置に係り、特に高耐圧ブレーナ型半導
体装置の表面保護構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a surface protection structure for a high-voltage Brainer type semiconductor device.

（従来の技術） 従来より、ブレーナ型半導体装置の耐圧を出す構造の一
つとして、ガードリング構造が良く知られている。この
ガードリング構造を採用したＭＯＳ　Ｆ　Ｅ　Ｔの例を
第２図に示す。素子基板１゜は、ｎ＋型トド９４２層１
１ｎ−型ドレイン層１２、ｐ型ベース層１３およびｎ型
ソース層１４から構成されている。この素子基板１０の
ドレイン層１１側の第１の表面には第１の主電極である
ドレイン電極２０が形成されている。また第２の表面に
は、ゲート絶縁膜１５を介してゲート′Ｉ４極１６が形
成され、ｐ型ベース［１１３とｎ型ソース層１４にオー
ミック接触する第２の主電極１８、およびゲート電極１
６にオーミック接触する＄制御電極である金屑ゲート電
極１９が設けられている。(Prior Art) A guard ring structure has been well known as one of the structures for increasing the withstand voltage of a Brehner type semiconductor device. An example of a MOS FET employing this guard ring structure is shown in FIG. The element substrate 1° is an n+ type Todo 942 layer 1
It is composed of an n-type drain layer 12, a p-type base layer 13, and an n-type source layer 14. A drain electrode 20, which is a first main electrode, is formed on the first surface of the element substrate 10 on the drain layer 11 side. Further, on the second surface, a gate 'I4 pole 16 is formed via a gate insulating film 15, a second main electrode 18 in ohmic contact with the p-type base [113 and the n-type source layer 14], and a gate electrode 1
A metal scrap gate electrode 19, which is a $ control electrode, is provided in ohmic contact with the gate electrode 6.

素子基板１０の周縁部には、数本のｐ＋＋ガードリング
層２１が形成され、その表面には巖化膜２２が形成され
ている。Several p++ guard ring layers 21 are formed on the periphery of the element substrate 10, and a dilatation film 22 is formed on the surface thereof.

この構造では、逆バイアスをｐｎ接合に印加した時に主
接合が降伏しないように第１段のガードリングで一定の
電圧を負担し、次に第１段のガードリングが降伏しない
ように第２のガードリングが一定の電圧を負担する、と
いうように、最終段のガートリングには十分低い電圧が
かかるようにしている。即ちガードリング構造では、ガ
ードリング間の電位差が十分小さくなるようにして、例
えばＲ終段ガードリングは３００Ｖ程度の電圧を負担す
るように設計される。In this structure, when a reverse bias is applied to the pn junction, the first stage guard ring bears a constant voltage to prevent the main junction from breaking down, and then the second stage guard ring bears a certain voltage to prevent the first stage guard ring from breaking down. The guard ring bears a certain voltage, so that a sufficiently low voltage is applied to the final stage guard ring. That is, the guard ring structure is designed so that the potential difference between the guard rings is sufficiently small, so that, for example, the R final stage guard ring bears a voltage of about 300V.

従ってこのガードリング構造では、十分な耐圧を得るた
めにはガードリングの数を多くしなければならず、高耐
圧素子は巨大化するという第１の問題があった。Therefore, in this guard ring structure, the first problem is that the number of guard rings must be increased in order to obtain a sufficient breakdown voltage, and the high breakdown voltage element becomes large.

またこの様な素子では、これをパッケージに収納する前
に基本的特性を検査しており、その際にＡｆｌ等により
形成されたソース電極１８および金属ゲート電極１９に
タングステンなどの針を接触させることが行われる。こ
のタングステン針をソース′Ｒ極１８．金属ゲートｉ！
１ｉ１９に接触させる時、誤って素子表面を滑らせると
、ソース電極あるいはゲート電橋１９のＡλが押出され
てソース・ゲート間が短絡する事故が発生する。ソース
電極１８と金属ゲート電極１９は通常分離幅数１０μｍ
で近接しているため、この様な事故が容易に発生する。In addition, the basic characteristics of such devices are inspected before they are packaged, and at that time, a needle made of tungsten or the like is brought into contact with the source electrode 18 and metal gate electrode 19 formed of Afl or the like. will be held. Connect this tungsten needle to the source 'R pole 18. Metal gate i!
If the device surface is mistakenly slid when contacting the device 1i19, the source electrode or Aλ of the gate bridge 19 may be pushed out, causing a short circuit between the source and the gate. The source electrode 18 and metal gate electrode 19 are usually separated by a width of several tens of μm.
Due to their close proximity, accidents like this can easily occur.

またこの程度の分離幅の場合、この分離領域に微少な金
ｚ片等が付着することによっても、ソース・ゲート間が
短絡する。これが第２の問題である。In addition, in the case of an isolation width of this extent, a short circuit between the source and the gate may also occur if a minute piece of gold Z or the like adheres to this isolation region. This is the second problem.

第１の問題を解決する構造として、第３図に示すものが
知られている。なお第３図は第２図（ｂ）に対応する断
面図で、第２図と対応する部分には第２図と同一符号を
付しである。この素子では、素子外周部にｎ＋型Ｊｉ２
５を形成し、これにオーミック接触するへ２電極２６を
形成している。また素子表面に露出するｐｎ接合を覆う
壊化１Ｉ２４を形成し、この酸化１１２４上にＡ２電極
２６とソース電極１８に同時にコンタクトする抵抗性フ
ィールドプレートＩ［！２７を形成している。A structure shown in FIG. 3 is known as a structure that solves the first problem. Note that FIG. 3 is a cross-sectional view corresponding to FIG. 2(b), and parts corresponding to those in FIG. 2 are given the same reference numerals as in FIG. 2. In this device, n+ type Ji2 is located on the outer periphery of the device.
5 is formed, and two electrodes 26 are formed to make ohmic contact therewith. In addition, a oxidized oxide 1124 is formed to cover the pn junction exposed on the element surface, and a resistive field plate I[! 27 is formed.

この構造では、ｐｎ接合に逆バイアスしたとき、抵抗性
フィールドプレート膜２７に微少電流が流れ、ここに一
定の電位勾配が形成されるため、基板表面のｐｎ接合で
の電界強度が弱められる。これにより、高耐圧化が図ら
れる。具体的に例えば、ｎ−型ドレイン層１２の比抵抗
を１００〜１２０Ω・αとし、ｎ＋型１１２５とｐベー
ス！１１３の間隔を５００μｍ程度とした時、耐圧１８
００■以上を得ることができる。この耐圧を前述のガー
ドリング構造で実現するにはガードリングの領域を約１
１Ｍ１以上にする必要があり、このフィールドプレート
構造により素子サイズを大きくすることなく高耐圧化が
できることが判る。In this structure, when a reverse bias is applied to the pn junction, a minute current flows through the resistive field plate film 27 and a certain potential gradient is formed there, so that the electric field strength at the pn junction on the substrate surface is weakened. This achieves high voltage resistance. Specifically, for example, the specific resistance of the n-type drain layer 12 is set to 100 to 120Ω·α, and the n+ type is 1125 and the p base! When the interval of 113 is about 500 μm, the breakdown voltage is 18
00■ or more can be obtained. To achieve this voltage resistance with the guard ring structure described above, the area of the guard ring should be approximately 1
It is necessary to make it 1M1 or more, and it can be seen that with this field plate structure, a high breakdown voltage can be achieved without increasing the element size.

一方、先の第２の問題に対しては、第２図に示すように
ソース電極１８と金属ゲート電極１９を覆うＣＶＤ絶縁
！１１２３を設けることが行われる。On the other hand, for the second problem mentioned above, as shown in FIG. 2, CVD insulation covering the source electrode 18 and metal gate electrode 19! 1123 is provided.

しかしこれは、ＣＶＤ工程が入る分、素子のコストが高
くなるという新たな問題を生じる。However, this creates a new problem in that the cost of the device increases due to the CVD process involved.

（発明が解決しようとする問題点） 以上のように従来技術では、第２の主電極と制御電極間
のｒｉ絽の問題をＣＶＤ絶縁膜で覆うことが解決したが
、これはコスト高の原因となっている。(Problems to be Solved by the Invention) As described above, in the conventional technology, the problem of ri-ga between the second main electrode and the control electrode was solved by covering it with a CVD insulating film, but this was a cause of high cost. It becomes.

本発明はこの様な問題を解決した高耐圧ブレーナ型半導
体装置を提供することを目的とする。An object of the present invention is to provide a high breakdown voltage Brainer type semiconductor device that solves these problems.

［発明の構成コ （問題点を解決するための手段） 本発明は、半導体素子基板の第１の表面に第１の電極が
形成され、第２の表面に第２の主電極と制ｍ’ｉａ極が
形成され、かつ第２の表面の周縁部に露出するｐｎ接合
上に絶縁膜を介して抵抗性フィールドプレート膜を設け
る構造において、この抵抗性フィールドプレート膜を第
２の主Ｎ也と♂すｗＪＮ極を同時に覆うように配設する
ことを特徴とする。[Structure of the Invention (Means for Solving the Problems)] The present invention provides a first electrode formed on the first surface of a semiconductor element substrate, a second main electrode formed on the second surface, and a second main electrode formed on the second surface. In a structure in which an ia pole is formed and a resistive field plate film is provided via an insulating film on the pn junction exposed at the peripheral edge of the second surface, this resistive field plate film is used as the second main Nya. It is characterized by being arranged so as to simultaneously cover the male and female wJN poles.

（作用） 本発明の構成とすれば、抵抗性フィールドプレート膜は
素子寸法を大きくすることなく高耐圧化する機能を有す
ると同時に、素子特性検査時等に制御電極と第２の主電
極間の短Ｆ？！事故を防止する保１１！ｌの動きをする
。(Function) With the configuration of the present invention, the resistive field plate film has the function of increasing the withstand voltage without increasing the device size, and at the same time, the resistive field plate film has the function of increasing the withstand voltage without increasing the device size. Short F? ! 11 tips to prevent accidents! Make the l movement.

（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.

第１図は一実施例のＭ　ＯＳ　Ｆ　Ｅ　Ｔであり、（ａ
）は平面図、（ｂ）、（ｃ）はそれぞれ（ａ）のＡ−Ａ
＝、Ｂ−Ｂ′断面図である。従来例として示した第２図
および第３図と対応する部分にはこれらと同じ符号を付
して詳細な説明は省略する。FIG. 1 shows an embodiment of the MOS FET, (a
) is a plan view, (b) and (c) are respectively A-A of (a)
=, BB' sectional view. Portions corresponding to those in FIGS. 2 and 3 shown as conventional examples are designated by the same reference numerals, and detailed description thereof will be omitted.

第１図（ｂ）と対応する第３図を比較して明らかなよう
に、この実施例では抵抗性フィールドプレートｒ１２７
はソース電極１８と金属ゲート電極１９を同時に覆うよ
う配設している。As is clear from a comparison of FIG. 1(b) and the corresponding FIG. 3, in this embodiment the resistive field plate r127
are arranged so as to simultaneously cover the source electrode 18 and the metal gate electrode 19.

この実施例の構造を、具体的な製造工程にしたがって次
に説明する。まずｎ＋型トド９４２層１１エピタキシャ
ル成長により比抵抗１００〜１２０Ω・αのｎ−型ドレ
イン層１２を形成したウェーハを用意する。次にｎ°型
トドレイン１１２表面に１μｍ程度の酸化膜２４を形成
した後、これを所定パターンにエツチングし、霧出した
基板に１０００人のゲート数化［１１５を介して多結晶
シリコン躾によるゲート電極１６を形成する。The structure of this embodiment will now be explained according to specific manufacturing steps. First, a wafer is prepared in which an n- type drain layer 12 having a specific resistance of 100 to 120 Ω·α is formed by epitaxial growth of an n + type Todo 942 layer 11. Next, after forming an oxide film 24 of about 1 μm on the surface of the n° type drain 112, this is etched into a predetermined pattern, and the number of gates is 1000 on the sprayed substrate. Electrodes 16 are formed.

次いでこのゲート電極１６と酸化ｌ１Ｉ２４をマスクと
して不純物をイオン注入してｐ型ベース層１３を形成す
る。更にゲートｉｆ極１６による拡散窓内にソース層形
成用の酸化ＷＡ（図示しない）を形成し、この酸化膜と
ゲート電極１６をマスクとしてＡｓのイオン注入を行な
い、ｎ＋＋ソース層１４と同時にｎ＋＋層２５を形成す
る。この後ゲート１！１１６表面を酸化［６１１７で覆
い、ゲート電極１６のコンタクト部に孔を開けて、ｐ型
ベース層１３とｎ＋＋ソース層１４にオーミック接触す
るソース電極（第２の主電極）１８、およびゲート電極
１６にオーミック接触する金属ゲート電極（制御！ｌ電
極）１９をＡｎ膜等により形成する。そして、素子全面
にａ−８ｉｌｌを１μｍ程度堆積し、抵抗性フィールド
プレートｌＩ２７を形成する。ここでフィールドプレー
ト１１２７は、ソース電極１８と金属ゲート電極１９を
同時に覆っている。Next, impurity ions are implanted using the gate electrode 16 and the oxide l1I24 as masks to form the p-type base layer 13. Further, an oxidized WA (not shown) for forming a source layer is formed within the diffusion window formed by the gate if electrode 16, and As ions are implanted using this oxide film and the gate electrode 16 as a mask. Form 25. After that, the surface of the gate 1!116 is covered with oxidation [6117], a hole is made in the contact part of the gate electrode 16, and a source electrode (second main electrode) 18 is made in ohmic contact with the p-type base layer 13 and the n++ source layer 14. , and a metal gate electrode (control!l electrode) 19 in ohmic contact with the gate electrode 16 is formed of an An film or the like. Then, a-8ill is deposited to a thickness of about 1 μm over the entire surface of the device to form a resistive field plate II27. Here, the field plate 1127 covers the source electrode 18 and the metal gate electrode 19 at the same time.

またフィールドプレート膜２７には、ソース電極１８お
よび金属ゲート１ｆｆｉ１９上の一部に外部配線を施す
ための開口が設けられる。最後にウェーハ裏面にＶ−Ｎ
ｉ−Ａｕの蒸着によりドレイン電極（第１０主電１）２
０を形成して、素子は完成する。Further, the field plate film 27 is provided with an opening for providing external wiring in a portion above the source electrode 18 and the metal gate 1ffi19. Finally, V-N on the back side of the wafer.
Drain electrode (10th main electrode 1) 2 by vapor deposition of i-Au
0 is formed, and the device is completed.

この様な構成とすれば、ソース電極１８と金属ゲート電
極１９が同時にフィールドブレーｌ−膜２７に覆われて
いるため、フィールドプレート膜２７が保ｙｔ膜となっ
てソース電極１８と金属ゲートｌ！ｔｆＡ１９の短絡事
故は確実に防止される。またフィールドプレートＩＩ！
＄２７が同時に素子の表面保護膜となっているから、従
来のようにフィールドプレート膜と別にＣｖＤによる保
Ｋ１１ｇを形成するという工程が要らず、製造工程が簡
略化される。With this configuration, the source electrode 18 and the metal gate electrode 19 are simultaneously covered with the field barrier l- film 27, so the field plate film 27 acts as a protective film to protect the source electrode 18 and the metal gate l! Short circuit accidents of tfA19 are reliably prevented. Field plate II again!
Since the film 27 also serves as a surface protection film for the element, there is no need for the conventional process of forming the protective film 11g by CvD separately from the field plate film, thereby simplifying the manufacturing process.

更に、フィールドプレート［１２７は抵抗性であるため
、静電気等によりゲート酸化膜中に自然に充電される電
荷を常に放電することができる。このため、Ｄ？！気に
起因するゲート酸化膜破壊が防止され、信頼姓の高い素
子が得られる。Furthermore, since the field plate [127 is resistive, it is possible to constantly discharge charges that are naturally accumulated in the gate oxide film due to static electricity or the like. For this reason, D? ! Destruction of the gate oxide film due to air pollution is prevented, and a highly reliable device can be obtained.

実施例ではＭＯＳＦＥＴについて説明したが、本発明は
バイポーラ型ＭＯ８ＦＥＴやバイポーラトランジスタ等
に適用して同様の効果が得られる。In the embodiment, a MOSFET has been described, but the present invention can be applied to a bipolar MO8FET, a bipolar transistor, etc. to obtain similar effects.

［発明の効果］ 以上説明したように本発明によれば、本来高耐圧化のた
めに形成される抵抗性フィールドプレート膜をそのまま
素子の表面保ｍ１ｌｌとして用いることにより、簡単な
工程で信頼性の高い高耐圧ブレーナ型半導体素子を得る
ことができる。[Effects of the Invention] As explained above, according to the present invention, by using the resistive field plate film originally formed for high breakdown voltage as it is as the surface protection layer of the element, reliability can be improved with a simple process. A high breakdown voltage Brainer type semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）（ｂ）（ｃ）は本発明の一実陥例のＭＯＳ
ＦＥＴを示す平面図とそのＡ−Ａ　−。 Ｂ−Ｂ−新面図、第２図（ａ）（ｂ）（Ｃ）は従来例の
ＭＯＳＦＥＴを示す平面図とそのＡ−Ａ−。 Ｂ−８＝断面図、第３図は他の従来例を示す断面図であ
る。 １１・・・ｎ＋型ドレイン層、１２・・・ｎ−型ドレイ
ン層、１３・・・ｐ型ベース層、１４・・・ｎ＋＋ソー
ス層、１５・・・ゲート酸化層、１６・・・ゲート電極
、１７・・・酸化膜、１８・・・ソース電極（第２の主
電極）、１９・・・金属ゲート電極（制御電極）、２０
・・・ドレイン電極（第１の主電極）、２４・・・酸化
膜、２５・・・ｎ”型層、２６・・・電極、２７・・・
抵抗性フィールドプレート膜。Figures 1 (a), (b), and (c) show a MOS according to an actual example of the present invention.
A plan view showing the FET and its AA-. B-B-New view, FIGS. 2(a), (b), and (C) are plan views showing a conventional MOSFET and its A-A-. B-8 = sectional view, FIG. 3 is a sectional view showing another conventional example. DESCRIPTION OF SYMBOLS 11... N+ type drain layer, 12... N- type drain layer, 13... P type base layer, 14... N++ source layer, 15... Gate oxide layer, 16... Gate electrode , 17... Oxide film, 18... Source electrode (second main electrode), 19... Metal gate electrode (control electrode), 20
... Drain electrode (first main electrode), 24... Oxide film, 25... N'' type layer, 26... Electrode, 27...
Resistive field plate membrane.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子基板の第１の表面に第１の主電極、第２の表
面に第２の主電極および制御電極が設けられ、かつ基板
の第２の表面の周縁部に露出するｐｎ接合上に絶縁膜を
介して抵抗性フィールドプレート膜が設けられた半導体
装置において、前記抵抗性フィールドプレート膜を前記
第２の主電極と制御電極を同時に覆うように配設したこ
とを特徴とする半導体装置。A first main electrode is provided on the first surface of the semiconductor element substrate, a second main electrode and a control electrode are provided on the second surface, and an insulating electrode is provided on the pn junction exposed at the periphery of the second surface of the substrate. A semiconductor device in which a resistive field plate film is provided with a film interposed therebetween, characterized in that the resistive field plate film is disposed so as to cover the second main electrode and the control electrode at the same time.
JP61217509A 1986-09-16 1986-09-16 Semiconductor device Pending JPS6373564A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61217509A JPS6373564A (en) 1986-09-16 1986-09-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61217509A JPS6373564A (en) 1986-09-16 1986-09-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6373564A true JPS6373564A (en) 1988-04-04

Family

ID=16705345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61217509A Pending JPS6373564A (en) 1986-09-16 1986-09-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6373564A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02156572A (en) * 1988-12-08 1990-06-15 Fuji Electric Co Ltd Mos type semiconductor device
US5040042A (en) * 1989-04-28 1991-08-13 Asea Brown Boveri Ltd. Bidirectional semiconductor component that can be turned off
EP0543257A2 (en) * 1991-11-13 1993-05-26 Siemens Aktiengesellschaft Method of manufacturing a power-MISFET
JPH05198816A (en) * 1991-09-27 1993-08-06 Nec Corp Semiconductor device
EP0567341A1 (en) * 1992-04-23 1993-10-27 Siliconix Incorporated Power device with isolated gate pad region
US5349223A (en) * 1993-12-14 1994-09-20 Xerox Corporation High current high voltage vertical PMOS in ultra high voltage CMOS
US5545573A (en) * 1994-06-01 1996-08-13 Mitsubishi Denki Kabushiki Kaisha Method of fabricating insulated gate semiconductor device
US5726472A (en) * 1995-03-31 1998-03-10 Rohm Co., Ltd. Semiconductor device
JP2012054592A (en) * 2004-04-30 2012-03-15 Siliconix Inc Super trench mosfet including embedded source electrode and method of manufacturing the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02156572A (en) * 1988-12-08 1990-06-15 Fuji Electric Co Ltd Mos type semiconductor device
US5040042A (en) * 1989-04-28 1991-08-13 Asea Brown Boveri Ltd. Bidirectional semiconductor component that can be turned off
JPH05198816A (en) * 1991-09-27 1993-08-06 Nec Corp Semiconductor device
EP0543257A2 (en) * 1991-11-13 1993-05-26 Siemens Aktiengesellschaft Method of manufacturing a power-MISFET
EP0543257A3 (en) * 1991-11-13 1994-07-13 Siemens Ag Method of manufacturing a power-misfet
EP0567341A1 (en) * 1992-04-23 1993-10-27 Siliconix Incorporated Power device with isolated gate pad region
US5430314A (en) * 1992-04-23 1995-07-04 Siliconix Incorporated Power device with buffered gate shield region
US5445978A (en) * 1992-04-23 1995-08-29 Siliconix Incorporated Method of making power device with buffered gate shield region
US5349223A (en) * 1993-12-14 1994-09-20 Xerox Corporation High current high voltage vertical PMOS in ultra high voltage CMOS
US5545573A (en) * 1994-06-01 1996-08-13 Mitsubishi Denki Kabushiki Kaisha Method of fabricating insulated gate semiconductor device
US5726472A (en) * 1995-03-31 1998-03-10 Rohm Co., Ltd. Semiconductor device
JP2012054592A (en) * 2004-04-30 2012-03-15 Siliconix Inc Super trench mosfet including embedded source electrode and method of manufacturing the same

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