JPS5916361A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to make the specific resistance uniform by preventing the evaporation and re-distribution of the impurity doped by high temperature heat treatment by a method wherein the grain diameter of a polycrystalline Si film is increased and thus made uniform, and thereafter the polycrystalline Si film is doped with the impurity. CONSTITUTION:The polycrystalline Si film is grown at a low temperature of approx. 620 deg.C by using pressure reduction CVD method (B1). Next, heat treatment is performed at a high temperature of 1,000 deg.C or more for approx. 30min (B2). Then the ion implantation of phosphorus ion is performed to a gate electrode region, and that of arsenic ion to a load resistance element region (B3). After the ion implantation, annealing for approx. 30min in N2 gas is performed at a high temperature of 900 deg.C (B4). The gate electrode of an MOS transistor and a high resistant load element are formed by photoetching method (B5). The condition of high temperature heat treatment is preferable at a high temperature for a short time. The annealing for 2sec-100sec, for example enables to increase the temperature up to 1,200 deg.C-1,400 deg.C and decrease the re-distribution of impurity in an Si substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device including a resistor with high resistance and uniform resistance value suitable for a resistive load MO3 semiconductor integrated circuit device.

Conventionally, MO3 semiconductor integrated circuits (MOS/IC), especially
MOS and LSI devices with high resistance loads have the advantage of small element area and high operating speed, and are widely used. However, the load resistance is required to have a uniform resistance value, which has been a problem in forming LSIs. In other words, to explain the problem in detail, the high resistance element used in conventional MOS and LSI is
is formed, and a polycrystalline silicon film is formed thereon, for example by CV
It was formed by a method of growing by the D method or the like, implanting impurities by ion implantation, activating the implanted impurities by annealing, and determining the resistance value.

The high resistance formed in this way is due to the grain size of the polycrystalline silicon film formed on the surface of the Sio2 film, making it difficult to obtain a constant resistance value even if certain impurities are implanted in a later process. For example, even if the same impurity was implanted in the grain size range of 0.17 zm-0.2 pm, the resistance value varied by 6 to 6 times.

FIG. 1 is a sectional view of a semiconductor device in which a MOS transistor and a load resistor as its circuit structure are integrally formed.

The outline of this device is that the surface of a P-type silicon substrate 1 is separated by a thick insulating film 2, wear-resistant regions 3 and 4 are formed on one side, and a thin insulating film 6 is interposed between these two regions to separate the surface of the P-type silicon substrate 1. MO8 provided with a gate electrode 6 made of a crystalline silicon conductive layer
One end is in contact with an N-type region 7 formed at the other position separated from the +- transistor part by a thick insulating film 2 on the surface, and the other end is on a thick insulating film 2' called a field insulating film. Each of these essential parts is covered with a stabilizing film 9 at the forefront, and is brought into contact with an electrode wiring layer 10 through an opening in the stabilizing film 9 for external circuit connection. This is what made it possible. In addition, external type single pole terminal S.

D and G are the source, train, and gate, respectively, and similarly, R1 and R2 represent both terminals of the resistor.

By the way, the resistor part usually has a thickness of 0.27 zm to
○. The MOj is formed of a polycrystalline silicon layer 8 having a thickness of 6 μm and a sheet resistance of 10 7 to 10 9 Ω/1−.

When used as a load resistor by circuit-coupling with a transistor section, a high resistance value of 10 MΩ to 1x is required. The conventional method for forming such a resistor is to form a polycrystalline silicon layer at a low temperature of about 620°C using a chemical vapor phase reaction method called low pressure CVD method, as shown in the steps shown in FIG. A1), impurity of 1 or less is accurately implanted into this using ion implantation method (A2), annealed (A3), and patterned by photoetching (A4) to obtain a predetermined resistance value. I was trying. However, in the conventional method, the polycrystalline silicon produced at a relatively low temperature is fine particles with a grain size of about 0.1 to 0.2 μm, and the variation is wide, so ion implantation method Even if the introduction of impurities was controlled, the resistance value was not uniform and varied widely.

The present invention provides a method for manufacturing a semiconductor device including a high resistance element with little variation in resistance value.

That is, the present invention prevents evaporation and redistribution of doped impurities caused by high-temperature heat treatment by increasing the grain size of the polycrystalline silicon film to make it uniform and then doping the polycrystalline silicon film with impurities. The purpose is to make the specific resistance uniform.

The present invention adds a high-temperature heat treatment process after polycrystalline silicon is formed to increase the grain size, thereby reducing the variation ratio of the grain size and making it the same as the maximum value of the resistance value in the opening 7). The ratio of the minimum value becomes about 1 to 3 times, which is less than % of the conventional value, and stable device characteristics can be obtained.

An example of the method of the present invention is shown in FIG. 3 below.

1. First, a polycrystalline silicon film with a thickness of about 0.571 m is grown at a low temperature of about 620'C using the low pressure CVD method (B
1). Next, heat treatment is performed at a high temperature of 1000° C. or higher for about 30 minutes (B2).

Here, polycrystalline silicon having a grain size of 0.37 zm or more can be obtained by heat treatment at a high temperature of 1000° C. or more. Next, phosphorus ions were implanted into the gate electrode region at an acceleration energy of 40 KeV and a dose of 1×1015 to 1×1016 IV.
Arsenic ions are implanted at an acceleration energy of 100 KeV and an implantation amount of 1×1013 to 1× in the load resistance element region.
Ions are implanted at a rate of about 10 ions/cm (B3). After the ion implantation, annealing is performed in N2 gas at a temperature of 900° C. for about 30 minutes (B4). Next, a gate electrode of a MOS transistor and a high resistance load element are formed by photoetching (B5).

In this embodiment, arsenic ions are used to form the high resistance load region, but doping may also be performed by phosphorus ion implantation. In that case, the implantation conditions are acceleration energy 40 KeV, iJ
i~1Qi'' pieces//cn12.

In the embodiments of the present invention, in order to make the grain size of polycrystalline silicon as large as possible and stabilize the resistance value, the formation temperature in the polycrystalline deposition step (B1) must be as low as possible, and the high-temperature heat treatment step ( It is desirable to carry out the heat treatment in B2) at as high a temperature as possible. The grain size of polycrystalline silicon increases with increasing temperature above 1000°C. However, when heat treatment is performed at high temperature for a long time, /
Redistribution of impurities in the highly doped region of the silicon substrate or impurities from the gate electrode 4 of the transistor passing through the gate oxide film by diffusion causes problems such as changes in the concentration of the silicon substrate. Therefore, the high temperature heat treatment conditions are preferably high temperature and short time.

For example, annealing for about 2 seconds to 100 seconds using a radiation heating method can raise the temperature to about 1200 DEG C. to 14 DEG C. and reduce the redistribution of impurities in the silicon substrate.

As described above, according to the present invention, by forming a polycrystalline silicon film having a large grain size and then ion-implanting impurities, it is possible to provide a semiconductor device having a resistance with little variation in resistance value.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a resistive load MO3 semiconductor device, FIG. 2 is a process diagram showing a conventional resistor forming method, and FIG. 3 is a process diagram showing a resistor forming method according to the method of the present invention. 1...P-type silicon substrate, 2.2'...
Isolation insulating film, 6... Gate electrode, 8...
...Polycrystalline silicon layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Zumon 05) Rashinswo - Negative beat Ka. Figure 3

Claims (1)

[Claims] A method for manufacturing a semiconductor device, comprising doping crystalline silicon N with an impurity.