JPS5851567A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the integration of a semiconductor device to be formed by opening a connecting port in a self-aligning type, thereby eliminating the necessity of providing a margin in the size between a gate electrode and an SiO2 film for isolating between elements. CONSTITUTION:A polysilicon film 4 is formed on an insulating film 3 on a semiconductor substrate 1, and a photoresist film 11 to be patterned on the film 4 is formed. Then, with the film 11 as a mask the film 4 is removed, and a gate electrode 5 having a width smaller than the width of the film 11 is formed. Further, an Si3N4 film 12 is formed on the substrate 1, the film 11 on the electrode 5 is then removed, and the film 12 on the film 11 is also removed. Then, the periphery of the electrode 5 is thermally oxidized, and the film 12 remaining on the substrate 1 is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a semiconductor device.

A conventional method for manufacturing an MO5 type semiconductor device will be explained using FIGS. 1 to 3. First, P-type silicon (
Sl) A predetermined pattern of silicon dioxide (5iO2
) forming film 2;

After that, gate oxide 1 and 3 are formed on the substrate by thermal oxidation method, and then chemical vaporization is performed on the substrate. A poly-Sl film 4 which will become a gate electrode is formed by (CVD).

After coating a photoresist film (not shown) on the hindlimb substrate, the photoresist film is formed into a predetermined pattern using photolithography, and then the poly-Sl film is formed into a predetermined pattern using the photoresist film to be patterned as a mask. A gate electrode such as 5 in FIG. 2 is formed by shaping by plasma etching.

Thereafter, the surface of the poly-Sl gate electrode is oxidized by thermal oxidation.

Furthermore, phosphorus CP') is applied on the substrate using the gate electrode 5 and the 5to2 film 2 for isolation between elements as masks.
Sos region 1 and drain region 7 are formed by ion-implanting II atoms as shown by the arrows.

Thereafter, as shown in the third factor, phosphosilicate gas (phosphorus silicate gas) (
PSG) Film 11CVD? Since JilCj Rigata tau,
Connection ports 9 and 10 for taking out wiring from the sources [6 and drain region 7] are opened.

By the way, in order to open the aforementioned connection port, for example, a negative photoresist film is coated on the substrate, an exposure mask with a predetermined pattern is placed on the photoresist film, and the photoresist film is exposed in a predetermined pattern. Remove the unexposed portions of the photoresist film.

Using the photoresist film for buttering the hindlimb as a mask, the lower PSG film is etched using hydrofluoric acid (HF) or the like to open the connection port.

However, with such a method, a positional shift may occur when installing the exposure mask, and due to this positional shift, the connection port is not opened above the source region or the drain region, and the connection port is not opened above the gate electrode 5. Inconveniences such as welding occur. So, aw! Gate 1 was prepared with a margin of 100 cm for opening the access hole in advance! An attempt was made to increase the dimension from the end of the pole to the end A of the element isolation 5i02 hood, but such a method has the disadvantage that the element integration if is low.

The object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks.

A method for manufacturing a semiconductor device to achieve such an object includes the steps of forming a double-sided V silicon layer and a gate layer for isolation between elements on a semiconductor substrate, a step of forming a polysilicon hood on the substrate, A step of forming a photoresist film that can be patterned on the polysilicon film, using the photoresist film that can be patterned as a mask to remove unnecessary polysilicon traces in the F section so that the width of the photoresist film that can be patterned is smaller than the width of the photoresist film that can be patterned. a step of forming a wide gate electrode;
- forming a silicon nitride film on the substrate; removing the photoresist film on the gate electrode and also removing the silicon nitride film on the photoresist film; thermally oxidizing the peripheral portion of the gate electrode; a step of removing silicon nitride remaining on the substrate; a step of adding impurity atoms to the substrate to form source and drain regions; a step of forming wiring holes on the substrate; This method is characterized in that it includes a step of patterning the pebble into a predetermined pattern. .

Hereinafter, one embodiment of the present invention will be described in detail using drawings F.

4 to 12 are cross-sectional views showing the steps of the method for manufacturing a semiconductor device of the present invention.

First, as shown in FIG. 4, a 5i02 layer 2 for isolation between elements is formed on, for example, a P-type Si substrate 1 using, for example, a selective oxidation method.

Thereafter, a gate oxide layer 11!3 is formed by a heat treatment method, and then poly-Si[4, which becomes 1[4] is formed on the substrate by a CVD method.

Thereafter, a patterned photoresist WXli having a medium dimension larger than the medium dimension of the gate electrode to be formed is formed on the polysI hood on the gate electrode formation region. To form such a photoresist film, it is preferable to apply the photoresist film on the substrate and then form it using photolithography.

Thereafter, as shown in FIG. 5, using the patterned photoresist film as a mask, the unnecessary poly 5ilJ at the bottom is removed by sputter etching using carbon tetrapartite J# (CF4) gas as a reaction gas. In this way, by adjusting the etching time, the reactive gas can enter from the buttered photoresist film to the bottom.
A Kate wire 5 is formed with a medium size smaller than the patterned photoresist film 11.

After that, silicon nitride @1 is deposited on the substrate as shown in Figure @6.
2 is formed by a sputtering method.

After that, the photoresist @ll on S is removed, and the Si@N4 resist 12 on it is also removed. This state is shown in Figure 7. Thereafter, as shown in FIG. 8, the substrate is thermally oxidized to form thick oxides 14 and 13 around the goo. Thereafter, the S i 3N4 film 12 remaining on the etching substrate is removed by a pine vine etching method using CF4 gas as a reaction gas. At this time C
When Nubatsuta etching is performed with F4 reactive gas, Si3N
Since the rate at which 4@ is etched is as fast as that at which 5iOz is etched, the thick 95i02z film around the gate electrode is hardly attacked.

Thereafter, as shown in FIG. 9, using the 5102 film for element isolation as a mask, Pi ions are implanted into the substrate in the direction of the arrow to form the source region 6 and the drain. Bond M, form 7. After that, we used photolithography to form a resist pattern to provide a connection port! As shown in Figure 10, 5i02 around the gate electrode, the source region and the doVin@ region
Taking advantage of the difference in image quality, 5i02% of the source and drain regions are etched using fluorine or the like.

As a result, the Si on the source vA region and the drain region
The surface of the substrate is exposed, and then, as shown in FIG. 11, a wiring width 14 of aluminum (AI) is formed by vapor deposition. By doing this, by predetermining the medium dimension of the gate electrode and the thickness of the 5in2 film 13 formed on the same curve of the gate electrode, the A/ The position where the wiring width is connected to the substrate can be determined automatically, and the connection port does not come into contact with the gate electrode as in the conventional method.

In other words, the connection port is formed using a 7p line method. Furthermore, since there is no need to accommodate an extra margin in the dimension between the gate electrode and the element isolation 5i02 hood to open the connection hole, the 1#@ degree of the formed device is also the same as above.

As shown in FIG. 12, the above-mentioned 4-arrangement N-layer is formed into a predetermined pattern by photolithography and differential etching, and then a passivated PSG [15] is formed on the ItI substrate by CVD. Semiconductor device. Here, 14A in the figure shows a patterned * film.

As described below, there is an advantage that the degree of integration of a semiconductor device formed by the method of the present invention is improved.

[Brief explanation of the drawing]

1 and 3 are cross-sectional views showing the conventional manufacturing process of a single-stage semiconductor device, and FIGS. 4 to 12 are cross-sectional views showing the steps of the manufacturing method of the present invention. be. In the figure, l is a Si substrate, 2 is a 5i02 top for isolation between elements, 3 is a gate oxide film, 4 is a poly-Si back, 5 is a gate electrode, 6 is a source region, 7 is a drain region, 8.15 is a P
SG hood, 9, 1O is connection port, 11.16 is HOF resin)
Top, 12 is S i 3N4 hood, 13 is 5if2"l, 1
4.14A is the wiring width, and A is the end. Figure 1 Figure 2 Figure 3 Flash 41121 51X21 1 Figure 6 Flash Figure 7 Figure 8 Leap Figure 9 Figure 10

Claims (1)

[Claims] A step of forming a polysilicon film on an insulating film on a semiconductor substrate, a step of forming a photoresist film to be patterned on the polysilicon film, and a step of removing the polysilicon film using the photoresist film to be patterned as a mask. forming a gate electrode having a dimension smaller than the width of the photoresist film to be patterned; further forming a silicon nitride film on the substrate; removing the photoresist film on the gate electrode; A semiconductor device characterized by comprising the steps of also removing the silicon nitride hood of the substrate, thermally oxidizing the peripheral portion of the gate electrode, and removing the silicon nitride hood remaining on the substrate. Production method.