KR0167608B1 - Method of making gate electrode of rom - Google Patents
Method of making gate electrode of rom Download PDFInfo
- Publication number
- KR0167608B1 KR0167608B1 KR1019940038146A KR19940038146A KR0167608B1 KR 0167608 B1 KR0167608 B1 KR 0167608B1 KR 1019940038146 A KR1019940038146 A KR 1019940038146A KR 19940038146 A KR19940038146 A KR 19940038146A KR 0167608 B1 KR0167608 B1 KR 0167608B1
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- South Korea
- Prior art keywords
- gate electrode
- etching mask
- forming
- rom
- pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
본 발명은 노광기의 해상력과는 무관하게 패턴간 간격을 최소화할 수 있는 롬의 게이트 전극 제조방법에 관한 것으로, 게이트 전극층 상부에 게이트 전극 패턴 형성을 위한 식각마스크로 감광막 패턴을 형성하는 제1단계; 상기 감광막 패턴 측벽에 플리머를 형성하는 제2단계; 상기 감광막 패턴 및 폴리머를 식각마스크로 상기 게이트 전극층을 선택식각함으로써 게이트 전극간 간격이 상기 감광막 패턴간 간격보다 좁게 되도록 하는 제3단계를 포함하여 이루는 것을 특징으로 한다.The present invention relates to a method for manufacturing a gate electrode of a ROM capable of minimizing the spacing between patterns irrespective of the resolution of the exposure machine, the method comprising: forming a photoresist pattern as an etching mask for forming a gate electrode pattern on the gate electrode layer; Forming a polymer on sidewalls of the photoresist pattern; And selectively etching the gate electrode layer using the photoresist pattern and the polymer as an etch mask to make the gap between the gate electrodes narrower than the gap between the photoresist patterns.
Description
제1도는 낸드(NAND)형 마스크롬의 기본 회로도.1 is a basic circuit diagram of a NAND mask mask.
제2도는 종래방법에 따라 형성된 제1도의 마스크롬의 1스트링의 단면도.2 is a cross-sectional view of one string of mask rom of FIG. 1 formed according to a conventional method.
제3a도 내지 제3d도는 본 발명에 따른 상기 제1도의 마스크롬의 제조 공정 단면도.3A to 3D are sectional views of the process of manufacturing the mask rom of FIG. 1 according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
33 : 폴리실리콘층 34,35' : 감광막 패턴33 polysilicon layer 34,35 ': photosensitive film pattern
본 발명은 롬의 게이트 전극 제조 방법에 관한 것으로, 특히 콘택 형성 없이 워드라인 선택라인(W/L select line)과 롬코드라인(ROM code line) 형성시 워드라인과 워드라인 사이 간격을 최소화 하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate electrode of a ROM, and particularly, to minimize the spacing between a word line and a word line when forming a word line select line and a ROM code line without forming a contact. It is about a method.
콘택-레스(contact-less) 마스크롬(MASKROM)은 콘택홀이 필요 없이 웨이퍼에 이온주입된 불순물의 확산에 의해 스트링이 형성되는 마스크롬을 일컫는다.The contact-less mask ROM refers to a mask ROM in which a string is formed by diffusion of impurities implanted into a wafer without requiring a contact hole.
제1도는 낸드(NAND)형 마스크롬의 기본 회로도로서, 비트라인은 콘택에 의해 메탈라인으로 구성되며, 롬코드(W/LO 내지 W/L7) 및 워드라인 선택(W/L선택1, W/L선택2)은 폴리실리콘 라인으로 구성된다. 즉, 콘택-레스로 연결되어 있다.FIG. 1 is a basic circuit diagram of a NAND type mask ROM, in which a bit line is composed of metal lines by contact, and ROM codes (W / LO to W / L7) and word line selections (W / L selections 1 and W). / L selection2) consists of polysilicon lines. That is, contactless.
한편, 제2도는 종래방법에 따라 형성된 제1도의 마스크롬의 단면도로서, 이를 통하여 종래기술을 개략적으로 설명하면 다음과 같다.On the other hand, Figure 2 is a cross-sectional view of the mask ROM of Figure 1 formed in accordance with the conventional method, through which the prior art will be outlined as follows.
도시된 바와 같이 반도체기판(1) 위에 게이트산화층(2), 게이트폴리실리콘층(3)을 차례로 증착한 다음, 워드라인선택1, 2(11, 12)와 워드라인0 내지 워드라인 7(21 내지 28)의 폴리실리콘라인은 포토리소그래피 공정에 의한 감광막 패턴을 식각마스크로 상기 게이트폴리실리콘층(3), 게이트산화층(2)을 차례로 선택식각함으로써 이루어 진다.As illustrated, the gate oxide layer 2 and the gate polysilicon layer 3 are sequentially deposited on the semiconductor substrate 1, and then word line selection 1, 2 (11, 12) and word lines 0 to word line 7 (21). The polysilicon lines of (28) to (28) are formed by selectively etching the gate polysilicon layer (3) and the gate oxide layer (2) in an etch mask using a photoresist pattern by a photolithography process.
그러나, 상기 종래방법은 노광기의 해상력을 고려할 때, 제2도에 도시한 바와 같이 워드라인과 워드라인 사이의 간격(A)을 0.5㎛ 내지 0.7㎛로 형성해야 하기 때문에 집적도 향상에 저해가 되는 문제점이 있다.However, in the conventional method, when considering the resolution of the exposure machine, as shown in FIG. 2, the distance A between the word line and the word line should be formed to be 0.5 µm to 0.7 µm, which hinders the improvement of the degree of integration. There is this.
상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 본 발명은 노광기의 해상력과는 무관하게 패턴간 간격을 최소화할 수 있는 롬의 게이트 전극 제조 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the problems of the prior art as described above is an object of the present invention to provide a method for manufacturing a gate electrode of the ROM that can minimize the gap between patterns irrespective of the resolution of the exposure machine.
상기 목적을 달성하기 위하여 본 발명은 롬의 게이트 전극 제조 방법에 있어서, 게이트 전극을 이를 전도층 상에 다수의 제1 식각마스크 패턴을 형성하는 제1단계; 상기 제1 식각마스크 패턴 사이에 노출된 상기 전도충 상에 제2 식각마스크 패턴을 형성하여, 상기 제1 식각마스크 페턴과 제2 식각마스의 패턴 사이에 게이트 전극을 이루지 않는 전도층 부분을 노출시키는 제2 단계; 상기 제2 단계에서 노출된 상기 전도층 부분을 선택적으로 제거하는 제3 단계; 및 상기 제1 및 제2 식각마스크 패턴을 제거하는 제4 단계를 포함하는 롬의 게이트 전극 제조 방법을 제공한다.In order to achieve the above object, the present invention provides a method for manufacturing a gate electrode of a ROM, comprising: a first step of forming a plurality of first etching mask patterns on the conductive layer of the gate electrode; Forming a second etching mask pattern on the conductive worm exposed between the first etching mask pattern, exposing a portion of the conductive layer that does not form a gate electrode between the pattern of the first etching mask pattern and the second etching mask. Second step; A third step of selectively removing the conductive layer portion exposed in the second step; And a fourth step of removing the first and second etching mask patterns.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
제3a도 내지 제3d도는 본 발명에 따른 상기 제1도의 마스크롬의 제조 공정 단면도로서, 먼저, 제3a도에 도시된 바와 같이 반도체 기판(31) 위에 게이트 산화층(32)을 형성하고, 폴리실리콘층(33)을 증착한 다음 게이트 전극 형성영역 이외의 영역에 제1 감광막 패턴(34)을 형성한다. 상기 제1 감광막 패턴(34)의 폭(B)은 0.6㎛이며 , 상기 제1 감광막 패턴 간의 간격은 0.9㎛로 형성된다. 상기 제1 감광막 패턴(34)을 대신하여 화학기상증착(CVD)법에 의한 산화막 패턴을 형성할 수도 있다.3A to 3D are cross-sectional views of the manufacturing process of the mask rom of FIG. 1 according to the present invention. First, as shown in FIG. 3A, the gate oxide layer 32 is formed on the semiconductor substrate 31, and then polysilicon is formed. After the layer 33 is deposited, the first photoresist pattern 34 is formed in a region other than the gate electrode formation region. The width B of the first photoresist pattern 34 is 0.6 μm, and the interval between the first photoresist patterns is 0.9 μm. An oxide film pattern may be formed by chemical vapor deposition (CVD) instead of the first photoresist pattern 34.
다음으로, 이후 공정에서 상기 제1 감광막 패턴이 현상용액에 의해 손상되지 않도록 하기 위하여, 상기 제1 감광막 패턴을 120℃ 내지 150℃의 온도하에서 90 내지 200초간 하드베이크(hard-bake)한다. 이때, 하드 베이크 과정에서 감광막 내의 광 활성성분(photo active compound)이 그 기능을 상실하기 때문에, 차후 빛 에너지를 받아도 감광막이 현상용액에 현상되지 않는다.Next, in order to prevent the first photoresist pattern from being damaged by the developing solution in a subsequent process, the first photoresist pattern is hard-baked for 90 to 200 seconds at a temperature of 120 ° C to 150 ° C. At this time, since the photo active compound in the photosensitive film loses its function during the hard bake process, the photosensitive film is not developed in the developing solution even after receiving light energy.
다음으로, 제3b도에 도시된 바와 같이 상기 구조 전체 상부에 감광막(35)을 도포하고, 제 3c도에 도시된 바와 같이 상기 감광막(35)을 선택식각하여 상기 제1 감광막 패턴(34) 사이에 제2 감광막 패턴(35')을 형성한다. 이때, 상기 제2 감광막 패턴의 폭(D)는 0.6㎛이며, 제2 감광막 패턴간의 간격(E)은 1.2㎛로 형성되어, 제1 감광막 패턴(34)과 제2 감광막 패턴의 간격(F)이 0.3㎛ 이하가 되도록 한다.Next, as shown in FIG. 3B, a photoresist film 35 is coated on the entire structure, and as shown in FIG. 3C, the photoresist film 35 is selectively etched to form a gap between the first photoresist film pattern 34. The second photosensitive film pattern 35 'is formed on the substrate. At this time, the width (D) of the second photosensitive film pattern is 0.6㎛, the interval (E) between the second photosensitive film pattern is formed to 1.2㎛, the interval (F) between the first photosensitive film pattern 34 and the second photosensitive film pattern. It should be 0.3 micrometer or less.
다음으로, 상기 제1 및 제2 감광막 패턴(34, 35')을 식각마스크로 상기 폴리실콘층(33)을 식각하고, 상기 제1 및 제2 감광막 패턴을 제거하여 제3d도에 도시된 바와 같이 이웃하는 전극 간의 간격(A')이 0.3㎛인 게이트 전극을 형성한다.Next, the polysilicon layer 33 is etched using the first and second photoresist pattern 34, 35 ′ as an etch mask, and the first and second photoresist pattern are removed, as shown in FIG. 3D. Similarly, a gate electrode having a spacing A 'between neighboring electrodes is 0.3 mu m.
한편, 낸드형 EPROM 형성 공정에서도 콘택-레스 컨트롤 게이트가 사용되므로 본 발명이 적용될 수 있다.On the other hand, since the contact-less control gate is also used in the NAND-type EPROM forming process, the present invention can be applied.
상기와 같이 이루어지는 본 발명은 마스크롬 제조시 패턴간 간격을 줄임으로써 소자의 집적도를 증대시킬 수 있다.According to the present invention made as described above it is possible to increase the degree of integration of the device by reducing the spacing between the patterns when manufacturing the mask rom.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
Claims (4)
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KR1019940038146A KR0167608B1 (en) | 1994-12-28 | 1994-12-28 | Method of making gate electrode of rom |
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KR1019940038146A KR0167608B1 (en) | 1994-12-28 | 1994-12-28 | Method of making gate electrode of rom |
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KR0167608B1 true KR0167608B1 (en) | 1999-01-15 |
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KR100390848B1 (en) * | 1999-06-24 | 2003-07-10 | 주식회사 하이닉스반도체 | method for forming gate electrode of semiconductor device |
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