KR960026891A - Rom gate electrode manufacturing method - Google Patents

Rom gate electrode manufacturing method Download PDF

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Publication number
KR960026891A
KR960026891A KR1019940037660A KR19940037660A KR960026891A KR 960026891 A KR960026891 A KR 960026891A KR 1019940037660 A KR1019940037660 A KR 1019940037660A KR 19940037660 A KR19940037660 A KR 19940037660A KR 960026891 A KR960026891 A KR 960026891A
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KR
South Korea
Prior art keywords
gate electrode
pattern
size
mask
forming
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Application number
KR1019940037660A
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Korean (ko)
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KR0167607B1 (en
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940037660A priority Critical patent/KR0167607B1/en
Publication of KR960026891A publication Critical patent/KR960026891A/en
Application granted granted Critical
Publication of KR0167607B1 publication Critical patent/KR0167607B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 롬의 게이트전극 제조방법에 관한 것으로, 특히 워드라인과 워드라인 사이 간격을 최소화 하기 위해 게이트전극층 상부에 게이트전극 형성을 위한 제1마스크 패턴을 형성하되, 패턴의 크기는 예정된 게이트전극의 크기와 동일하게, 패턴간 간격은 게이트전극의 패턴 크기에 게이트전극간 간격의 2배를 더한 크기가 되도록 하는 제1단계; 상기 제1마스크 패턴 사이에 게이트전극과 크기와 동일한 제2마스크 패턴을 형성하는 제2단계; 상기 제1 및 제2마스크 패턴을 식각마스크로 하여 게이트전극층을 식각하는 제3단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method for manufacturing a gate electrode of a ROM, and in particular, to form a first mask pattern for forming a gate electrode on the gate electrode layer in order to minimize the gap between the word line and the word line, the size of the pattern is a predetermined In the same manner as the size, the inter-pattern spacing is the first step of adding the pattern size of the gate electrode to twice the spacing between the gate electrodes; Forming a second mask pattern having a same size as a gate electrode between the first mask pattern; And etching the gate electrode layer using the first and second mask patterns as etch masks.

Description

롬의 게이트전극 제조방법Rom gate electrode manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A도 내지 제3D도는 본 발명에 따른 상기 제1도의 마스크 롬의 제조과정을 나타내는 공정단면도.3A to 3D are cross-sectional views illustrating a process of manufacturing the mask ROM of FIG. 1 according to the present invention.

Claims (4)

롬의 게이트전극 제조방법에 있어서, 게이트전극층 상부에 게이트전극 형성을 위한 제1마스크 패턴을 형성하되, 패턴의 크기는 예정된 게이트전극의 크기와 동일하게, 패턴간 간격은 게이트 전극의 패턴 크기에 게이트전극간 간격의 2배를 더한 크기가 되도록 하는 제1단계; 상기 제1마스크 패턴 사이에 게이트전극의 크기와 동일한 제2마스크 패턴을 형성하는 제2단계; 상기 제1 및 제2마스크 패턴을 식각마스크로 하여 상기 게이트전극층을 식각하는 제3단계를 포함하여 이루어지는 것을 특징으로 하는 롬의 게이트전극 제조방법.In the method of manufacturing a gate electrode of a ROM, a first mask pattern for forming a gate electrode is formed on the gate electrode layer, and the size of the pattern is the same as that of the predetermined gate electrode, and the spacing between the patterns is equal to the pattern size of the gate electrode. A first step of adding two times the interval between electrodes; Forming a second mask pattern having a size equal to that of a gate electrode between the first mask patterns; And etching the gate electrode layer using the first and second mask patterns as etch masks. 제1항에 있어서, 상기 제1 및 제2마스크 패턴은 감광물질로 이루어지는 것을 특징으로 하는 롬의 게이트전극 제조방법.The method of claim 1, wherein the first and second mask patterns are made of a photosensitive material. 제2항에 있어서, 상기 제1감광막 패턴 형성 후 120 내지 150℃의 온도하에서 90 내지 200초간 하드베이크 하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 롬의 게이트 전극 제조방법.The method of claim 2, further comprising hard baking for 90 to 200 seconds at a temperature of 120 to 150 ° C. after forming the first photoresist pattern. 제1항에 있어서, 상기 제1마스크 패턴은 절연물질로, 제2마스크 패턴은 감광물질로 이루어지는 것을 특징으로 하는 롬의 게이트 전극 제조방법.The method of claim 1, wherein the first mask pattern is made of an insulating material, and the second mask pattern is made of a photosensitive material. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037660A 1994-12-28 1994-12-28 Method of making gate electrode of rom KR0167607B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940037660A KR0167607B1 (en) 1994-12-28 1994-12-28 Method of making gate electrode of rom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940037660A KR0167607B1 (en) 1994-12-28 1994-12-28 Method of making gate electrode of rom

Publications (2)

Publication Number Publication Date
KR960026891A true KR960026891A (en) 1996-07-22
KR0167607B1 KR0167607B1 (en) 1999-01-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940037660A KR0167607B1 (en) 1994-12-28 1994-12-28 Method of making gate electrode of rom

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100370137B1 (en) * 2000-12-29 2003-01-30 주식회사 하이닉스반도체 A array of flat rom cell method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100370137B1 (en) * 2000-12-29 2003-01-30 주식회사 하이닉스반도체 A array of flat rom cell method for fabricating the same

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Publication number Publication date
KR0167607B1 (en) 1999-01-15

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