KR930024152A - Metal layer pattern separation method of semiconductor device - Google Patents

Metal layer pattern separation method of semiconductor device Download PDF

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Publication number
KR930024152A
KR930024152A KR1019920009077A KR920009077A KR930024152A KR 930024152 A KR930024152 A KR 930024152A KR 1019920009077 A KR1019920009077 A KR 1019920009077A KR 920009077 A KR920009077 A KR 920009077A KR 930024152 A KR930024152 A KR 930024152A
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KR
South Korea
Prior art keywords
pattern
metal layer
separation
semiconductor device
region
Prior art date
Application number
KR1019920009077A
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Korean (ko)
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KR950005439B1 (en
Inventor
황재성
한민석
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김광호
삼성전자 주식회사
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Priority to KR1019920009077A priority Critical patent/KR950005439B1/en
Publication of KR930024152A publication Critical patent/KR930024152A/en
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Publication of KR950005439B1 publication Critical patent/KR950005439B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

다수의 영역으로 분리될 패턴금속층 위에 제1 포토레지스트층을 도포하고, 그 위에 절연층을 적층한 후, 다시 제2의 포토레지스트층을 도포하는 단계와, 상기 금속층이 분리 패터닝되도록 분리 영역이 있는 마스크는 그 패턴을 포위하는 또다른 패턴(가상 패턴:dummy pattern)이 함께 포함되어 있고, 상기 제2의 포토레지스트 상에 마스킹 되어 노광 현상 및 식각을 거쳐 상기 금속층을 패터닝 하는 단계로 이루어져, 금속층에 패턴간 분리 영역이 형성되도록 하는 것을 특징으로 하는 반도체 장치의 금속층의 패턴 분리 방법.Applying a first photoresist layer on the patterned metal layer to be divided into a plurality of regions, laminating an insulating layer thereon, and then applying a second photoresist layer, and having a separation region to separate and pattern the metal layer. The mask includes another pattern (dummy pattern) surrounding the pattern, and is masked on the second photoresist to pattern the metal layer through exposure development and etching. The pattern separation method of the metal layer of a semiconductor device characterized by forming the isolation | separation area | region between patterns.

Description

반도체 장치의 금속층 패턴 분리 방법Metal layer pattern separation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도 (a), (b)는 본 발명의 일실시예에 따른 다층 포토레지스트 층에 의한 금속층 패턴 분리 방법을 설명하는 공정도, 제6도는 제5도의 예를 적용한 마스크 패턴 구성도.5 (a) and 5 (b) are process diagrams illustrating a metal layer pattern separation method using a multilayer photoresist layer according to an embodiment of the present invention, and FIG. 6 is a mask pattern configuration diagram to which the example of FIG. 5 is applied.

Claims (3)

다수의 영역으로 패턴 분리될 금속층 위에 제1 포토레지스트층을 도포하고, 그 위에 절연층을 적층한 후, 다시 제2의 포토레지스트층을 도포하는 단계와, 상기 금속층이 분리 패터닝되도록 분리 영역이 있는 마스크는 그 패턴을 포위하는 또다른 패턴(가상 패턴:dummy fattern)이 함께 포함되어 있고, 상기 제2의 포토레지스트상에 마스킹 되어 노광 현상 및 식각을 거쳐 상기 금속층을 패터닝 하는 단계로 이루어져, 금속층에 패턴간 분리 영역이 형성되도록 하는 것을 특징으로 하는 반도체 장치의 금속층의 패턴 분리 방법.Applying a first photoresist layer on the metal layer to be pattern-separated into a plurality of regions, laminating an insulating layer thereon, and then applying a second photoresist layer, and having a separation region to separate and pattern the metal layer. The mask includes another pattern (dummy fattern) surrounding the pattern, and is masked on the second photoresist to pattern the metal layer through exposure and etching. The pattern separation method of the metal layer of a semiconductor device characterized by forming the isolation | separation area | region between patterns. 제1항에 있어서, 상기 다수의 영역은 각각의 분리의 영역이 인접하여 있는 일군의 영역이며, 이 일군의 영역마다 이를 포위하는 분리 영역인 가상 패턴 영역이 형성되도록하여 사진 식각을 행하는 것을 특징으로 하는 반도체 장치의 금속층의 패턴 분리 방법.The method of claim 1, wherein the plurality of areas is a group of areas in which each of the separation areas is adjacent to each other, and the photo etching is performed by forming a virtual pattern area, which is a separation area surrounding each of the groups. The pattern separation method of the metal layer of the semiconductor device. 제1항에 있어서, 상기 다수의 영역은 일정 간격으로 배열되는 라인 형태이며, 이 다수의영역과 이웃한 또다른 패턴 영역과 분리되는 영역에 또다른 분리 패턴인 가상 패턴을 형성하도록 하여 사진 식각을 행하는 것을 특징으로 하는 반도체 장치의 금속층의 패턴 분리 방법.The photolithography process of claim 1, wherein the plurality of regions are in the form of lines arranged at regular intervals, and a photo pattern is formed by forming a virtual pattern, which is another separation pattern, in the region separated from another region adjacent to the plurality of regions. The pattern separation method of the metal layer of a semiconductor device characterized by the above-mentioned. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920009077A 1992-05-27 1992-05-27 Metal layer pattern sepatation method of semiconductor device KR950005439B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920009077A KR950005439B1 (en) 1992-05-27 1992-05-27 Metal layer pattern sepatation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920009077A KR950005439B1 (en) 1992-05-27 1992-05-27 Metal layer pattern sepatation method of semiconductor device

Publications (2)

Publication Number Publication Date
KR930024152A true KR930024152A (en) 1993-12-22
KR950005439B1 KR950005439B1 (en) 1995-05-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100707577B1 (en) * 2005-12-30 2007-04-13 동부일렉트로닉스 주식회사 Pattern for monitoring process defects of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100707577B1 (en) * 2005-12-30 2007-04-13 동부일렉트로닉스 주식회사 Pattern for monitoring process defects of semiconductor device

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Publication number Publication date
KR950005439B1 (en) 1995-05-24

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