KR970017951A - Multiple pattern formation method using the same reticle - Google Patents
Multiple pattern formation method using the same reticle Download PDFInfo
- Publication number
- KR970017951A KR970017951A KR1019950031818A KR19950031818A KR970017951A KR 970017951 A KR970017951 A KR 970017951A KR 1019950031818 A KR1019950031818 A KR 1019950031818A KR 19950031818 A KR19950031818 A KR 19950031818A KR 970017951 A KR970017951 A KR 970017951A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- forming
- film
- interlayer insulating
- photoresist
- Prior art date
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Abstract
본 발명은 동일한 리티클을 사용하여 반도체기판상에 복수의 패턴을 형성하는 반도체장치의 제조방법에 관한 것으로서, 그 방법은 상기 반도체기판상에 층간절연막을 도포하는 공정과; 리터클을 사용하여 소정패턴의 제1감광막을 형성하는 공정과; 상기 소정패턴의 감광막패턴을 마스크로 사용하여 상기 층간절연막을 선택적으로 제거하여 콘택홀을 형성하는 공정과; 상기 콘택홀을 충진하면서 상기 층간절연막상에 패턴대상막을 도포하는 공정과; 상기 동일한 리티클을 사용하여 소정패턴의 제2감광막을 형성하는 공정과, 상기 소정패턴의 제2감광막패턴을 마스크로 사용하여 상기 패턴대상막을 선택적으로 제거하는 공정을 포함한다. 본 발명의 패턴형성방법에 의하면 동일한 리티클을 사용하여 복수의 패턴을 형성할 수 있기 때문에 많은 리티클을 사용할 필요가 없을 뿐만 아니라, 적층에 대한 층대층의 오정렬을 방지할 수 있다.The present invention relates to a method of manufacturing a semiconductor device for forming a plurality of patterns on a semiconductor substrate using the same liticle, the method comprising: applying an interlayer insulating film on the semiconductor substrate; Forming a first photosensitive film having a predetermined pattern by using a ruffle; Forming a contact hole by selectively removing the interlayer insulating layer using the photoresist pattern of the predetermined pattern as a mask; Applying a pattern target film on the interlayer insulating film while filling the contact hole; Forming a second photoresist film of a predetermined pattern using the same liticle; and selectively removing the pattern target film using the second photoresist film pattern of the predetermined pattern as a mask. According to the pattern forming method of the present invention, since a plurality of patterns can be formed using the same rible, it is not necessary to use many ribules, and the misalignment of the layer-to-layer layer for lamination can be prevented.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 따른 패턴형성방법의 공정수순을 보여주는 플로우차트,3 is a flowchart showing the process sequence of the pattern forming method according to the present invention,
제4A도 내지 제4G도는 본 발명의 패턴형성방법을 이용하여 반도체장치를 제조하는 순차적인 제조공정을 보인 단면도이다.4A to 4G are cross-sectional views showing a sequential manufacturing process for manufacturing a semiconductor device using the pattern forming method of the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031818A KR970017951A (en) | 1995-09-26 | 1995-09-26 | Multiple pattern formation method using the same reticle |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950031818A KR970017951A (en) | 1995-09-26 | 1995-09-26 | Multiple pattern formation method using the same reticle |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970017951A true KR970017951A (en) | 1997-04-30 |
Family
ID=66615898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950031818A KR970017951A (en) | 1995-09-26 | 1995-09-26 | Multiple pattern formation method using the same reticle |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970017951A (en) |
-
1995
- 1995-09-26 KR KR1019950031818A patent/KR970017951A/en not_active Application Discontinuation
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