KR960012332A - Method of forming fine pattern of semiconductor device - Google Patents

Method of forming fine pattern of semiconductor device Download PDF

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Publication number
KR960012332A
KR960012332A KR1019940022563A KR19940022563A KR960012332A KR 960012332 A KR960012332 A KR 960012332A KR 1019940022563 A KR1019940022563 A KR 1019940022563A KR 19940022563 A KR19940022563 A KR 19940022563A KR 960012332 A KR960012332 A KR 960012332A
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KR
South Korea
Prior art keywords
etching
lower photoresist
semiconductor device
predetermined
photoresist film
Prior art date
Application number
KR1019940022563A
Other languages
Korean (ko)
Inventor
기 식 최
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940022563A priority Critical patent/KR960012332A/en
Publication of KR960012332A publication Critical patent/KR960012332A/en

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

본 발명은 반도체 소자의 미세패턴 형성방법에 관한 것으로, 새로운 기술 및 장비의 도입없이 이층 구조의 감광막을 이용하되, 각각의 노광 공정시 소정의 노광부분이 중첩되도록 한 다음 식각공정을 통해 중첩된 부분의 감광막 패턴을 남김으로써 최선선폭 이하의 미세패턴을 형성할 수 있도록 한 반도체 소자의 미세패턴 형성 방법에 관한 것이다.The present invention relates to a method for forming a fine pattern of a semiconductor device, using a photosensitive film having a two-layer structure without the introduction of new technologies and equipment, the predetermined portion overlaps during each exposure process and then the overlapped portion through an etching process The present invention relates to a method for forming a micropattern of a semiconductor device in which a micropattern having a maximum line width or less can be formed by leaving a photosensitive film pattern of.

Description

반도체 소자의 미세패턴 형성방법Method of forming fine pattern of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A 내지 제1F도는 본 발명에 따른 반도체 소자의 미세패턴 형성방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a method for forming a fine pattern of a semiconductor device according to the present invention.

Claims (5)

반도체 소자의 미세패턴 형성방법에 있어서, 패턴이 형성될 소정의 층 상부에 하부 감광막을 도포하고 소정의 래티클을 사용하여 상기 하부 감광막을 1차 노광시키는 단계와, 상기 단계로부터 상부 감광막을 도포하고 소정의 래티클을 사용하여 상기 하부 감광막의 노광부분과 소정폭만큼 중첩되도록 2차 노광시키는 단계와, 상기 단계로부터 상기 상부 및 하부 감광막의 노광되지 않은 부분을 1차 식각하여 제거시킨 후, 하부 감광막의 중첩된 부분만 남도록 2차 식각하는 단계와, 상기 단계로부터 잔류된 하부감광막을 마스크로 이용하여 상기 소정의 층을 식각하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.A method of forming a fine pattern of a semiconductor device, comprising: applying a lower photoresist film over a predetermined layer on which a pattern is to be formed, and firstly exposing the lower photoresist film using a predetermined lattice; Performing a secondary exposure to overlap the exposed portion of the lower photoresist film by a predetermined width using a predetermined lattice; and removing the unexposed portions of the upper and lower photoresist films from the step by primary etching and then removing the lower photoresist film. And etching second such that only the overlapped portions of the substrate remain, and etching the predetermined layer by using the lower photoresist film remaining from the above step as a mask. 제1항에 있어서, 상기 상부 및 하부 감광막은 각 1 내지 2㎛ 정도의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.The method of claim 1, wherein the upper and lower photoresist layers are formed to a thickness of about 1 to 2 μm, respectively. 제1항에 있어서, 상기 2차 노광시 래티클의 이동에 의해 상부 및 하부 감광막의 노광부분이 소정부분 중첩되는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.The method of forming a fine pattern of a semiconductor device according to claim 1, wherein the exposed portions of the upper and lower photoresist layers overlap a predetermined portion by the movement of the reticle during the second exposure. 제1항에 있어서, 상기 2차 식각공정은 하부층에 대한 감광막의 식각선택비가 높은 식각방법으로 실시되는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.The method of claim 1, wherein the secondary etching process is performed by an etching method having a high etching selectivity of the photoresist layer with respect to the lower layer. 제1 또는 제4항에 있어서, 상기 2차 식각공정은 전면 식각방법으로 실시되는 것을 특징으로 하는 반도체 소자의 미세패턴 형성방법.The method of claim 1, wherein the secondary etching process is performed by a front surface etching method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940022563A 1994-09-08 1994-09-08 Method of forming fine pattern of semiconductor device KR960012332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940022563A KR960012332A (en) 1994-09-08 1994-09-08 Method of forming fine pattern of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940022563A KR960012332A (en) 1994-09-08 1994-09-08 Method of forming fine pattern of semiconductor device

Publications (1)

Publication Number Publication Date
KR960012332A true KR960012332A (en) 1996-04-20

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KR1019940022563A KR960012332A (en) 1994-09-08 1994-09-08 Method of forming fine pattern of semiconductor device

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KR (1) KR960012332A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100574999B1 (en) * 2004-12-06 2006-04-28 삼성전자주식회사 Method of forming pattern of semiconductor device
KR100896845B1 (en) * 2007-12-18 2009-05-12 주식회사 동부하이텍 Method for forming photo resist pattern for manufacturing a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100574999B1 (en) * 2004-12-06 2006-04-28 삼성전자주식회사 Method of forming pattern of semiconductor device
KR100896845B1 (en) * 2007-12-18 2009-05-12 주식회사 동부하이텍 Method for forming photo resist pattern for manufacturing a semiconductor device

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