JPS57100748A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57100748A
JPS57100748A JP17682580A JP17682580A JPS57100748A JP S57100748 A JPS57100748 A JP S57100748A JP 17682580 A JP17682580 A JP 17682580A JP 17682580 A JP17682580 A JP 17682580A JP S57100748 A JPS57100748 A JP S57100748A
Authority
JP
Japan
Prior art keywords
layer
glass
semiconductor device
spin
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17682580A
Other languages
Japanese (ja)
Inventor
Shohei Shima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17682580A priority Critical patent/JPS57100748A/en
Publication of JPS57100748A publication Critical patent/JPS57100748A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the stepwise disconnection of an upper layer wire in an internal wire of a semiconductor device by laminating interlayer insulating layer between the upper and lower wires with an insulating laye formed by an ordinary vapor growth with a glass layer by a coating method and smoothening the surface. CONSTITUTION:An interlayer insulating layer 33 formed of SiO2 by a CVD method or the like is formed on a wiring pattern 32 formed of aluminum formed on a semiconductor substrate 31 formed of Si or the like and a glass layer 34 is coated by a spin-on glass method on the layer 33. Then, the stepwise part of the pattern 32 is charged to be smoothened. An SiO2 layer 35 is formed by a CVD method further thereon, and spin-on glass layer 34 is annealed by the heating in the step of coating the layer 35, and according no crack occurs. Eventually, the upper wiring layer 36 is formed.
JP17682580A 1980-12-15 1980-12-15 Manufacture of semiconductor device Pending JPS57100748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17682580A JPS57100748A (en) 1980-12-15 1980-12-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17682580A JPS57100748A (en) 1980-12-15 1980-12-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57100748A true JPS57100748A (en) 1982-06-23

Family

ID=16020493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17682580A Pending JPS57100748A (en) 1980-12-15 1980-12-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57100748A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5911647A (en) * 1982-07-12 1984-01-21 Nec Corp Semiconductor device and manufacture thereof
JPS61102754A (en) * 1984-10-26 1986-05-21 Nec Corp Semiconductor device
JPS61216341A (en) * 1985-03-20 1986-09-26 Nec Kyushu Ltd Manufacture of semiconductor device
JPS6230335A (en) * 1985-07-31 1987-02-09 Fujitsu Ltd Manufacture of semiconductor device
JPS62205630A (en) * 1986-03-06 1987-09-10 Seiko Epson Corp Semiconductor device
US4801560A (en) * 1987-10-02 1989-01-31 Motorola Inc. Semiconductor processing utilizing carbon containing thick film spin-on glass
JPH02166751A (en) * 1988-12-21 1990-06-27 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5091340A (en) * 1988-07-19 1992-02-25 Nec Corporation Method for forming multilayer wirings on a semiconductor device
US5155576A (en) * 1990-03-28 1992-10-13 Nec Corporation Semiconductor integrated circuit having a multilayer wiring structure
US5293503A (en) * 1991-09-11 1994-03-08 Nec Corporation Semiconductor device having multilayer metal interconnection
US5399529A (en) * 1992-05-27 1995-03-21 Nec Corporation Process for producing semiconductor devices
US5420068A (en) * 1991-09-27 1995-05-30 Nec Corporation Semiconductor integrated circuit and a method for manufacturing a fully planar multilayer wiring structure

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5911647A (en) * 1982-07-12 1984-01-21 Nec Corp Semiconductor device and manufacture thereof
JPS6362104B2 (en) * 1982-07-12 1988-12-01
JPS61102754A (en) * 1984-10-26 1986-05-21 Nec Corp Semiconductor device
JPS61216341A (en) * 1985-03-20 1986-09-26 Nec Kyushu Ltd Manufacture of semiconductor device
JPS6230335A (en) * 1985-07-31 1987-02-09 Fujitsu Ltd Manufacture of semiconductor device
JPS62205630A (en) * 1986-03-06 1987-09-10 Seiko Epson Corp Semiconductor device
US4801560A (en) * 1987-10-02 1989-01-31 Motorola Inc. Semiconductor processing utilizing carbon containing thick film spin-on glass
US5091340A (en) * 1988-07-19 1992-02-25 Nec Corporation Method for forming multilayer wirings on a semiconductor device
JPH02166751A (en) * 1988-12-21 1990-06-27 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5155576A (en) * 1990-03-28 1992-10-13 Nec Corporation Semiconductor integrated circuit having a multilayer wiring structure
US5293503A (en) * 1991-09-11 1994-03-08 Nec Corporation Semiconductor device having multilayer metal interconnection
US5420068A (en) * 1991-09-27 1995-05-30 Nec Corporation Semiconductor integrated circuit and a method for manufacturing a fully planar multilayer wiring structure
US5399529A (en) * 1992-05-27 1995-03-21 Nec Corporation Process for producing semiconductor devices

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