JPS5739554A - Multilayer wiring method - Google Patents
Multilayer wiring methodInfo
- Publication number
- JPS5739554A JPS5739554A JP11502780A JP11502780A JPS5739554A JP S5739554 A JPS5739554 A JP S5739554A JP 11502780 A JP11502780 A JP 11502780A JP 11502780 A JP11502780 A JP 11502780A JP S5739554 A JPS5739554 A JP S5739554A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- layer
- wire
- gate
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To prevent the stepwise disconnection of a multilayer wire and to perform a multilayer wire having excellent moisture resistance by covering a lower aluminum wire layer with a glass layer having a melting point lower than that of aluminum, softening the glass layer to form an upper aluminum wire layer and forming an aluminum multilayer wire configuration. CONSTITUTION:Source and drain regions 3, 4, a field oxidized film 2 and a gate oxidized film 5 are formed on a substrate 1, and an MOSFET having a polycrystalline Si gate 6 is formed. A phosphorus glass film 7 is formed on the polycrystalline Si gate 6, the phosphorus glass layer is softened by heat treatment, and an aluminum wire layer 8 is then formed. Subsequently, a low melting point glass film 9 of PbO-B2O3-SiO2-ZnO, etc. is deposited. Then, a contacting hole is opened, a primary aluminum is annealed, and then an upper aluminum wire layer 10 is formed. In this manner, an aluminum multilayer wire having no stepwise disconnection and excellent moisture resistance can be formed.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11502780A JPS5739554A (en) | 1980-08-21 | 1980-08-21 | Multilayer wiring method |
NLAANVRAGE8103007,A NL188775C (en) | 1980-08-21 | 1981-06-22 | METHOD FOR MANUFACTURING A SEMI-CONDUCTOR MULTIPLE WIRING LAYER SEPARATED BY INSULATING GLASS LAYERS. |
GB8120808A GB2082838B (en) | 1980-08-21 | 1981-07-06 | Semiconductor device with a zinc oxide glass layer |
FR8115610A FR2489042B1 (en) | 1980-08-21 | 1981-08-12 | SEMICONDUCTOR DEVICE HAVING A MULTI-LAYER INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF |
DE19813132645 DE3132645A1 (en) | 1980-08-21 | 1981-08-18 | SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING MULTILAYER WIRING IN SUCH A |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11502780A JPS5739554A (en) | 1980-08-21 | 1980-08-21 | Multilayer wiring method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5739554A true JPS5739554A (en) | 1982-03-04 |
Family
ID=14652402
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11502780A Pending JPS5739554A (en) | 1980-08-21 | 1980-08-21 | Multilayer wiring method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5739554A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61164045U (en) * | 1986-03-20 | 1986-10-11 |
-
1980
- 1980-08-21 JP JP11502780A patent/JPS5739554A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61164045U (en) * | 1986-03-20 | 1986-10-11 |
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